CDCE18005RGZT

CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Five/Ten Output Clock Programmable Buffer Check for Samples: CDCE18005 FEATURES APPLICATIONS • • • • • • • • 1 • • • • • • • • • • • Universal Input Buffers That Accept LVPECL, LVDS, or LVCMOS Level Signaling Fully Configurable Outputs Including Frequency, Output Format, and Output Skew Output Multiplexer That Serves as a Clock Switch Between the Three Reference Inputs and the Outputs Clock Generation Via AT-Cut Crystal Integrated EEPROM Determines Device Configuration at Power-up Low Additive Jitter Performance Universal Output Blocks Support up to 5 Differential, 10 Single-ended, or Combinations of Differential or Single-ended: – Low Additive Jitter – Output Frequency up to 1.5 GHz – LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes – Independent Output Dividers Support Divide Ratios from 1–80 – Independent limited Coarse Skew Control on all Outputs Flexible Inputs: – Two Universal Differential Inputs Accept Frequencies up to 1500 MHz (LVPECL), 800 MHz (LVDS), or 250 MHz (LVCMOS). – One Auxiliary Input Accepts Crystal. Auxiliary Input Accepts Crystals in the Range of 2 MHz–42 MHz – Clock Generator Mode Using Crystal Input. Typical Power Consumption 1W at 3.3V (see Table 28) Offered in QFN-48 Package ESD Protection Exceeds 2kV HBM Industrial Temperature Range –40°C to 85°C Data Converter and Data Aggregation Clocking Wireless Infrastructure Switches and Routers Medical Electronics Military and Aerospace Industrial Clock Fan-out DESCRIPTION The CDCE18005 is a high performance clock distributor featuring a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for buffering clocks for data converters and high-speed digital signals, the CDCE18005 achieves low additive jitter in the 50 fs RMS (1) range. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz (2) ) and skew relationship via a programmable delay block. If all outputs are configured in singleended mode (e.g. LVCMOS), the CDCE18005 supports up to ten outputs. Each output can select one of three clock input sources. The input block includes two universal differential inputs which support frequencies up to 1500 MHz and an auxiliary input that can be configured to connect to a crystal via an on chip oscillator block. spacer LVCMOS 25MHz LVCMOS 25MHz LVPECL 1.5GHz / LVDS 800MHz LVPECL 800MHz CDCE18005 Crystal 25MHz LVDS 400MHz LVDS 800MHz LVPECL 1.5GHz Figure 1. CDCE18005 Application Example (1) (2) 1 12 kHz to 20 MHz integration bandwidth. Maximum output frequency depends on the output format selected Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2012, Texas Instruments Incorporated CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com DEVICE INFORMATION PACKAGE The CDCE18005 is packaged in a 48-Pin Plastic Quad Flatpack Package with enhanced bottom thermal pad for heat dissipation. The Texas Instruments Package Designator is: RGZ (S-PQFP-N48) 36 25 37 24 Top View Not up to Scale 48 13 1 12 2 GND VCC_CORE VCC_CORE TEST_MODE VCC_OUT TEST_MODE2 TESTOUTA VCC_OUT U0N U0P VCC_OUT SPI_LE Figure 2. 48-Pin QFN Package Outline 36 35 34 33 32 31 30 29 28 27 26 25 NC 37 24 SPI_CLK NC 38 23 SPI_MOSI VCC_CORE 39 22 SPI_MISO NC 40 21 VCC_OUT NC 41 20 U1N VCC_CORE 42 19 U1P 18 VCC_OUT CDCE18005 (Top View) SYNC VBB 48 13 AUX_OUT 1 2 3 4 5 6 7 8 9 10 Submit Documentation Feedback 11 12 Power_Down 14 VCC_OUT 47 U3N VCC_IN_PRI U3P VCC_OUT VCC_OUT PRI_REF- 15 U4N U2P 46 U4P PRI_REF+ 16 VCC_CORE U2N 45 NC 17 SEC_REF+ VCC_IN_AUX 44 SEC_REF- 43 VCC_IN_SEC AUX_IN Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 PIN FUNCTIONS (1) PIN NAME QFN TYPE DESCRIPTION VCC_OUT 8, 11, 15, 18, 21, 26, 29, 32 Power 3.3V Supply for the Output Buffers VCC_CORE 5, 39, 42, 34, 35 Power 3.3V Core Voltage Circuitry VCC_IN_PRI 47 A. Power 3.3V References Input Buffer and Circuitry Supply Voltage. VCC_IN_SEC 1 A. Power 3.3V References Input Buffer and Circuitry Supply Voltage. VCC_IN_AUX 44 A. Power 3.3V Crystal Oscillator Input Circuitry. GND 36 Ground Ground (All internal Ground Pins are connected to the PAD) GND PAD Ground Ground is on Thermal PAD. See Layout recommendation SPI_MISO 22 O 3-state LVCMOS Output that is enabled when SPI_LE is asserted low. It is the serial Data Output to the SPI bus interface SPI_LE 25 I LVCMOS input, control Latch Enable for Serial Programmable Interface (SPI), with Hysteresis in SPI Mode. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level "1". The SPI_LE status also impacts whether the device loads the EEPROM into the device registers at power up. SPI_LE has to be logic "0" before the Power_Down# toggles low-tohigh in order for the EEPROM to load properly. SPI_CLK 24 I LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level "1". SPI_MOSI 23 I LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE18005 for the SPI bus interface. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level "1". TEST_MODE 33 I Pull High or leave unconnected TEST_MODE2 31 I Pull High or leave unconnected Power_Down 12 I Active Low. Power down mode can be activated via this pin. See Table 14 for more details. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level "1". SPI_LE has to be HIGH in order for the rising edge of Power_Down signal to load the EEPROM. SYNC 14 I Active Low. Sync mode can be activated via this pin. See Table 14 for more details. The input has an internal 150-kΩ, pull-up resistor if left unconnected it will default to logic level “1”. AUX_IN 43 I Auxiliary Input is a single ended input including an on-board oscillator circuit so that a crystal may be connected. AUX_OUT 13 O Auxiliary Output LVCMOS level that can be programmed via SPI interface to be driven by Output 2 or Output 3. PRI_REF+ 45 I Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference Clock, PRI_REF– 46 I Universal Input Buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In case of LVCMOS signaling Ground this pin through 1kΩ resistor. SEC_REF+ 3 I Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary Reference Clock, SEC_REF– 2 I Universal Input Buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock. In case of LVCMOS signaling Ground this pin through 1kΩ resistor. TESTOUTA 30 Analog NC 4, 37, 38, 40, 41 VBB 48 U0P:U0N U1P:U1N: U2P:U2N U3P:U3N U4P:U4N 27, 28 19, 20 16,17 9, 10 6, 7 (1) Analog Test Point for Use for TI Internal Testing. Pull Down to GND Via a 1kΩ Resistor. This Pin is not used Analog O Capacitor for the internal termination viltage. Connect to a 1µF Capacitor. The Main outputs of CDCE18005 are user definable and can be any combination of up to 5 LVPECL outputs, 5 LVDS outputs or up to 10 LVCMOS outputs. The outputs are selectable via SPI interface. The power-up setting is EEPROM configurable. The internal memory (EEPROM and RAM) are sourced from various power pins. All VCC connections must be powered for proper functionality of the device. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 3 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com FUNCTIONAL DESCRIPTION PRI_REF Output Divider 0 SEC_REF XTAL / AUX_IN Output Divider 1 Output Divider 2 Output Divider 3 Output Divider 4 /Power_Down U0P U0N U1P U1N U2P U2N U3P U3N U4P U4N /SYNC SPI_LE SPI_CLK SPI_MISO SPI_MOSI Interface & Control EEPROM AUX OUT Figure 3. CDCE18005 Block Diagram The CDCE18005 comprises three primary blocks: the interface and control block, the input block and the output block. In order to determine which settings are appropriate for any specific combination of input/output frequencies, a basic understanding of these blocks is required. The interface and control block determines the state of the CDCE18005 at power-up based on the contents of the on-chip EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE18005 by writing directly to the device registers after power-up. The input block buffers three clock signals, converts them to differential signals, and drives them onto an internal clock distribution bus. The output block provides five separate clock channels that are fully programmable and configurable to select and condition one of four internal clock sources NOTE This Section of the data sheet provides a high-level description of the features of the CDCE18005 for purpose of understanding its capabilities. For a complete description of device registers and I/O, please refer to the Device Configuration Section. 4 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Interface and Control Block The CDCE18005 is a highly flexible and configurable architecture and as such contains a number of registers so that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM determine device configuration at all times. The CDCE18005 implements the SPI Interface Mode. SPI Interface Mode is used to access the device RAM and EEPROM either during normal operation (if the host system provides a native SPI interface) or during device configuration (i.e. device programming). During power up the EEPROM content gets copied into the registers after the detection of a valid device power-up. The EEPROM can be locked enabling the designer to implement a fault tolerant design. Static RAM (Device Registers) Register 8 Register 7 Register 6 /Power_Down /SYNC SPI_LE SPI_CLK SPI_MISO SPI_MOSI Register 5 Interface & Control Device Hardware Register 4 Register 3 Register 2 Register 1 Register 0 EEPROM (Default Configuration) Register 7 Register 6 Register 5 Register 4 Register 3 Register 2 Register 1 Register 0 Figure 4. CDCE18005 Interface and Control Block Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 5 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Input Block The Input Block includes a pair of Universal Input Buffers and an Auxiliary Input. The Input Block buffers the incoming signals and facilitates signal routing to the Internal Clock Distribution bus. The Internal Clock Distribution Bus connects to all output blocks discussed in the next section. Therefore, a clock signal present on the Internal Clock Distribution bus can appear on any or all of the device outputs. 1500 MHz Internal Clock Distribution Bus PRI_REF LVPECL : 1500 MHz LVDS : 800 MHz LVCMOS : 250 MHz SEC_REF 1500 MHz Crystal : 2MHz – 42MHz Figure 5. CDCE18005 Input Block 6 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Output Block Each of the five identical output blocks incorporates an output multiplexer, a clock divider module, and a universal output array as shown. Internal Clock Distribution Bus Output MUX Control Sync Pulse Digital Phase Adjust PRI_REF Output Buffer Control Enable (7 -bits ) UxP SEC_REF /1,2,3,4,5Clock Divider /1 - /8 Module 0/2- 4 LVDS AUX_IN UxN LVPECL Figure 6. CDCE18005 Output Block (1 of 5) Clock Divider Module 0–4 The following shows a simplified version of a Clock Divider Module (CDM). If an individual clock output channel is not used, then the user should disable the CDM and Output Buffer for the unused channel to save device power. Each channel includes two 7-bit registers to control the divide ratio used and the clock phase for each output. Enable Sync Pulse (internally generated) From Output MUX Digital Phase Adjust (7-bits) To Output Buffer /1 - /80 Figure 7. CDCE18005 Output Divider Module (1 of 5) Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 7 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT VCC Supply voltage range -0.5 to 4.6 V VI Input voltage range (3) –0.5 to VCC + 0.5 V VO Output voltage range (3) –0.5 to VCC + 0.5 V Input Current (VI < 0, VI > VCC) ±20 mA Output current for LVPECL/LVCMOS Outputs (0 < VO < VCC) ±50 mA TJ Maximum junction temperature 125 °C Tstg Storage temperature range –65 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All supply voltages have to be supplied simultaneously. The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed. THERMAL CHARACTERISTICS Package Thermal Resistance for QFN (RGZ) Package (1) (2) AIRFLOW (LFM) (1) (2) (3) 8 θJP (°C/W) (3) θJA (°C/W) 0 JEDEC Compliant Board (6X6 VIAs on PAD) 2 28.9 100 JEDEC Compliant Board (6X6 VIAs on PAD) 2 20.4 0 Recommended Layout (7X7 VIAs on PAD) 2 27.3 100 Recommended Layout (7X7 VIAs on PAD) 2 20.3 The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). Connected to GND with 36 thermal vias (0,3 mm diameter). θJP (Junction – Pad) is used for the QFN Package, because the main heat flow is from the Junction to the GND-Pad of the QFN. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS recommended operating conditions for the CDCE18005 device for under the specified Industrial temperature range of –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VCC Supply voltage 3 3.3 3.6 VCC_IN , VCore Analog supply voltage 3 3.3 3.6 PLVPECL REF at 491.52 MHz, Outputs are LVPECL PLVDS REF at 491.52 MHz, Outputs are LVDS PLVCMOS REF at 491.52 MHz, Outputs are LVCMOS POFF REF at 491.52 MHz Output 1 = 491.52 MHz M(LVCMOS = 245 MHz) Output 2 = 245.76 MHz Output 3 = 122.88 MHz Output 4 = 61.44 MHz Output 5 = 30.72 MHz Dividers are disabled. Outputs are disabled. PPD Device is powered down V 1.6 W 1.3 W 1.5 W 0.45 W 20 mW DIFFERENTIAL INPUT MODE (PRI_REF, SEC_REF) VIN Differential input amplitude (VIN – VIN) 0.1 1.3 V VIC Common-mode input voltage 1.0 VCC–0.3 V IIH Differential input current high (no internal termination) VI = VCC, VCC = 3.6 V 20 μA IIL Differential input current low (no internal termination) VI = 0 V, VCC = 3.6 V 20 μA –20 Input Capacitance on PRI_REF, SEC_REF 3 pF CRYSTAL INPUT SPECIFICATIONS On-chip load capacitance 8 Equivalent series resistance (ESR) 10 pF 50 Ω LVCMOS INPUT MODE (SPI_CLK, SPI_MOSI, SPI_LE, Power_Down, SYNC, PRI_REF, SEC_REF ) Low-level input voltage LVCMOS, 0 0.3 VCC V High-level input voltage LVCMOS 0.7 VCC VCC V –1.2 V VIK LVCMOS input clamp voltage VCC = 3 V, II = –18 mA IIH LVCMOS input current VI = VCC, VCC = 3.6 V IIL LVCMOS input (Except PRI_REF and SEC_REF) VI = 0 V, VCC = 3.6 V –10 IIL LVCMOS input (PRI_REF and SEC_REF) VI = 0 V, VCC = 3.6 V –10 CI Input capacitance (LVCMOS signals) VI = 0 V or VCC μA –40 μA 10 μA 3 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 pF 9 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued) recommended operating conditions for the CDCE18005 device for under the specified Industrial temperature range of –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT SPI OUTPUT (MISO) IOH High-level output current VCC = 3.3 V, VO = 1.65 V –30 mA IOL Low-level output current VCC = 3.3 V, VO = 1.65 V 33 mA VOH High-level output voltage for LVCMOS outputs VCC = 3 V, IOH = −100 μA VOL Low-level output voltage for LVCMOS outputs VCC = 3 V, IOL = 100 μA CO Output capacitance on MISO VCC = 3.3 V; VO = 0 V or VCC IOZH IOZL VCC–0.5 V 0.3 3 pF 5 3-state output current VO = VCC , VO = 0 V Termination voltage for reference inputs. IBB = –0.2 mA, Depending on the setting. V μA –5 VBB VBB 0.9 1.9 V INPUT BUFFERS INTERNAL TERMINATION RESISTORS (PRI_REF and SEC_REF) Termination resistance Single ended Ω 50 LVCMOS OUTPUT / AUXILIARY OUTPUT fclk Output frequency, see Figure Below Load = 5 pF to GND VOH High-level output voltage for LVCMOS outputs VCC = min to max IOH = –100 μA VOL Low-level output voltage for LVCMOS outputs VCC = min to max IOL =100 µA IOH High-level output current VCC = 3.3 V VO = 1.65 V –30 mA IOL Low-level output current VCC = 3.3 V VO = 1.65 V 33 mA tpd(LH)/ tpd(HL) Propagation delay from PRI_REF or SEC_REF to Outputs (LVCMOS to LVCMOS) VCC/2 to VCC/2 4 ns tsk(o) Skew, output to output For Y0 to Y4 All Outputs set at 200 MHz, Reference = 200 MHz 75 ps CO Output capacitance on Y0 to Y4 VCC = 3.3 V; VO = 0 V or VCC 5 pF VO = VCC 5 μA VO = 0 V –5 IOZH 3-State LVCMOS output current IOZL IOPDH IOPDL Power Down output current Duty cycle LVCMOS tslew-rate (1) MHz 0.3 V VCC –0.5 μA VO = VCC 25 μA VO = 0 V 5 μA 50% / 50% input duty cycle Output rise/fall slew rate 45% 3.6 55% 5.2 V/ns All typical values are at VCC = 3.3 V, temperature = 25°C LVCMOS 10 250 5 pF Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued) recommended operating conditions for the CDCE18005 device for under the specified Industrial temperature range of –40°C to 85°C PARAMETER MIN TYP (1) TEST CONDITIONS MAX UNIT 800 MHz 550 mV 50 mV LVDS OUTPUT fclk Output frequency Configuration Load (100 Ω) |VOD| Differential output voltage RL = 100 Ω ΔVOD LVDS VOD magnitude change VOS Offset Voltage ΔVOS VOS magnitude change 270 –40°C to 85°C 1.24 V 40 mV Short circuit Vout+ to ground VOUT = 0 27 mA Short circuit Vout– to ground VOUT = 0 27 mA Propagation delay from PRI_REF or SEC_REF to outputs (LVDS to LVDS) Crosspoint to Crosspoint 3.1 ns Skew, output to output For Y0 to Y4 All Outputs set at 200 MHz Reference = 200 MHz 25 ps CO Output capacitance on Y0 to Y4 VCC = 3.3 V; VO = 0 V or VCC IOPDH Power down output current VO = VCC IOPDL Power down output current VO = 0 V Duty cycle 50% / 50% input duty cycle Rise and fall time 20% to 80% of VOUT(PP) 110 160 190 ps Crosspoint to VCC/2 0.9 1.4 1.9 ns tpd(LH)/tpd(HL) tsk(o) tr / tf (2) 5 45% pF 25 μA 5 μA 55% LVCMOS-TO-LVDS tskP_c (1) (2) (3) Output skew between LVCMOS and LVDS outputs (3) All typical values are at VCC = 3.3 V, temperature = 25°C The tsk(o) specification is only valid for equal loading of all outputs. The phase of LVCMOS is lagging in reference to the phase of LVDS. LVDS DC Termination Test 100 Ω Oscilloscope Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 11 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued) recommended operating conditions for the CDCE18005 device for under the specified Industrial temperature range of –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT 1500 MHz LVPECL OUTPUT fclk Output frequency VOH LVPECL high-level output voltage load VCC –1.06 VCC –0.88 VOL LVPECL low-level output voltage load VCC –2.02 VCC –1.58 |VOD| Differential output voltage 610 970 tpd(LH)/ tpd(HL) Propagation delay from PRI_REF or SEC_REF to outputs (LVPECL to LVPECL) Crosspoint to Crosspoint 3.4 ns tsk(o) Skew, output to output For Y0 to Y4 All Outputs set at 200 MHz Reference = 200MHz 25 ps CO Output capacitance on Y0 to Y4 VCC = 3.3 V; VO = 0 V or VCC IOPDH IOPDL tr / tf Configuration load (Figures below) 5 VO = VCC Power Down output current VO = 0 V 45% V V mV pF 25 μA 5 μA Duty Cycle 50% / 50% input duty cycle 55% Rise and fall time 20% to 80% of Voutpp 55 75 135 ps Crosspoint to Crosspoint 0.9 1.1 1.3 ns –150 260 700 ps V LVDS-TO-LVPECL tskP_C Output skew between LVDS and LVPECL outputs LVCMOS-TO-LVPECL tskP_C Output skew between LVCMOS and LVPECL outputs VCC/2 to crosspoint LVPECL HI-SWING OUTPUT VOH LVPECL high-level output voltage load VCC –1.11 VCC –0.87 VOL LVPECL low-level output voltage load VCC –2.06 VCC –1.73 |VOD| Differential output voltage 760 1160 mV tr / tf Rise and fall time 135 ps (1) 20% to 80% of Voutpp 55 75 V All typical values are at VCC = 3.3 V, temperature = 25°C LVPECL AC Termination Test LVPECL DC Termination Test 50 Ω Oscilloscope 50 Ω 150 Ω 150 Ω 50 Ω Oscilloscope 12 Submit Documentation Feedback 50 Ω Vcc-2 Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 V Figure 8. LVPECL Output Swing vs Frequency Figure 10. LVDS Output Swing vs Frequency Figure 11. LVCMOS Output Swing vs Frequency Figure 9. HI Swing LVPECL Output Swing vs Frequency Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 13 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com TIMING REQUIREMENTS over recommended ranges of supply voltage, load and operating free air temperature (unless otherwise noted) PARAMETER MIN TYP MAX UNIT PRI_REF/SEC_REF INPUT REQUIREMENTS fmax For Single ended Inputs ( LVCMOS) on PRI_REF and SEC_REF For Differential Inputs on PRI_REF and SEC_REF 250 MHz 1500 MHz 42 MHz AUX_IN Input REQUIREMENTS fREF AT-Cut Crystal Input 2 Drive level 100 µW Maximum Shunt Capacitance 7 pF 4 ns Power_Down, SYNC REQUIREMENTS tr/ tf Rise and fall time of the Power_Down, SYNC, signal from 20% to 80% of VCC PHASE NOISE ANALYSIS Table 1. Output Phase Noise for a 491.52 MHz External Reference Phase Noise Specifications under following configuration: REF = 491.52 MHz Diff, LVPECL Phase Noise Reference 491.52 MHz LVPECL 491.52 MHz LVDS 245.52 MHz LVCMOS 122.88 MHz Unit 10 Hz -86 -84 -90 -96 dBc/Hz 100 Hz -100 -100 -105 -111 dBc/Hz 1 kHz -108 -109 -115 -121 dBc/Hz 10 kHz -130 -130 -136 -140 dBc/Hz 100 kHz -135 -135 -140 -145 dBc/Hz 1 MHz -138 -142 -143 -148 dBc/Hz 10 MHz -150 -148 -150 -153 dBc/Hz 20 MHz -150 -148 -150 -152 dBc/Hz 84 93 150 206 fs Jitter RMS 10k–20MHz Table 2. Output Phase Noise for a 25 MHz Crystal Reference Phase Noise Specifications under following configuration: REF = 25 MHz, SE:LVCMOS PHASE NOISE LVPECL 25 MHz LVDS 25 MHz LVCMOS 25 MHz UNIT 10 Hz -83 -82 -82 dBc/Hz 100 Hz -115 -116 -115 dBc/Hz 1 kHz -142 -142 -141 dBc/Hz 10 kHz -152 -149 -151 dBc/Hz 100 kHz -155 -151 -155 dBc/Hz 1 MHz -157 -151 -158 dBc/Hz 5 MHz -157 -151 -158 dBc/Hz Jitter RMS 10k–5MHz 275 345 249 fs DEVICE CONFIGURATION The Functional Description Section described three different functional blocks contained within the CDCE18005. Figure 12 depicts these blocks along with a high-level functional block diagram of the circuit elements comprising each block. The balance of this section focuses on a detailed discussion of each functional block from the perspective of how to configure them. 14 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Output Blocks Output Channel 0 Output Channel 1 Input Block Interface & Control Device Registers Output Channel 2 Interface & Control Block Output Channel 3 Output Channel 4 EEPROM Figure 12. CDCE18005 Circuit Blocks Throughout this section, references to Device Register memory locations follow the following convention: Register 5 Register Number (s) 5 4 3 RAM Bit Number (s) 2 5.2 Figure 13. Device Register Reference Convention INTERFACE AND CONTROL BLOCK The Interface and Control Block includes a SPI interface, two control pins, a non-volatile memory array in which the device stores default configuration data, and an array of device registers implemented in Static RAM. This RAM, also called the device registers, configures all hardware within the CDCE18005. SPI (Serial Peripheral Interface) The serial interface of CDCE18005 is a simple bidirectional SPI interface for writing and reading to and from the device registers. It implements a low speed serial communications link in a master/slave topology in which the CDCE18005 is a slave. The SPI consists of four signals: • SPI_CLK: Serial Clock (Output from Master) – the CDCE18005 clocks data in and out on the rising edge of SPI_CLK. Data transitions therefore occur on the falling edge of the clock. • SPI_MOSI: Master Output Slave Input (Output from Master). • SPI_MISO: Master Input Slave Output (Output from Slave). • SPI_LE: Latch Enable (Output from Master). The falling edge of SPI_LE initiates a transfer. If SPI_LE is high, no data transfer can take place. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 15 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com SPI Interface Master The Interface master can be designed using a FPGA or a micro controller. The CDCE18005 acts as a slave to the SPI master and only supports nonconsecutive read and write command. The SPI clock should start and stop with respect to the SPI_LE signal as shown in Figure 14 SPI_MOSI, SPI_CLK and SPI_LE are generated by the SPI Master. SPI_MISO is generated by the SPI slave the CDCE18005. SPI_MISO SPI_MISO SPI_MOSI SPI_MOSI SPI_CLK SPI_CLK SPI_LE SPI_LE SPI_MISO SPI_MOSI SPI_CLK SPI_LE Figure 14. CDCE18005 SPI Read/Write Command SPI Consecutive Read/Write Cycles to the CDCE18005 Figure 15 Illustrates how two consecutive SPI cycles are performed between a SPI Master and the CDCE18005 SPI Slave. SPI Master SPI Slave SPI_MISO SPI_MOSI SPI_CLK SPI_LE Figure 15. Consecutive Read/Write Cycles Writing to the CDCE18005 Figure 16 illustrates a Write to RAM operation. Notice that the latching of the first data bit in the data stream (Bit 0) occurs on the first rising edge of SPI_CLK after SPI_LE transitions from a high to a low. For the CDCE18005, data transitions occur on the falling edge of SPI_CLK. A rising edge on SPI_LE signals to the CDCE18005 that the transmission of the last bit in the stream (Bit 31) has occurred. SPI_CLK Bit 0 SPI_MOSI Bit 1 Bit 29 Bit 30 Bit31 SPI_LE Figure 16. CDCE18005 SPI Write Operation 16 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Reading from the CDCE18005 Figure 17 shows how the CDCE18005 executes a Read Command. The SPI master first issues a Read Command to initiate a data transfer from the CDCE18005 back to the host (see Table 5)This command specifies the address of the register of interest. By transitioning SPI_LE from a low to a high, the CDCE18005 resolves the address specified in the appropriate bits of the data field. The host drives SPI_LE low and the CDCE18005 presents the data present in the register specified in the Read Command on SPI_MISO. SPI_CLK SPI_MOSI Bit31 Bit30 SPI_MISO Bit0 Bit1 SPI_LE Figure 17. CDCE18005 SPI Read Operation Writing to EEPROM After the CDCE18005 detects a power-up and completes a reset cycle, the device copies the contents of the onchip EEPROM into the Device Registers. (SPI_LE signal has to be HIGH in order for the EEPROM to load correctly during the rising edge of Power_Down signal). The host issues one of two special commands shown in Table 6 to copy the contents of Device Registers 0 through 7 (a total of 224 bits) into EERPOM. They include: • Copy RAM to EEPROM – Unlock, Execution of this command can happen many times. • Copy RAM to EEPROM – Lock: Execution of this command can happen only once; after which the EEPROM is permanently locked. After either command is initiated, power must remain stable and the host must not access the CDCE18005 for at least 50 ms to allow the EEPROM to complete the write cycle and to avoid the possibility of EEPROM corruption. SPI CONTROL INTERFACE TIMING t1 t4 t5 SPI_CLK t3 t2 SPI_MOSI Bit0 Bit1 Bit29 Bit30 Bit31 t7 SPI_LE t6 Figure 18. Timing Diagram for SPI Write Command Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 17 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com t4 t5 SPI_CLK t2 SPI_MOSI Bit30 t8 t3 Bit31 SPI_MISO Bit1 Bit0 = 0 Bit2 t7 SPI_LE t6 t9 Figure 19. Timing Diagram for SPI Read Command Table 3. SPI Bus Timing Characteristics SPI BUS TIMINGS PARAMETER MIN TYP MAX UNIT 20 MHz fClock Clock Frequency for the SPI_CLK t1 SPI_LE to SPI_CLK setup time 10 ns t2 SPI_MOSI to SPI_CLK setup time 10 ns t3 SPI_MOSI to SPI_CLK hold time 10 ns t4 SPI_CLK high duration 25 ns t5 SPI_CLK low duration 25 ns t6 SPI_CLK to SPI_LE Hold time 10 ns t7 SPI_LE Pulse Width 20 ns t8 SPI_CLK to MISO data valid 10 ns t9 SPI_LE to SPI_MISO Data Valid 10 ns CDCE18005 SPI Command Structure The CDCE18005 supports four commands issued by the Master via the SPI: • Write to RAM • Read Command • Copy RAM to EEPROM – unlock • Copy RAM to EEPROM – lock Table 4 provides a summary of the CDCE18005 SPI command structure. The host (master) constructs a Write to RAM command by specifying the appropriate register address in the address field and appends this value to the beginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first. The host must issue a Read Command to initiate a data transfer from the CDCE18005 back to the host. This command specifies the address of the register of interest in the data field. 18 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Table 4. CDCE18005 SPI Command Structure Data Field (28 Bits) Register Addr Field (4 Bits) Operation NVM 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 3 2 1 0 0 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 1 2 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 0 3 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 4 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 0 5 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 6 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 0 7 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1 8 Status/Control No X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 0 0 Instruction Read Command No 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A 1 1 1 0 Instruction RAMM EEPROM Unlock (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Instruction RAMM EEPROM Lock 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 (1) CAUTION: After execution of this command, the EEPROM is permanently locked. After locking the EEPROM, device configuration can only be changed via Write to RAM after power-up; however, the EEPROM can no longer be changed The CDCE18005 on-board EEPROM has been factory preset to the default settings listed in the table below. REGISTER DEFAULT SETTING REG0000 8140000 REG0001 8140000 REG0002 8140000 REG0003 8140000 REG0004 8140000 REG0005 0000096 REG0006 0000000 REG0007 9400000 The default configuration programmed in the device is set to: PRI_REF (set to LVPECL) feeding all outputs. Output dividers are set to DIVIDE by 1. All outputs are set to LVPECL. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 19 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Device Registers: Register 0 Address 0x00 Table 5. CDCE18005 Register 0 Bit Definitions RAM BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 0 RESERVED 1 RESERVED EEPROM 2 RESERVED 3 RESERVED 4 OUTMUX0SELX Output 0 5 OUTMUX0SELY Output 0 6 PH0ADJC0 Output 0 EEPROM 7 PH0ADJC1 Output 0 EEPROM 8 PH0ADJC2 Output 0 9 PH0ADJC3 Output 0 10 PH0ADJC4 Output 0 EEPROM 11 PH0ADJC5 Output 0 EEPROM 12 PH0ADJC6 Output 0 EEPROM 13 OUT0DIVRSEL0 Output 0 EEPROM 14 OUT0DIVRSEL1 Output 0 EEPROM 15 OUT0DIVRSEL2 Output 0 16 OUT0DIVRSEL3 Output 0 17 OUT0DIVRSEL4 Output 0 EEPROM 18 OUT0DIVRSEL5 Output 0 EEPROM 19 OUT0DIVRSEL6 Output 0 EEPROM Always Set to "0" for Proper Operation EEPROM EEPROM OUTPUT MUX “0” Select. Selects the Signal driving Output Divider ”0” (X,Y) = 00: PRI_REF, 01: SEC_REF, 10: AUX_IN, 11: Reserved EEPROM EEPROM OUTPUT DIVIDER “0” Ratio Select EEPROM EEPROM 20 OUT0DIVSEL Output 0 21 HiSWINGLVPECL0 Output 0 High Swing LVPECL When set to “1” and Normal Swing when set to “0” – If LVCMOS or LVDS is selected the Output swing will stay at the same level. (1) – If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1” and Normal LVPECL if it is set to “0”. 22 CMOSMODE0PX Output 0 23 CMOSMODE0PY Output 0 24 CMOSMODE0NX Output 0 25 CMOSMODE0NY Output 0 26 OUTBUFSEL0X Output 0 OUTBUFSEL0Y EEPROM EEPROM Coarse phase adjust select for output divider “0” When set to “0”, the divider is disabled When set to “1”, the divider is enabled 27 EEPROM EEPROM EEPROM LVCMOS mode select for OUTPUT “0” Positive Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM LVCMOS mode select for OUTPUT “0” Negative Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM Output 0 OUTPUT TYPE EEPROM EEPROM RAM BITS EEPROM 22 23 24 25 26 27 LVPECL 0 0 0 0 0 1 LVDS 0 1 0 1 1 1 0 0 1 0 LVCMOS Output Disabled See Settings Above* 0 1 0 1 EEPROM * Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs (1) 20 Set Register R0.21 to '0' for LVDS and LVCMOS outputs Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Device Registers: Register 1 Address 0x01 Table 6. CDCE18005 Register 1 Bit Definitions RAM BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 0 RESERVED 1 RESERVED EEPROM 2 RESERVED 3 RESERVED 4 OUTMUX1SELX Output 1 5 OUTMUX1SELY Output 1 6 PH1ADJC0 Output 1 EEPROM 7 PH1ADJC1 Output 1 EEPROM 8 PH1ADJC2 Output 1 9 PH1ADJC3 Output 1 10 PH1ADJC4 Output 1 EEPROM 11 PH1ADJC5 Output 1 EEPROM 12 PH1ADJC6 Output 1 EEPROM 13 OUT1DIVRSEL0 Output 1 EEPROM 14 OUT1DIVRSEL1 Output 1 EEPROM 15 OUT1DIVRSEL2 Output 1 16 OUT1DIVRSEL3 Output 1 17 OUT1DIVRSEL4 Output 1 EEPROM 18 OUT1DIVRSEL5 Output 1 EEPROM 19 OUT1DIVRSEL6 Output 1 EEPROM Always St "0" for Proper Operation EEPROM EEPROM OUTPUT MUX “1” Select. Selects the Signal driving Output Divider ”1” (X,Y) = 00: PRI_REF, 01:SEC_REF, 10:AUX_IN, 11:Reserved EEPROM EEPROM OUTPUT DIVIDER “1” Ratio Select EEPROM EEPROM 20 OUT1DIVSEL Output 1 21 HiSWINGLVPECL1 Output 1 High Swing LVPECL When set to “1” and Normal Swing when set to “0” – If LVCMOS or LVDS is selected the Output swing will stay at the same level. (1) – If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1” and Normal LVPECL if it is set to “0”. 22 CMOSMODE1PX Output 1 23 CMOSMODE1PY Output 1 24 CMOSMODE1NX Output 1 25 CMOSMODE1NY Output 1 26 OUTBUFSEL1X Output 1 OUTBUFSEL1Y Output 1 EEPROM EEPROM Coarse phase adjust select for output divider “1” When set to “0”, the divider is disabled When set to “1”, the divider is enabled 27 EEPROM EEPROM EEPROM LVCMOS mode select for OUTPUT “1” Positive Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM LVCMOS mode select for OUTPUT “1” Negative Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM OUTPUT TYPE EEPROM EEPROM RAM BITS EEPROM 22 23 24 25 26 27 LVPECL 0 0 0 0 0 1 LVDS 0 1 0 1 1 1 See Settings Above* 0 0 1 0 LVCMOS Output Disabled 0 1 0 1 EEPROM * Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs (1) Set Register R1.21 to '0' for LVDS and LVCMOS outputs Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 21 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Device Registers: Register 2 Address 0x02 Table 7. CDCE18005 Register 2 Bit Definitions RAM BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 0 RESERVED 1 RESERVED EEPROM 2 RESERVED 3 RESERVED 4 OUTMUX2SELX Output 2 5 OUTMUX2SELY Output 2 6 PH2ADJC0 Output 2 EEPROM 7 PH2ADJC1 Output 2 EEPROM 8 PH2ADJC2 Output 2 9 PH2ADJC3 Output 2 10 PH2ADJC4 Output 2 EEPROM 11 PH2ADJC5 Output 2 EEPROM 12 PH2ADJC6 Output 2 EEPROM 13 OUT2DIVRSEL0 Output 2 EEPROM 14 OUT2DIVRSEL1 Output 2 EEPROM 15 OUT2DIVRSEL2 Output 2 16 OUT2DIVRSEL3 Output 2 17 OUT2DIVRSEL4 Output 2 EEPROM 18 OUT2DIVRSEL5 Output 2 EEPROM 19 OUT2DIVRSEL6 Output 2 EEPROM Always Set to "0" for Proper Operation EEPROM EEPROM OUTPUT MUX “2” Select. Selects the Signal driving Output Divider ”2” (X,Y) = 00: PRI_REF, 01:SEC_REF, 10:AUX_IN, 11:Reserved EEPROM EEPROM OUTPUT DIVIDER “2” Ratio Select EEPROM EEPROM 20 OUT2DIVSEL Output 2 21 HiSWINGLVPEC2 Output 2 High Swing LVPECL When set to “1” and Normal Swing when set to “0” – If LVCMOS or LVDS is selected the Output swing will stay at the same level. (1) – If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1” and Normal LVPECL if it is set to “0”. 22 CMOSMODE2PX Output 2 23 CMOSMODE2PY Output 2 24 CMOSMODE2NX Output 2 25 CMOSMODE2NY Output 2 26 OUTBUFSEL2X Output 2 OUTBUFSEL2Y EEPROM EEPROM Coarse phase adjust select for output divider “2” When set to “0”, the divider is disabled When set to “1”, the divider is enabled 27 EEPROM EEPROM EEPROM LVCMOS mode select for OUTPUT “2” Positive Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM LVCMOS mode select for OUTPUT “2” Negative Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM Output 2 OUTPUT TYPE EEPROM EEPROM RAM BITS EEPROM 22 23 24 25 26 27 LVPECL 0 0 0 0 0 1 LVDS 0 1 0 1 1 1 0 0 1 0 LVCMOS See Settings Above* Output Disabled 0 1 0 1 EEPROM * Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs (1) 22 Set Register R2.21 to '0' for LVDS and LVCMOS outputs Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Device Registers: Register 3 Address 0x03 Table 8. CDCE18005 Register 3 Bit Definitions RAM BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 0 RESERVED 1 RESERVED EEPROM 2 RESERVED 3 RESERVED 4 OUTMUX3SELX Output 3 5 OUTMUX3SELY Output 3 6 PH3ADJC0 Output 3 EEPROM 7 PH3ADJC1 Output 3 EEPROM 8 PH3ADJC2 Output 3 9 PH3ADJC3 Output 3 10 PH3ADJC4 Output 3 EEPROM 11 PH3ADJC5 Output 3 EEPROM 12 PH3ADJC6 Output 3 EEPROM 13 OUT3DIVRSEL0 Output 3 EEPROM 14 OUT3DIVRSEL1 Output 3 EEPROM 15 OUT3DIVRSEL2 Output 3 16 OUT3DIVRSEL3 Output 3 17 OUT3DIVRSEL4 Output 3 EEPROM 18 OUT3DIVRSEL5 Output 3 EEPROM 19 OUT3DIVRSEL6 Output 3 EEPROM Always Set to "0" for Proper Operation EEPROM EEPROM OUTPUT MUX “3” Select. Selects the Signal driving Output Divider ”3” (X,Y) = 00: PRI_REF, 01:SEC_REF, 10:AUX_IN, 11:Reserved EEPROM EEPROM OUTPUT DIVIDER “3” Ratio Select EEPROM EEPROM 20 OUT3DIVSEL Output 3 21 HiSWINGLVPEC3 Output 3 High Swing LVPECL When set to “1” and Normal Swing when set to “0” – If LVCMOS or LVDS is selected the Output swing will stay at the same level. (1) – If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1” and Normal LVPECL if it is set to “0”. 22 CMOSMODE3PX Output 3 23 CMOSMODE3PY Output 3 24 CMOSMODE3NX Output 3 25 CMOSMODE3NY Output 3 26 OUTBUFSEL3X Output 3 OUTBUFSEL3Y Output 3 EEPROM EEPROM Coarse phase adjust select for output divider “3” When set to “0”, the divider is disabled When set to “1”, the divider is enabled 27 EEPROM EEPROM EEPROM LVCMOS mode select for OUTPUT “3” Positive Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM LVCMOS mode select for OUTPUT “3” Negative Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM OUTPUT TYPE EEPROM EEPROM RAM BITS EEPROM 22 23 24 25 26 27 LVPECL 0 0 0 0 0 1 LVDS 0 1 0 1 1 1 LVCMOS See Settings Above* 0 0 Output Disabled 0 1 0 1 0 1 EEPROM * Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs (1) Set Register R3.21 to '0' for LVDS and LVCMOS outputs Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 23 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Device Registers: Register 4 Address 0x04 Table 9. CDCE18005 Register 4 Bit Definitions RAM BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 0 RESERVED 1 RESERVED 2 RESERVED 3 RESERVED 4 OUTMUX4SELX Output 4 5 OUTMUX4SELY Output 4 6 PH4ADJC0 Output 4 EEPROM 7 PH4ADJC1 Output 4 EEPROM 8 PH4ADJC2 Output 4 9 PH4ADJC3 Output 4 10 PH4ADJC4 Output 4 EEPROM 11 PH4ADJC5 Output 4 EEPROM 12 PH4ADJC6 Output 4 EEPROM 13 OUT4DIVRSEL0 Output 4 EEPROM 14 OUT4DIVRSEL1 Output 4 EEPROM 15 OUT4DIVRSEL2 Output 4 16 OUT4DIVRSEL3 Output 4 17 OUT4DIVRSEL4 Output 4 EEPROM 18 OUT4DIVRSEL5 Output 4 EEPROM 19 OUT4DIVRSEL6 Output 4 20 OUT4DIVSEL EEPROM EEPROM Must be set to "0" for proper operation EEPROM EEPROM Output 4 OUTPUT MUX “4” Select. Selects the Signal driving Output Divider ”4” (X,Y) = 00: PRI_REF, 01:SEC_REF, 10:SMART_AUX_IN, 11:Reserved EEPROM EEPROM EEPROM Coarse phase adjust select for output divider “4” EEPROM EEPROM OUTPUT DIVIDER “4” Ratio Select EEPROM EEPROM When set to “0”, the divider is disabled When set to “1”, the divider is enabled EEPROM (1) 21 HiSWINGLVPEC4 Output 4 22 CMOSMODE4PX Output 4 23 CMOSMODE4PY Output 4 24 CMOSMODE4NX Output 4 25 CMOSMODE4NY Output 4 26 OUTBUFSEL4X Output 4 27 OUTBUFSEL4Y High Swing LVPECL When set to “1” and Normal Swing when set to “0” – If LVCMOS or LVDS is selected the Output swing will stay at the same level. – If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1” and Normal LVPECL if it is set to “0”. EEPROM LVCMOS mode select for OUTPUT “4” Positive Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM LVCMOS mode select for OUTPUT “3” Negative Pin. (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State EEPROM Output 4 OUTPUT TYPE EEPROM EEPROM RAM BITS EEPROM 22 23 24 25 26 27 LVPECL 0 0 0 0 0 1 LVDS 0 1 0 1 1 1 LVCMOS See Settings Above* 0 0 Output Disabled 0 1 0 1 0 1 EEPROM * Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs (1) 24 Set Register R4.21 to '0' for LVDS and LVCMOS outputs Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Device Registers: Register 5 Address 0x05 Table 10. CDCE18005 Register 5 Bit Definitions RAM BIT BIT NAME RELATED BLOCK 0 INBUFSELX INBUFSELX 1 INBUFSELY INBUFSELY 2 SYNCSEL1 3 SYNCSEL2 Output Divider Synchronizatio n 4 5 6 ACDCSEL DESCRIPTION/FUNCTION Input Buffer Select (LVPECL,LVDS or LVCMOS) XY(01 ) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin EEPROM SYNCSEL(1,2)= 10 :Output divider sync to Primary input SYNCSEL(1,2)= 01 :Output divider sync to Secondary input SYNCSEL(1,2)= 00 :Output divider sync to Auxiliary input EEPROM RESERVED Always Set to "1" for Proper Operation EEPROM RESERVED Always Set to "0" for Proper Operation EEPROM Input Buffers If Set to “1” DC Termination, If set to “0” AC Termination EEPROM EEPROM EEPROM EEPROM 7 HYSTEN Input Buffers If Set to “1” Input Buffers Hysteresis Enabled. It is not recommended that Hysteresis be disabled. 8 PRI_TERMSEL Input Buffers If Set to “0” Primary Input Buffer Internal Termination Enabled If set to “1” Primary Internal Termination circuitry Disabled EEPROM 9 PRIINVBB Input Buffers If Set to “1” Primary Input Negative Pin Biased with Internal VBB Voltage. EEPROM 10 SECINVBB Input Buffers If Set to “1” Secondary Input Negative Pin Biased with Internal VBB Voltage EEPROM 11 FAILSAFE Input Buffers If Set to “1” Fail Safe is Enabled for all Input Buffers configured as LVDS, DC Coupling only. EEPROM 12 RESERVED EEPROM 13 RESERVED EEPROM 14 RESERVED EEPROM 15 RESERVED EEPROM 16 RESERVED EEPROM 17 RESERVED EEPROM 18 RESERVED EEPROM 19 RESERVED 20 RESERVED 21 RESERVED EEPROM 22 RESERVED EEPROM 23 RESERVED EEPROM 24 RESERVED EEPROM 25 RESERVED EEPROM 26 RESERVED EEPROM 27 RESERVED EEPROM ---- Must be set to "0" for proper operation EEPROM EEPROM Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 25 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Device Registers: Register 6 Address 0x06 Table 11. CDCE18005 Register 6 Bit Definitions RAM BIT 26 BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 0 RESERVED EEPROM 1 RESERVED EEPROM 2 RESERVED EEPROM 3 RESERVED EEPROM 4 RESERVED EEPROM 5 RESERVED 6 RESERVED 7 RESERVED EEPROM 8 RESERVED EEPROM 9 RESERVED EEPROM 10 RESERVED EEPROM 11 RESERVED EEPROM Must be set to "0" EEPROM EEPROM Input Buffers If Set to “0” Secondary Input Buffer Internal Termination Enabled If set to “1” Secondary Internal Termination circuitry Disabled 12 SEC_TERMSEL EEPROM 13 RESERVED EEPROM 14 RESERVED EEPROM 15 RESERVED EEPROM 16 RESERVED EEPROM 17 RESERVED 18 RESERVED 19 RESERVED EEPROM 20 RESERVED EEPROM 21 RESERVED EEPROM 22 RESERVED EEPROM 23 RESERVED 24 AUXOUTEN EEPROM Must be set to "0" EEPROM EEPROM Output AUX Enable Auxiliary Output when set to “1” EEPROM Output AUX Select the Output that will driving the AUX Output; Low for Selecting Output Divider “2” and High for Selecting Output Divider “3” EEPROM 25 AUXFEEDSEL 26 RESERVED Must be set to "0" EEPROM 27 RESERVED Must be set to "0" EEPROM Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Device Registers: Register 7 Address 0x07 Table 12. CDCE18005 Register 7 Bit Definitions RAM BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 0 RESERVED EEPROM 1 RESERVED EEPROM 2 RESERVED EEPROM 3 RESERVED EEPROM 4 RESERVED EEPROM 5 RESERVED EEPROM 6 RESERVED EEPROM 7 RESERVED EEPROM 8 RESERVED EEPROM 9 RESERVED EEPROM 10 RESERVED 11 RESERVED 12 RESERVED EEPROM 13 RESERVED EEPROM 14 RESERVED EEPROM 15 RESERVED EEPROM 16 RESERVED EEPROM 17 RESERVED EEPROM 18 RESERVED EEPROM 19 RESERVED EEPROM 20 RESERVED EEPROM 21 RESERVED 22 TESTMUX1 23 RESERVED 24 TEXTMUX2 25 RESERVED 26 EPUNLOCK Status If it reads "0" the EEPROM is unlocked. If it reads "1" the EEPROM is Locked RAM 27 EPSTATUS Status Read only; always reads "1" RAM EEPROM Always Set to "0" for Proper Operation EEPROM EEPROM Diagnostics Diagnostics Set to “1” EEPROM Always Set to "0" for Proper Operation EEPROM Set to “1” EEPROM Always Set to "0" for Proper Operation EEPROM Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 27 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Device Registers: Register 8 Address 0x08 Table 13. CDCE18005 Register 8 Bit Definitions (1) RAM BIT (1) 28 BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 0 RESERVED RAM 1 RESERVED RAM 2 RESERVED 3 RESERVED 4 RESERVED RAM 5 RESERVED RAM 6 RESERVED 7 SLEEP Status Set Device Sleep mode On when set to “0”, Normal Mode when set to “1” RAM 8 SYNC Status If set to “0” this bit forces “SYNC ; Set to “1” to exit the Synchronization State. RAM 9 RESERVED Must be set to "0" RAM 10 VERSION0 Silicon Revision RAM 11 VERSION1 Silicon Revision RAM 12 VERSION2 Silicon Revision RAM 13 RESERVED RAM 14 RESERVED RAM 15 RESERVED RAM 16 RESERVED RAM 17 RESERVED RAM 18 RESERVED RAM 19 RESERVED 20 RESERVED 21 RESERVED RAM 22 RESERVED RAM 23 RESERVED RAM 24 RESERVED RAM 25 RESERVED RAM 26 RESERVED RAM 27 RESERVED RAM RAM TI Test Registers. For TI Use Only RAM RAM RAM TI Test Registers. For TI Use Only RAM All reserved Bits can be set to "0" when writing to Register 8 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Device Control Figure 20 provides a conceptual explanation of the CDCE18005 Device operation. Table 14 defines how the device behaves in each of the operational states. Device OFF Power Applied Power ON Reset Sleep Sleep = OFF Power Down = OFF Power Down = ON Delay Finished Sleep = ON Sync = ON Power Down = ON Power Down Sync Active Mode Sync = OFF Figure 20. CDCE18005 Device State Control Diagram Table 14. CDCE18005 Device State Definitions Status State Device Behavior Power-On Reset After device power supply reaches approximately 2.35V, the contents of EEPROM are copied into the Device Registers within 100 ns, thereby initializing the device hardware. Active Mode Normal Operation Entered Via Exited Via SPI Port Output Divider Output Buffer Power applied to the device or upon exit from Power Down State via the Power_Down pin set HIGH. Power On Reset and EEPROM loading delays are finished OR the Power_Down pin is set LOW. OFF Disabled OFF Sync = OFF (from Sync State). Sync, Power Down, Sleep, or Manual Recalibration activated. ON Disabled or Enabled HI-Z or Enabled Power_Down pin is pulled LOW. Power_Down pin is pulled HIGH. ON Disabled HI-Z Power Down Used to shut down all hardware and Resets the device after exiting the Power Down State. Therefore, the EEPROM contents will eventually be copied into RAM after the Power Down State is exited. Identical to the Power Down State except the EEPROM contents are not copied into RAM. SLEEP bit in device register 8 bit 7 is set LOW. SLEEP bit in device register 8 bit 7 is set HIGH. ON Disabled HI-Z Sleep Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 29 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Table 14. CDCE18005 Device State Definitions (continued) Status State Sync Device Behavior Entered Via Sync synchronizes all output dividers so that they begin counting at the same time. Note: this operation is performed automatically each time a divider register is accessed. Exited Via SYNC Bit in device register 8 bit 8 is set LOW or SYNC pin is pulled LOW SPI Port Output Divider Output Buffer ON Disabled HI-Z SYNC Bit in device register 8 bit 8 is set HIGH or SYNC pin is pulled HIGH External Control Pins Power_Down The Power_Down pin places the CDCE18005 into the power down state. Additionally, the CDCE18005 loads the contents of the EEPROM into RAM after the Power_Down pin is de-asserted; therefore, it is used to initialize the device after power is applied. SPI_LE signal has to be HIGH in order for EEPROM to load correctly during the rising edge of Power_Down. SYNC The SYNC pin (Active LOW) has a complementary register location located in Device Register 8 bit 8. When enabled, Sync synchronizes all output dividers so that they begin counting simultaneously. Further, SYNC disables all outputs when in the active State. INPUT BLOCK The Input Block includes two Universal Input Buffers, an Auxiliary Input. The Input Block drives three different clock signals onto the Internal Clock Distribution Bus. 1500 MHz Internal Clock Distribution Bus PRI_REF LVPECL : 1500 MHz LVDS : 800 MHz LVCMOS : 250 MHz SEC_REF Crystal : 2 MHz – 42 MHz 1500 MHz XTAL / AUX_IN Figure 21. CDCE18005 Input Block With References to Registers 30 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Universal Input Buffers (UIB) Figure 22 shows the key elements of a universal input buffer. A UIB supports multiple formats along with different termination and coupling schemes. The CDCE18005 implements the UIB by including on board switched termination, a programmable bias voltage generator, and an output multiplexer. The CDCE18005 provides a high degree of configurability on the UIB to facilitate most existing clock input formats. PRI_REF PINV PN PP 50 Ω 50 Ω 50 Ω 50 Ω SN SP Register 6 12 Vbb Register 5 10 9 8 Vbb 1 mF Settings 5.1 5.0 5.6 Nominal INBUFSELY INBUFSELX ACDCSEL Vbb 1 0 0 1.9V 1 0 1 1.2V 1 1 0 1.2V 1 1 1 1.2V Universal Input Control 7 6 1 0 SINV 5.0 INBUFSELX 0 X X X SEC_REF Settings 5.1 5.8, 6.12 INBUFSELY TERMSEL 0 X X 1 1 0 1 0 SWITCH Status 5.9,5.10 INVBB X X 0 1 P OFF OFF ON ON N OFF OFF ON ON INV OFF OFF ON OFF Figure 22. CDCE18005 Universal Input Buffer Table 15 lists several settings for many possible clock input scenarios. Note that the two universal input buffers share the Vbb generator. Therefore, if both inputs use internal termination, they must use the same configuration mode (LVDS, LVPECL, or LVCMOS). If the application requires different modes (e.g. LVDS and LVPECL) then one of the two inputs must implement external termination. Table 15. CDCE18005 Universal Input Buffer Configuration Matrix PRI_REF CONFIGURATION MATRIX SETTINGS Register.Bit → Bit Name → CONFIGURATION 5.7 5.1 5.0 5.8 5.9 5.6 HYSTEN INBUFSELY INBUFSELX PRI_TERMSEL PRIINVBB ACDCSEL Hysteresis Mode Coupling Termination 1 0 0 X X X ENABLED LVCMOS DC N/A — 1 1 0 0 0 0 ENABLED LVPECL AC Internal 1.9V 1 1 0 0 0 1 ENABLED LVPECL DC Internal 1.2V 1 1 0 1 X X ENABLED LVPECL — External — 1 1 1 0 0 0 ENABLED LVDS AC Internal 1.2V 1 1 1 0 0 1 ENABLED LVDS DC Internal 1.2V 1 1 1 1 X X ENABLED LVDS — External — 0 X X X X X OFF — — — — 1 X X X X X ENABLED — — — — Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 Vbb 31 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Table 15. CDCE18005 Universal Input Buffer Configuration Matrix (continued) PRI_REF CONFIGURATION MATRIX SETTINGS Register.Bit → Bit Name → CONFIGURATION 5.7 5.1 5.0 5.8 5.9 5.6 HYSTEN INBUFSELY INBUFSELX PRI_TERMSEL PRIINVBB ACDCSEL Hysteresis Mode Coupling Termination Vbb SEC_REF CONFIGURATION MATRIX SETTINGS Register.Bit → Bit Name → CONFIGURATION 5.7 5.1 5.0 6.12 5.10 5.6 HYSTEN INBUFSELY INBUFSELX SEC_TERMSEL SECINVBB ACDCSEL Hysteresis Mode Coupling Termination 1 0 0 X X X ENABLED LVCMOS DC N/A — 1 1 0 0 0 0 ENABLED LVPECL AC Internal 1.9V 1 1 0 0 0 1 ENABLED LVPECL DC Internal 1.2V 1 1 0 1 X X ENABLED LVPECL — External — 1 1 1 0 0 0 ENABLED LVDS AC Internal 1.2V 1 1 1 0 0 1 ENABLED LVDS DC Internal 1.2V 1 1 1 1 X X ENABLED LVDS — External — 0 X X X X X OFF — — — — 1 X X X X X ENABLED — — — — Vbb LVDS Fail Safe Mode Differential data line receivers can switch on noise in the absence of an input signal. This occurs when the clock driver is turned off or the interconnect is damaged or missing. Traditionally the solution to this problem involves incorporating an external resistor network on the receiver input. This network applies a steady-state bias voltage to the input pins. The additional cost of the external components notwithstanding, the use of such a network lowers input signal magnitude and thus reduces the differential noise margin. The CDCE18005 provides internal failsafe circuitry on all LVDS inputs if enabled as shown in Table 16 for DC termination only. Table 16. LVDS Failsafe Settings Bit Name → Register.Bit → FAILSAFE 5.11 LVDS Failsafe 0 Disabled for all inputs 1 Enabled for all inputs OUTPUT BLOCK The output block includes five identical output channels. Each output channel comprises an output multiplexer, a clock divider module, and a universal output buffer as shown in Figure 23. Registers 0 - 4 5 Output MUX Control Internal Clock Distribution Bus Registers 0 - 4 4 27 26 25 24 23 22 21 Sync Pulse Output Buffer Control Enable PRI_REF UxP SEC_REF AUX_IN Clock Divider Module 0 - 4 LVDS UxN LVPECL Figure 23. CDCE18005 Output Channel 32 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Output Multiplexer Control The output multiplexer selects which of the four clock sources available on the Internal Clock Distribution Bus will be presented to the Clock Divider Module. For a description of these clock sources, see Figure 21. Table 17. CDCE18005 Output Multiplexer Control Settings OUTPUT MULTIPLEXER CONTROL Register n (n = 0,1,2,3,4) OUTMUXnSELX n.4 OUTMUXnSELY n.5 0 0 PRI_REF 0 1 SEC_REF 1 0 AUX_IN 1 1 Reserved CLOCK SOURCE SELECTED Output Buffer Control Each of the five output channels includes a programmable output buffer; supporting LVPECL, LVDS, and LVCMOS modes. Table 18 lists the settings required to configure the CDCE18005 for each output type. Registers 0 through 4 correspond to Output Channels 0 through 4 respectively. Table 18. CDCE18005 Output Buffer Control Settings OUTPUT BUFFER CONTROL Register n (n = 0,1,2,3,4) OUTPUT TYPE CMOSMODEnPX CMOSMODEnPY CMOSMODEnNX CMOSMODEnNY OUTBUFSELnX OUTBUFSELnY n.22 n.23 n.24 n.25 n.26 n.27 0 0 0 0 0 1 0 1 0 1 1 1 LVDS 0 0 LVCMOS 1 0 HI-Z See LVCMOS Output Buffer Configuration Settings 0 1 0 1 LVPECL Output Buffer Control – LVCMOS Configurations A LVCMOS output configuration requires additional configuration data. In the single ended configuration, each Output Channel provides a pair of outputs. The CDCE18005 supports four modes of operation for single ended outputs as listed in Table 19. Table 19. LVCMOS Output Buffer Configuration Settings OUTPUT BUFFER CONTROL – LVCMOS CONFIGURATION Register n (n = 0,1,2,3,4) Output Type Pin 0 LVCMOS Negative Active – Non-inverted 0 LVCMOS Negative Hi-Z 0 0 LVCMOS Negative Active – Non-inverted 1 0 0 LVCMOS Negative Low X X 0 0 LVCMOS Positive Active – Non-inverted 1 X X 0 0 LVCMOS Positive Hi-Z 1 0 X X 0 0 LVCMOS Positive Active – Non-inverted 1 1 X X 0 0 LVCMOS Positive Low CMOSMODEnPX CMOSMODEnPY CMOSMODEnNX CMOSMODEnNY OUTBUFSELnX OUTBUFSELnY n.22 n.23 n.24 n.25 n.26 n.27 X X 0 0 0 X X 0 1 0 X X 1 0 X X 1 0 0 0 Output Mode Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 33 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Output Dividers Figure 24 shows that each output channel provides a 7-bit divider and digital phase adjust block. Table 20 lists the divide ratios supported by the output divider for each output channel. The output divider’s maximum input frequency is limited to 1.175GHz. If the divider is bypassed (divide ratio = 1) then the maximum frequency of the output channel is 1.5GHz. Registers 0 - 4 Register 5 3 12 11 10 9 2 8 7 6 Select PRI_REF SEC_REF AUX_IN Divider Sync From Output MUX Digital Phase Adjust (7-bits) Output Divider (7-bits) To Output Buffer Registers 0 - 4 19 18 17 16 15 14 13 Figure 24. CDCE18005 Output Divider and Phase Adjust 34 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Table 20. CDCE18005 Output Divider Settings Output Divide Ratio 3** 6 1 4 – 4 8 1 1 5 – 5 10 1 1 3 2 6 6 1 0 1 4 2 8 8 0 1 1 1 5 2 10 10 1 0 1 1 3 4 12 12 0 1 1 0 1 4 4 16 16 0 0 1 1 1 1 5 4 20 20 0 1 0 0 1 1 3 6 18 18 0 0 1 0 1 0 1 4 6 24 24 0 0 0 1 0 1 1 1 5 6 30 30 0 0 0 1 1 1 0 1 4 8 32 32 0 0 0 1 1 1 1 1 5 8 40 40 0 0 1 0 0 1 1 1 5 10 50 50 0 0 1 0 1 0 1 1 3 12 36 36 0 0 1 0 1 1 0 1 4 12 48 48 0 0 1 0 1 1 1 1 5 12 60 60 0 0 1 1 0 0 0 1 2 14 28 28 0 0 1 1 0 0 1 1 3 14 42 42 0 0 1 1 0 1 0 1 4 14 56 56 0 0 1 1 0 1 1 1 5 14 70 70 0 0 1 1 1 1 0 1 4 16 64 64 0 0 1 1 1 1 1 1 5 16 80 80 n.19 n.18 n.17 n.16 n.15 n.14 n.13 n.20 X X X X X X X 0 0 1 0 0 0 0 0 1 – 1 0 0 0 0 0 0 1 2 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Prescaler Setting OUTnDIVSEL – OutnDIVSEL0 4 3 OUTnDIVSEL1 OFF 2** OUTnDIVSEL2 1 – OUTnDIVSEL3 – OUTnDIVSEL4 OFF OUTnDIVSEL5 OFF OUTnDIVSEL6 Auxiliary Output Prescaler Output Channels 0–4 Integer Divider Integer Divider Setting OUTPUT DIVIDER n SETTINGS Register n (n = 0,1,2,3,4) Multiplexer **Output channel 2 or 3 determine the auxiliary output divide ratio. For example, if the auxiliary output is programmed to drive via output 2 and output 2 divider is programmed to divide by 3, then the divide ratio for the auxiliary output will be 6. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 35 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Digital Phase Adjust Figure 25 provides an overview of the Digital Phase Adjust feature. The output divider includes a coarse phase adjust that shifts the divided clock signal that drives the output buffer. Essentially, the Digital Phase Adjust timer delays when the output divider starts dividing; thereby shifting the phase of the output clock. The phase adjust resolution is a function of the divide function. Coarse phase adjust parameters include: • Number of Phase Delay Steps – the number of phase delay steps available is equal to the divide ratio selected. For example, if a Divide by 4 is selected, then the Digital Phase Adjust can be programmed to select when the output divider changes state based upon selecting one of the four counts on the input. Figure 25 shows an example of divide by 16 in which there are 16 rising edges of Clock IN at which the output divider changes state (this particular example shows the fourth edge shifting the output by one fourth of the period of the output). • Phase Delay Step Size – the step size is determined by the number of phase delay steps according to the following equations: 360 degrees Stepsize(deg) = OutputDivideRatio (1) 1 Stepsize (sec ) = f ClockIN OutputDivideRatio Clock IN (2) Digital Phase Adjust (7-bits) Start Divider /1 - /80 To Output Buffer Clock IN Output Divider (no adjust ) Output Divider (phase adjust ) Figure 25. CDCE18005 Phase Adjust Phase Adjust example Given: Output Frequency: 30.72 MHz Input Frequency: 491.52 MHz Output Divider Setting: 16 360 o Stepsize(deg) = = 22.5 /Step 16 (3) The tables that follow provide a list of valid register settings for the digital phase adjust blocks. 36 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 18 20 24 Phase Delay (radian) 0 0 (2π/2) 0 (2π/3) 2(2π/3) 0 (2π/4) 2(2π/4) 3(2π/4) 0 (2π/5) 2(2π/5) 3(2π/5) 4(2π/5) 0 (2π/6) 2(2π/6) 3(2π/6) 4(2π/6) 5(2π/6) 0 (2π/8) 2(2π/8) 3(2π/8) 4(2π/8) 5(2π/8) 6(2π/8) 7(2π/8) 0 (2π/10) 2(2π/10) 3(2π/10) 4(2π/10) 5(2π/10) 6(2π/10) 7(2π/10) 8(2π/10) 9(2π/10) 0 (2π/12) 2(2π/12) 3(2π/12) 4(2π/12) 5(2π/12) 6(2π/12) 7(2π/12) 8(2π/12) 9(2π/12) 10(2π/12) 11(2π/12) 0 (2π/16) 2(2π/16) 3(2π/16) 4(2π/16) 5(2π/16) 6(2π/16) 7(2π/16) 8(2π/16) 9(2π/16) 10(2π/16) 11(2π/16) 12(2π/16) 13(2π/16) 14(2π/16) 15(2π/16) PHnADGC0 n.6 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PHnADGC1 n.7 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PHnADGC2 n.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHnADGC3 n.9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PHnADGC4 n.10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Divide Ratio n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHnADGC5 16 n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHnADGC6 12 Phase Delay 10 PHnADGC0 8 PHnADGC1 6 PHnADGC2 5 PHnADGC3 4 PHnADGC4 3 PHnADGC5 1 2 PHnADGC6 Divide Ratio Table 21. CDCE18005 Output Coarse Phase Adjust Settings (1) n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n.11 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 n.10 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 n.9 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 n.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n.7 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 n.6 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (radian) 0 (2π/18) 2(2π/18) 3(2π/18) 4(2π/18) 5(2π/18) 6(2π/18) 7(2π/18) 8(2π/18) 9(2π/18) 10(2π/18) 11(2π/18) 12(2π/18) 13(2π/18) 14(2π/18) 15(2π/18) 16(2π/18) 17(2π/18) 0 (2π/20) 2(2π/20) 3(2π/20) 4(2π/20) 5(2π/20) 6(2π/20) 7(2π/20) 8(2π/20) 9(2π/20) 10(2π/20) 11(2π/20) 12(2π/20) 13(2π/20) 14(2π/20) 15(2π/20) 16(2π/20) 17(2π/20) 18(2π/20) 19(2π/20) 0 (2π/24) 2(2π/24) 3(2π/24) 4(2π/24) 5(2π/24) 6(2π/24) 7(2π/24) 8(2π/24) 9(2π/24) 10(2π/24) 11(2π/24) 12(2π/24) 13(2π/24) 14(2π/24) 15(2π/24) 16(2π/24) 17(2π/24) 18(2π/24) 19(2π/24) 20(2π/24) 21(2π/24) 22(2π/24) 23(2π/24) Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 37 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com 38 32 36 Phase Delay (radian) 0 (2π/28) 2(2π/28) 3(2π/28) 4(2π/28) 5(2π/28) 6(2π/28) 7(2π/28) 8(2π/28) 9(2π/28) 10(2π/28) 11(2π/28) 12(2π/28) 13(2π/28) 14(2π/28) 15(2π/28) 16(2π/28) 17(2π/28) 18(2π/28) 19(2π/28) 20(2π/28) 21(2π/28) 22(2π/28) 23(2π/28) 24(2π/28) 25(2π/28) 26(2π/28) 27(2π/28) 0 (2π/30) 2(2π/30) 3(2π/30) 4(2π/30) 5(2π/30) 6(2π/30) 7(2π/30) 8(2π/30) 9(2π/30) 10(2π/30) 11(2π/30) 12(2π/30) 13(2π/30) 14(2π/30) 15(2π/30) 16(2π/30) 17(2π/30) 18(2π/30) 19(2π/30) 20(2π/30) 21(2π/30) 22(2π/30) 23(2π/30) 24(2π/30) 25(2π/30) 26(2π/30) 27(2π/30) 28(2π/30) 29(2π/30) PHnADGC0 n.6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 PHnADGC1 n.7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 PHnADGC2 Phase Delay n.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 PHnADGC3 PHnADGC0 n.9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 PHnADGC4 PHnADGC1 n.10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 PHnADGC5 PHnADGC2 n.11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 PHnADGC6 PHnADGC3 n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Divide Ratio PHnADGC4 30 PHnADGC5 28 PHnADGC6 Divide Ratio Table 22. CDCE18005 Output Coarse Phase Adjust Settings (2) n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 n.10 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 n.9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 n.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n.7 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 n.6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 (radian) 0 (2π/32) 2(2π/32) 3(2π/32) 4(2π/32) 5(2π/32) 6(2π/32) 7(2π/32) 8(2π/32) 9(2π/32) 10(2π/32) 11(2π/32) 12(2π/32) 13(2π/32) 14(2π/32) 15(2π/32) 16(2π/32) 17(2π/32) 18(2π/32) 19(2π/32) 20(2π/32) 21(2π/32) 22(2π/32) 23(2π/32) 24(2π/32) 25(2π/32) 26(2π/32) 27(2π/32) 28(2π/32) 29(2π/32) 30(2π/32) 31(2π/32) 0 (2π/36) 2(2π/36) 3(2π/36) 4(2π/36) 5(2π/36) 6(2π/36) 7(2π/36) 8(2π/36) 9(2π/36) 10(2π/36) 11(2π/36) 12(2π/36) 13(2π/36) 14(2π/36) 15(2π/36) 16(2π/36) 17(2π/36) 18(2π/36) 19(2π/36) 20(2π/36) 21(2π/36) 22(2π/36) 23(2π/36) 24(2π/36) 25(2π/36) 26(2π/36) 27(2π/36) 28(2π/36) 29(2π/36) 30(2π/36) 31(2π/36) 32(2π/36) 33(2π/36) 34(2π/36) 35(2π/36) Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 39 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com 40 48 Phase Delay (radian) 0 (2π/40) 2(2π/40) 3(2π/40) 4(2π/40) 5(2π/40) 6(2π/40) 7(2π/40) 8(2π/40) 9(2π/40) 10(2π/40) 11(2π/40) 12(2π/40) 13(2π/40) 14(2π/40) 15(2π/40) 16(2π/40) 17(2π/40) 18(2π/40) 19(2π/40) 20(2π/40) 21(2π/40) 22(2π/40) 23(2π/40) 24(2π/40) 25(2π/40) 26(2π/40) 27(2π/40) 28(2π/40) 29(2π/40) 30(2π/40) 31(2π/40) 32(2π/40) 33(2π/40) 34(2π/40) 35(2π/40) 36(2π/40) 37(2π/40) 38(2π/40) 39(2π/40) 0 (2π/42) 2(2π/42) 3(2π/42) 4(2π/42) 5(2π/42) 6(2π/42) 7(2π/42) 8(2π/42) 9(2π/42) 10(2π/42) 11(2π/42) 12(2π/42) 13(2π/42) 14(2π/42) 15(2π/42) 16(2π/42) 17(2π/42) 18(2π/42) 19(2π/42) 20(2π/42) 21(2π/42) 22(2π/42) 23(2π/42) 24(2π/42) 25(2π/42) 26(2π/42) 27(2π/42) 28(2π/42) 29(2π/42) 30(2π/42) 31(2π/42) 32(2π/42) 33(2π/42) 34(2π/42) 35(2π/42) 36(2π/42) 37(2π/42) 38(2π/42) 39(2π/42) 40(2π/42) 41(2π/42) PHnADGC0 n.6 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 PHnADGC1 n.7 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 PHnADGC2 Phase Delay n.8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHnADGC3 PHnADGC0 n.9 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 PHnADGC4 PHnADGC1 n.10 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 PHnADGC5 PHnADGC2 n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 PHnADGC6 PHnADGC3 n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Divide Ratio PHnADGC4 42 PHnADGC5 40 PHnADGC6 Divide Ratio Table 23. CDCE18005 Output Coarse Phase Adjust Settings (3) n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 n.10 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 n.9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 n.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n.7 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 n.6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (radian) 0 (2π/48) 2(2π/48) 3(2π/48) 4(2π/48) 5(2π/48) 6(2π/48) 7(2π/48) 8(2π/48) 9(2π/48) 10(2π/48) 11(2π/48) 12(2π/48) 13(2π/48) 14(2π/48) 15(2π/48) 16(2π/48) 17(2π/48) 18(2π/48) 19(2π/48) 20(2π/48) 21(2π/48) 22(2π/48) 23(2π/48) 24(2π/48) 25(2π/48) 26(2π/48) 27(2π/48) 28(2π/48) 29(2π/48) 30(2π/48) 31(2π/48) 32(2π/48) 33(2π/48) 34(2π/48) 35(2π/48) 36(2π/48) 37(2π/48) 38(2π/48) 39(2π/48) 40(2π/48) 41(2π/48) 42(2π/48) 43(2π/48) 44(2π/48) 45(2π/48) 46(2π/48) 47(2π/48) Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 56 Phase Delay (radian) 0 (2π/50) 2(2π/50) 3(2π/50) 4(2π/50) 5(2π/50) 6(2π/50) 7(2π/50) 8(2π/50) 9(2π/50) 10(2π/50) 11(2π/50) 12(2π/50) 13(2π/50) 14(2π/50) 15(2π/50) 16(2π/50) 17(2π/50) 18(2π/50) 19(2π/50) 20(2π/50) 21(2π/50) 22(2π/50) 23(2π/50) 24(2π/50) 25(2π/50) 26(2π/50) 27(2π/50) 28(2π/50) 29(2π/50) 30(2π/50) 31(2π/50) 32(2π/50) 33(2π/50) 34(2π/50) 35(2π/50) 36(2π/50) 37(2π/50) 38(2π/50) 39(2π/50) 40(2π/50) 41(2π/50) 42(2π/50) 43(2π/50) 44(2π/50) 45(2π/50) 46(2π/50) 47(2π/50) 48(2π/50) 49(2π/50) PHnADGC0 n.6 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 PHnADGC1 Phase Delay n.7 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 PHnADGC2 PHnADGC0 n.8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 PHnADGC3 PHnADGC1 n.9 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 PHnADGC4 PHnADGC2 n.10 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 PHnADGC5 PHnADGC3 n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 PHnADGC6 PHnADGC4 n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Divide Ratio PHnADGC5 50 PHnADGC6 Divide Ratio Table 24. CDCE18005 Output Coarse Phase Adjust Settings (4) n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 n.10 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 n.9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 n.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n.7 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 n.6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (radian) 0 (2π/56) 2(2π/56) 3(2π/56) 4(2π/56) 5(2π/56) 6(2π/56) 7(2π/56) 8(2π/56) 9(2π/56) 10(2π/56) 11(2π/56) 12(2π/56) 13(2π/56) 14(2π/56) 15(2π/56) 16(2π/56) 17(2π/56) 18(2π/56) 19(2π/56) 20(2π/56) 21(2π/56) 22(2π/56) 23(2π/56) 24(2π/56) 25(2π/56) 26(2π/56) 27(2π/56) 28(2π/56) 29(2π/56) 30(2π/56) 31(2π/56) 32(2π/56) 33(2π/56) 34(2π/56) 35(2π/56) 36(2π/56) 37(2π/56) 38(2π/56) 39(2π/56) 40(2π/56) 41(2π/56) 42(2π/56) 43(2π/56) 44(2π/56) 45(2π/56) 46(2π/56) 47(2π/56) 48(2π/56) 49(2π/56) 50(2π/56) 51(2π/56) 52(2π/56) 53(2π/56) 54(2π/56) 55(2π/56) Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 41 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com 42 64 Phase Delay (radian) 0 (2π/60) 2(2π/60) 3(2π/60) 4(2π/60) 5(2π/60) 6(2π/60) 7(2π/60) 8(2π/60) 9(2π/60) 10(2π/60) 11(2π/60) 12(2π/60) 13(2π/60) 14(2π/60) 15(2π/60) 16(2π/60) 17(2π/60) 18(2π/60) 19(2π/60) 20(2π/60) 21(2π/60) 22(2π/60) 23(2π/60) 24(2π/60) 25(2π/60) 26(2π/60) 27(2π/60) 28(2π/60) 29(2π/60) 30(2π/60) 31(2π/60) 32(2π/60) 33(2π/60) 34(2π/60) 35(2π/60) 36(2π/60) 37(2π/60) 38(2π/60) 39(2π/60) 40(2π/60) 41(2π/60) 42(2π/60) 43(2π/60) 44(2π/60) 45(2π/60) 46(2π/60) 47(2π/60) 48(2π/60) 49(2π/60) 50(2π/60) 51(2π/60) 52(2π/60) 53(2π/60) 54(2π/60) 55(2π/60) 56(2π/60) 57(2π/60) 58(2π/60) 59(2π/60) PHnADGC0 n.6 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 PHnADGC1 Phase Delay n.7 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 PHnADGC2 PHnADGC0 n.8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 PHnADGC3 PHnADGC1 n.9 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 PHnADGC4 PHnADGC2 n.10 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 PHnADGC5 PHnADGC3 n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 PHnADGC6 PHnADGC4 n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Divide Ratio PHnADGC5 60 PHnADGC6 Divide Ratio Table 25. CDCE18005 Output Coarse Phase Adjust Settings (5) n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n.10 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 n.9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 n.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n.7 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 n.6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (radian) 0 (2π/64) 2(2π/64) 3(2π/64) 4(2π/64) 5(2π/64) 6(2π/64) 7(2π/64) 8(2π/64) 9(2π/64) 10(2π/64) 11(2π/64) 12(2π/64) 13(2π/64) 14(2π/64) 15(2π/64) 16(2π/64) 17(2π/64) 18(2π/64) 19(2π/64) 20(2π/64) 21(2π/64) 22(2π/64) 23(2π/64) 24(2π/64) 25(2π/64) 26(2π/64) 27(2π/64) 28(2π/64) 29(2π/64) 30(2π/64) 31(2π/64) 32(2π/64) 33(2π/64) 34(2π/64) 35(2π/64) 36(2π/64) 37(2π/64) 38(2π/64) 39(2π/64) 40(2π/64) 41(2π/64) 42(2π/64) 43(2π/64) 44(2π/64) 45(2π/64) 46(2π/64) 47(2π/64) 48(2π/64) 49(2π/64) 50(2π/64) 51(2π/64) 52(2π/64) 53(2π/64) 54(2π/64) 55(2π/64) 56(2π/64) 57(2π/64) 58(2π/64) 59(2π/64) 60(2π/64) 61(2π/64) 62(2π/64) 63(2π/64) Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 80 Phase Delay (radian) 0 (2π/70) 2(2π/70) 3(2π/70) 4(2π/70) 5(2π/70) 6(2π/70) 7(2π/70) 8(2π/70) 9(2π/70) 10(2π/70) 11(2π/70) 12(2π/70) 13(2π/70) 14(2π/70) 15(2π/70) 16(2π/70) 17(2π/70) 18(2π/70) 19(2π/70) 20(2π/70) 21(2π/70) 22(2π/70) 23(2π/70) 24(2π/70) 25(2π/70) 26(2π/70) 27(2π/70) 28(2π/70) 29(2π/70) 30(2π/70) 31(2π/70) 32(2π/70) 33(2π/70) 34(2π/70) 35(2π/70) 36(2π/70) 37(2π/70) 38(2π/70) 39(2π/70) 40(2π/70) 41(2π/70) 42(2π/70) 43(2π/70) 44(2π/70) 45(2π/70) 46(2π/70) 47(2π/70) 48(2π/70) 49(2π/70) 50(2π/70) 51(2π/70) 52(2π/70) 53(2π/70) 54(2π/70) 55(2π/70) 56(2π/70) 57(2π/70) 58(2π/70) 59(2π/70) 60(2π/70) 61(2π/70) 62(2π/70) 63(2π/70) 64(2π/70) 65(2π/70) 66(2π/70) 67(2π/70) 68(2π/70) 69(2π/70) PHnADGC0 n.6 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 PHnADGC1 Phase Delay n.7 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 PHnADGC2 PHnADGC0 n.8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 PHnADGC3 PHnADGC1 n.9 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 PHnADGC4 PHnADGC2 n.10 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 PHnADGC5 PHnADGC3 n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PHnADGC6 PHnADGC4 n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Divide Ratio PHnADGC5 70 PHnADGC6 Divide Ratio Table 26. CDCE18005 Output Coarse Phase Adjust Settings (6) n.12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n.10 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 n.9 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 n.8 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 n.7 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 n.6 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 (radian) 0 (2π/80) 2(2π/80) 3(2π/80) 4(2π/80) 5(2π/80) 6(2π/80) 7(2π/80) 8(2π/80) 9(2π/80) 10(2π/80) 11(2π/80) 12(2π/80) 13(2π/80) 14(2π/80) 15(2π/80) 16(2π/80) 17(2π/80) 18(2π/80) 19(2π/80) 20(2π/80) 21(2π/80) 22(2π/80) 23(2π/80) 24(2π/80) 25(2π/80) 26(2π/80) 27(2π/80) 28(2π/80) 29(2π/80) 30(2π/80) 31(2π/80) 32(2π/80) 33(2π/80) 34(2π/80) 35(2π/80) 36(2π/80) 37(2π/80) 38(2π/80) 39(2π/80) 40(2π/80) 41(2π/80) 42(2π/80) 43(2π/80) 44(2π/80) 45(2π/80) 46(2π/80) 47(2π/80) 48(2π/80) 49(2π/80) 50(2π/80) 51(2π/80) 52(2π/80) 53(2π/80) 54(2π/80) 55(2π/80) 56(2π/80) 57(2π/80) 58(2π/80) 59(2π/80) 60(2π/80) 61(2π/80) 62(2π/80) 63(2π/80) 64(2π/80) 65(2π/80) 66(2π/80) 67(2π/80) 68(2π/80) 69(2π/80) 70(2π/80) 71(2π/80) 72(2π/80) 73(2π/80) 74(2π/80) 75(2π/80) 76(2π/80) 77(2π/80) 78(2π/80) 79(2π/80) Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 43 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Crystal Input Interface Fundamental mode is the recommended oscillation mode of operation for the input crystal and parallel resonance is the recommended type of circuit for the crystal. A crystal load capacitance refers to all capacitances in the oscillator feedback loop. It is equal to the amount of capacitance seen between the terminals of the crystal in the circuit. For parallel resonant mode circuits, the correct load capacitance is necessary to ensure the oscillation of the crystal within the expected parameters. The CDCE18005 implements an input crystal oscillator circuitry, known as the Colpitts oscillator, and requires one pad of the crystal to interface with the AUX_IN pin; the other pad of the crystal is tied to ground. In this crystal interface, it is important to account for all sources of capacitance when calculating the correct value for the discrete capacitor component, CL, for a design. The CDCE18005 has been characterized with 10-pF parallel resonant crystals. The input crystal oscillator stage in the CDCE18005 is designed to oscillate at the correct frequency for all parallel resonant crystals with low-pull capability and rated with a load capacitance that is equal to the sum of the on-chip load capacitance at the AUX_IN pin (10-pF), crystal stray capacitance, and board parasitic capacitance between the crystal and AUX_IN pin. The normalized frequency error of the crystal, as a result of load capacitance mismatch, can be calculated as Equation 4: Δf CS CS = f 2 (CL,R + C O ) 2 (C L,A + C O ) (4) Where: CS is the motional capacitance of the crystal CO is the shunt capacitance of the crystal CL,R is the rated load capacitance for the crystal CL,A is the actual load capacitance in the implemented PCB for the crystal Δf is the frequency error of the crystal f is the rated frequency of the crystal The first three parameters can be obtained from the crystal vendor. In order to minimize the frequency error of the crystal to meet application requirements, the difference between the rated load capacitance and the actual load capacitance should be minimized and a crystal with low-pull capability (low CS) should be used. For example, if an application requires less than ±50 ppm frequency error and a crystal with less than ±50 ppm frequency tolerance is picked, the characteristics are as follows: CO = 7 pF, CS = 10 Δf, and CL,R = 12 pF. In order to meet the required frequency error, calculate CL,A using Equation 2 to be 17 pF. Subtracting CL,R from CL,A, results in 5 pF; care must be taken during printed circuit board (PCB) layout with the crystal and the CDCE18005 to ensure that the sum of the crystal stray capacitance and board parasitic capacitance is less than the calculated 5 pF. Good layout practices are fundamental to the correct operation and reliability of the oscillator. It is critical to locate the crystal components very close to the XIN pin to minimize routing distances. Long traces in the oscillator circuit are a common source of problems. Do not route other signals across the oscillator circuit. Also, make sure power and high-frequency traces are routed as far away as possible to avoid crosstalk and noise coupling. Avoid the use of vias; if the routing becomes very complex, it is better to use 0-Ω resistors as bridges to go over other signals. Vias in the oscillator circuit should only be used for connections to the ground plane. Do not share ground connections; instead, make a separate connection to ground for each component that requires grounding. If possible, place multiple vias in parallel for each connection to the ground plane. Especially in the Colpitts oscillator configuration, the oscillator is very sensitive to capacitance in parallel with the crystal. Therefore, the layout must be designed to minimize stray capacitance across the crystal to less than 5 pF total under all circumstances to ensure proper crystal oscillation. Be sure to take into account both PCB and crystal stray capacitance. Auxiliary Output Figure 26 shows the auxiliary output port. Table 27 lists how the auxiliary output port is controlled. The output buffer supports a maximum output frequency of 250 MHz and drives at LVCMOS levels. See Table 20 for the list of divider settings that establishes the output frequency. 44 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Output Divider 2 AUX_OUT Output Divider 3 Register 6 25 Register 6 24 Figure 26. CDCE18005 Auxiliary Output Table 27. CDCE18005 Auxiliary Output Settings Bit Name → AUXFEEDSEL AUXOUTEN Register.Bit → 6.25 6.24 X 0 OFF 0 1 Divider 2 1 1 Divider 3 AUX_OUT SOURCE DEVICE POWER CALCULATION AND THERMAL MANAGEMENT The CDCE18005 is a high performance device, therefore careful attention must be paid to device configuration and printed circuit board layout with respect to power consumption. Table 28 provides the power consumption for the individual blocks within the CDCE18005. To estimate total power consumption, calculate the sum of the products of the number of blocks used and the power dissipated of each corresponding block. Provide Sample Calculation Here after numbers become available. Table 28. CDCE18005 Power Consumption Internal Block Power at 3.3V (typ) Power Dissipated per Block Number of Blocks 450 mW 1 Divider = 1 60 mW 5 Divider > 1 140 mW 5 75 mW (1) 5 Input and Control Circuit Output Dividers LVPECL Output Buffer LVDS Output Buffer Static LVCMOS Output Buffer (1) Transient, 'CL' load, 'fOUT' MHz output frequency, 'V' output swing 76 mW 5 7 mW 10 3.3 × V × fOUT × (CL + 20 × 10-12) × 103 10 Approximately 50 mW power dissipates externally at termination resistors per LVPECL output pair. This power estimate determines the degree of thermal management required for a specific design. Employing the thermally enhanced printed circuit board layout shown in Figure 28 insures that the thermal performance curves shown in Figure 27 apply. Observing good thermal layout practices enables the thermal pad on the backside of the QFN-48 package to provide a good thermal path between the die contained within the package and the ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance connection to the ground plane is essential. Figure 28 shows a layout optimized for good thermal performance and a good power supply connection as well. The 7×7 filled via patter facilitates both considerations. Finally, the recommended layout achieves θJA = 27.3°C/W in still air and 20.3°C/W in an environment with 100 LFM airflow if implemented on a JEDEC compliant thermal test board. Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 45 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com Die Temperature vs Total Device Power RL 0 LFM 85 C 125 JEDEC 0 LFM 25 C JEDEC 100 LFM 25 C RL 0 LFM 25 C JDEC 0 LFM 85 C JEDEC 0 LFM 25 C 100 JEDEC 100 LFM 25 C Die Temp (C) RL 100 LFM 85 C RL 0 LFM 25 C 75 JEDEC 100 LFM 85 C RL 100 LFM 25 C RL 100 LFM 25 C JEDEC 0 LFM 85 C 50 JEDEC 100 LFM 85 C RL 0 LFM 85 C 25 RL 100 LFM 85 C 0 0 1 2 3 4 Power (W) Figure 27. CDCE18005 Die Temperature vs Device Power 46 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 Component Side QFN-48 Thermal Slug (package bottom) Solder Mask Internal Ground Plane Internal Power Plane Thermal Dissipation Pad (back side) Thermal Vias No Solder Mask Back Side Figure 28. CDCE18005 Recommended PCB Layout Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 47 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 www.ti.com CDCE18005 Power Supply Bypassing – Recommended Layout Figure 29 shows two conceptual layouts detailing recommended placement of power supply bypass capacitors. If the capacitors are mounted on the back side, 0402 components can be employed; however, soldering to the Thermal Dissipation Pad can be difficult. For component side mounting, use 0201 body size capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Component Side Back Side Figure 29. CDCE18005 Power Supply Bypassing 48 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 APPLICATION INFORMATION AND GENERAL USAGE HINTS Fan-out Buffer Each output of the CDCE18005 can be configured as a fan-out buffer (divider bypassed) or fan-out buffer with divide and skew control functionality. Divide by 1: Up to 1500 MHz Otherwise : Up to 1175 MHz PRI_REF U0P /1 - /80 U0N SEC_REF Up to 5 Outputs : LVPECL or LVDS Up to 10 Outputs: LVCMOS U4P /1 - /80 U4N Figure 30. CDCE18005 Fan-out Buffer Mode Clock Buffer with Crystal Input The CDCE18005 can distribute 5–10 low noise clocks from a single crystal as follows: XTAL / AUX_IN U0P Output Divider 0 U0N U4P Output Divider 4 U4N Figure 31. CDCE18005 Clock Generator Mode Clock Distribution – Mixed Mode The following table presents a common scenario where the CDCE18005 can function as a clock switch that accepts LVDS and crystal inputs and drives LVDS, LVPECL and LVCMOS outputs. CLOCK FREQUENCY INPUT/OUTPUT FORMAT NUMBER CDCE18005 PORT 491.52 MHz Input LVDS 1 SEC_IN Reference 125 MHz Input LVDS 1 PRI_IN Reference from backplane Low end crystal oscillator 10 MHz COMMENT Input AT-Cut 1 AUX_IN 122.88 MHz Output LVDS 1 U0 SerDes Clock 491.52 MHz Output LVPECL 1 U1 ASIC 125 MHz Output LVPECL 1 U2 FPGA 30.72 MHz Outputs LVCMOS 2 U3 ASIC 10 MHz Outputs LVCMOS 2 U4 CPU, DSP Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 49 CDCE18005 SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 491.52 MHz www.ti.com Output Divider 0 122.88 MHz Output Divider 1 491.52 MHz Output Divider 2 125.00 MHz 125.00 MHz Xtal 10MHz 30.72 MHz Output Divider 3 Output Divider 4 30.72 MHz 10 MHz 10 MHz Figure 32. CDCE18005 Mixed Mode Clock Distribution Example 50 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 CDCE18005 www.ti.com SCAS863B – NOVEMBER 2008 – REVISED NOVEMBER 2012 REVISION HISTORY Changes from Original (November 2008) to Revision A Page • Changed Title From: Five/Ten Output Clock Generator/Buffer To: Five/Ten Output Clock Programmable/Buffer .............. 1 • Changed Flexible Inputs in the Features list ........................................................................................................................ 1 • Deleted Integrated EEPROM item from Features list ........................................................................................................... 1 • Added the Pin Out drawing and updated the Pin Functions table ........................................................................................ 2 • Added note (1) to the Pin Functions table ............................................................................................................................ 3 • Added under bar in Pin Names (43, 13, 45, 46, 3 and 2) and deleted space ...................................................................... 3 • Changed PRI_IN To PRI_REF and SEC_IN to SEC_REF in images and text throughout the data sheet ......................... 4 • Changed the ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS table ........................................................ 9 • Changed the TIMING REQUIREMENTS table ................................................................................................................... 14 • Changed From: Jitter RMS 10k≈5MHz To: Jitter RMS 10k–20MH in Table 1 ................................................................... 14 • Deleted the Reference 25.00 MHz column from Table 2 and changed Jitter RMS From: 10k≈20 Mhz To: 10k–5MHz. ... 14 • Deleted the SPI Control Interface Timing section ............................................................................................................... 14 • Deleted Figure CDCE18005 Interface and Control block illustration .................................................................................. 15 • Deleted Figure CDCE18005 SPI Communications Format ................................................................................................ 15 • Added new section SPI Interface Master ........................................................................................................................... 16 • Deleted the last row of the Register Default Setting table - (REG0008 (RAM) .................................................................. 19 • Deleted the first four rows of Table 5 through Table 13 - Bit Names A0, A1, A2, and A3. Added a note to Table 5 through Table 9 ................................................................................................................................................................... 20 • Changed Table 12 RAM BIT 26 From: Read only; always reads "1" ................................................................................. 27 • Changed Table 12 RAM BIT 27 From: EEPROM Status ................................................................................................... 27 • Added note to Table 13 ...................................................................................................................................................... 28 • Changed Table 14 - Output Buffer coulmn From: Disbled or Enabled To: Hi-Z or From: Enable or Disabled To: Hi-Z .... 29 • Added Table 20 - CDCE18005 Output Divider Settings ..................................................................................................... 35 • Changed Figure 25 Clock IN label From: Cloclk IN (from SMART_MUX) ......................................................................... 36 • Changed Equation 3 ........................................................................................................................................................... 36 • Added new section - Cystal Input Interface ........................................................................................................................ 44 • Changed Table 28 .............................................................................................................................................................. 45 Changes from Revision A (June 2011) to Revision B • Page Changed pin 2 From: SEC_REF+ To SEC_REF- and pin 3 From SEC_REF- To: SEC_REF+ .......................................... 2 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links :CDCE18005 51 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CDCE18005RGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAUAG Level-3-260C-168 HR -40 to 85 CDCE 18005 CDCE18005RGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAUAG Level-3-260C-168 HR -40 to 85 CDCE 18005 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of