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CDCE913, CDCEL913
SCAS849G – JUNE 2007 – REVISED OCTOBER 2016
CDCE(L)913: Flexible Low Power LVCMOS Clock Generator
With SSC Support for EMI Reduction
1 Features
3 Description
•
The CDCE913 and CDCEL913 devices are modular
PLL-based,
low-cost,
high-performance,
programmable clock synthesizers. They generate up
to three output clocks from a single input frequency.
Each output can be programmed in-system for any
clock frequency up to 230 MHz, using the integrated
configurable PLL.
1
•
•
•
•
•
•
•
•
•
•
Member of Programmable Clock Generator
Family
– CDCE913/CDCEL913: 1-PLL, 3 Outputs
– CDCE925/CDCEL925: 2-PLL, 5 Outputs
– CDCE937/CDCEL937: 3-PLL, 7 Outputs
– CDCE949/CDCEL949: 4-PLL, 9 Outputs
In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Settings
Flexible Input Clocking Concept
– External Crystal: 8 MHz to 32 MHz
– On-Chip VCXO: Pull Range ±150 ppm
– Single-Ended LVCMOS Up to 160 MHz
Free Selectable Output Frequency Up to
230 MHz
Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typical 50 ps)
Separate Output Supply Pins
– CDCE913: 3.3 V and 2.5 V
– CDCEL913: 1.8 V
Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2], for Example, SSC Selection,
Frequency Switching, Output Enable, or Power
Down
– Generates Highly Accurate Clocks for Video,
Audio, USB, IEEE1394, RFID, Bluetooth®,
WLAN, Ethernet™, and GPS
– Generates Common Clock Frequencies Used
With TI-DaVinci™, OMAP™, DSPs
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
1.8-V Device Power Supply
Wide Temperature Range: –40°C to 85°C
Packaged in TSSOP
Development and Programming Kit for Easy PLL
Design and Programming (TI Pro-Clock™)
The CDCx913 has separate output supply pins,
VDDOUT, which is 1.8 V for CDCEL913 and 2.5 V to
3.3 V for CDCE913.
The input accepts an external crystal or LVCMOS
clock signal. A selectable on-chip VCXO allows
synchronization of the output frequency to an external
control signal.
The PLL supports SSC (spread-spectrum clocking)
for better electromagnetic interference (EMI)
performance.
The
device
supports
nonvolatile
EEPROM
programming for easy customization of the device to
the application. All device settings are programmable
through the SDA/SCL bus, a 2-wire serial interface.
The CDCx913 operates in a 1.8-V environment. It
operates in a temperature range of –40°C to 85°C.
Device Information(1)
PART NUMBER
CDCE913
CDCEL913
PACKAGE
TSSOP (14)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Ethernet
PHY
USB
Controller
CDCE(L)9xx
Clock
25
MHz
WiFi
FPGA
2 Applications
D-TVs, STBs, IP-STBs, DVD Players, DVD
Recorders, and Printers
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCE913, CDCEL913
SCAS849G – JUNE 2007 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
3
4
4
5
5
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
EEPROM Specification .............................................
Timing Requirements: CLK_IN ................................
Timing Requirements: SDA/SCL ..............................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
11
13
14
15
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (April 2015) to Revision G
•
Page
Changed data sheet title from: CDCEx913 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and
3.3-V Outputs to: CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction ..... 1
Changes from Revision E (March 2010) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added in Figure 9, second S to Sr ....................................................................................................................................... 14
•
Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4 ................... 23
•
Changed under Example, fifth row, N", 2 places TO N' ....................................................................................................... 23
Changes from Revision D (October 2009) to Revision E
Page
•
Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0 20 pF, use additional external capacitors. The device input capacitance value must be considered, which always adds 1.5
pF (6 pF//2 pF) to the selected CL. For more about VCXO config. and crystal recommendation, see application report SCAA085.
The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The
EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The
EEWRITE bit must be reset to low after the programming is completed. The programming status can be monitored by reading out
EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
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Product Folder Links: CDCE913 CDCEL913
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CDCE913, CDCEL913
SCAS849G – JUNE 2007 – REVISED OCTOBER 2016
www.ti.com
Table 12. PLL1 Configuration Register
OFFSET
10h
11h
12h
13h
14h
15h
(1)
(2)
(3)
(4)
18
(1)
ACRONYM
DEFAULT (3)
7:5
SSC1_7 [2:0]
000b
4:2
SSC1_6 [2:0]
000b
1:0
SSC1_5 [2:1]
7
SSC1_5 [0]
6:4
SSC1_4 [2:0]
000b
3:1
SSC1_3 [2:0]
000b
0
SSC1_2 [2]
7:6
SSC1_2 [1:0]
5:3
SSC1_1 [2:0]
000b
2:0
SSC1_0 [2:0]
000b
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
7
MUX1
1b
PLL1 multiplexer:
0 – PLL1
1 – PLL1 bypass (PLL1 is in power down)
6
M2
1b
Output Y2 multiplexer:
0 – Pdiv1
1 – Pdiv2
5:4
M3
10b
Output Y3 Multiplexer:
00 –
01 –
10 –
11 –
3:2
Y2Y3_ST1
11b
00 – Y2/Y3 disabled to 3-state (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State
10–Y2/Y3 disabled to low
11 – Y2/Y3 enabled
BIT
(2)
000b
000b
DESCRIPTION
SSC1: PLL1 SSC selection (modulation amount).
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
(4)
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS1_x: PLL1 frequency selection (4)
0 – fVCO1_0 (predefined by PLL1_0 – multiplier/divider value)
1 – fVCO1_1 (predefined by PLL1_1 – multiplier/divider value)
1:0
Y2Y3_ST0
01b
Y2, Y3State0/1definition:
7
Y2Y3_7
0b
Y2Y3_x output state selection.
6
Y2Y3_6
0b
5
Y2Y3_5
0b
4
Y2Y3_4
0b
3
Y2Y3_3
0b
2
Y2Y3_2
0b
1
Y2Y3_1
1b
0
Y2Y3_0
0b
Pdiv1-divider
Pdiv2-divider
Pdiv3-divider
Reserved
(4)
0 – State0 (predefined by Y2Y3_ST0)
1 – State1 (predefined by Y2Y3_ST1)
Writing data beyond 20h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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SCAS849G – JUNE 2007 – REVISED OCTOBER 2016
Table 12. PLL1 Configuration Register (continued)
OFFSET
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
DESCRIPTION
7
SSC1DC
0b
PLL1 SSC down/center selection:
0 – Down
1 – Center
6:0
Pdiv2
01h
7-bit Y2-output-divider Pdiv2:
0 – Reset and stand-by
1 to 127 – Divider value
7
—
0b
Reserved – do not write others than 0
6:0
Pdiv3
01h
7-bit Y3-output-divider Pdiv3:
7:0
PLL1_0N [11:4]
7:4
PLL1_0N [3:0]
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
010b
1:0
VCO1_0_RANGE
00b
7:0
PLL1_1N [11:4]
7:4
PLL1_1N [3:0]
3:0
PLL1_1R [8:5]
7:3
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
010b
1:0
VCO1_1_RANGE
00b
16h
17h
18h
19h
1Ah
004h
000h
PLL1_0 (5): 30-bit multiplier/divider value for frequency fVCO1_0
(for more information, see the PLL Multiplier/Divider Definition paragraph).
10h
1Bh
1Ch
1Dh
1Eh
1Fh
(5)
0 – Reset and stand-by
1 to 127 – Divider value
fVCO1_0 range selection:
00 –
01 –
10 –
11 –
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
004h
000h
PLL1_1 (5): 30-bit multiplier/divider value for frequency fVCO1_1
(for more information see the PLL Multiplier/Divider Definition).
10h
fVCO1_1 range selection:
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: CDCE913 CDCEL913
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CDCE913, CDCEL913
SCAS849G – JUNE 2007 – REVISED OCTOBER 2016
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCE913 device is an easy-to-use high-performance, programmable CMOS clock synthesizer. it can be
used as a crystal buffer, clock synthesizer with separate output supply pin. The CDCE913 features an on-chip
loop filter and Spread-spectrum modulation. Programming can be done through SPI, pin-mode, or using on-chip
EEPROM. This section shows some examples of using CDCE913 in various applications.
9.2 Typical Application
Figure 14 shows the use of the CDCEL913 in an audio/video application using a 1.8-V single supply.
Figure 14. Single-Chip Solution Using CDCE913 for Generating Audio/Video Frequencies
9.2.1 Design Requirements
CDCE913 supports spread spectrum clocking (SSC) with multiple control parameters:
• Modulation amount (%)
• Modulation frequency (>20 kHz)
• Modulation shape (triangular, hershey, and others)
• Center spread / down spread (± or –)
20
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SCAS849G – JUNE 2007 – REVISED OCTOBER 2016
Typical Application (continued)
Figure 15. Modulation Frequency (fm) and Modulation Amount
Figure 16. Spread Spectrum Modulation Shapes
9.2.2 Detailed Design Procedure
9.2.2.1 Spread Spectrum Clock (SSC)
Spread Spectrum modulation is a method to spread emitted energy over a larger bandwidth. In clocking, spread
spectrum can reduce Electromagnetic Interference (EMI) by reducing the level of emission from clock distribution
network.
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Typical Application (continued)
CDCS502 with a 25-MHz Crystal, FS = 1, Fout = 100 MHz, and 0%, ±0.5, ±1%, and ±2% SSC
Figure 17. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock
9.2.2.2 PLL Frequency Planning
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCE913/CDCEL913 can be calculated:
ƒ
N
ƒOUT = IN ´
Pdiv M
where
•
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output divider.
(1)
The target VCO frequency (ƒVCO) of each PLL can be calculated:
N
ƒ VCO = ƒIN ´
M
(2)
The PLL internally operates as fractional divider and needs the following multiplier/divider settings:
• N
• P = 4 – int(log2N/M; if P < 0 then P = 0
• Q = int(N'/M)
• R = N′ – M × Q
where
N′ = N × 2P
N ≥ M;
22
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Typical Application (continued)
80 MHz ≤ ƒVCO ≤ 230 MHz
16 ≤ Q ≤ 63
0≤P≤4
0 ≤ R ≤ 51
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2
→ fOUT = 54 MHz
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ P = 4 – int(log25.5) = 4 – 2 = 2
2
→ N' = 4 × 2 = 16
→ N' = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.
9.2.2.3 Crystal Oscillator Start-up
When the CDCE913/CDCEL913 is used as a crystal buffer, crystal oscillator start-up dominates the start-up time
compared to the internal PLL lock time. The following diagram shows the oscillator start-up sequence for a 27MHz crystal input with an 8-pF load. The start-up time for the crystal is in the order of approximately 250 µs
compared to approximately 10 µs of lock time. In general, lock time will be an order of magnitude less compared
to the crystal start-up time.
Figure 18. Crystal Oscillator Start-Up vs PLL Lock Time
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Typical Application (continued)
9.2.2.4 Frequency Adjustment with Crystal Oscillator Pulling
The frequency for the CDCE913/CDCEL913 is adjusted for media and other applications with the VCXO control
input VCtrl. If a PWM modulated signal is used as a control signal for the VCXO, an external filter is needed.
LP
PWM
control
signal
Vctrl
CDCE(L)913
Xin/CLK
Xout
Figure 19. Frequency Adjustment Using PWM Input to the VCXO Control
9.2.2.5 Unused Inputs/Outputs
If VCXO pulling functionality is not required, VCtrl should be left floating. All other unused inputs should be set to
GND. Unused outputs should be left floating.
If one output block is not used, TI recommends disabling it. However, TI always recommends providing the
supply for the second output block even if it is disabled.
9.2.2.6 Switching Between XO and VCXO Mode
When the CDCE(L)913 is in crystal oscillator or in VCXO configuration, the internal capacitors require different
internal capacitance. The following steps are recommended to switch to VCXO mode when the configuration for
the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:
1. While in XO mode, put Vctrl = Vdd/2
2. Switch from X0 mode to VCXO mode
3. Program the internal capacitors in order to obtain 0 ppm at the output.
9.2.3 Application Curves
Figure 20, Figure 21, Figure 22, and Figure 23 show CDCE913 measurements with the SSC feature enabled.
Device Configuration: 27-MHz input, 27-MHz output.
Figure 20. fOUT = 27 MHz, VCO Frequency < 125 MHz, SSC
(2% Center)
24
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Figure 21. fOUT = 27 MHz, VCO Frequency > 175 MHz, SSC
(1%, Center)
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Typical Application (continued)
Figure 22. Output Spectrum With SSC Off
Figure 23. Output Spectrum With SSC On, 2% Center
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10 Power Supply Recommendations
There is no restriction on the power-up sequence. In case the VDDOUT is applied first, TI recommends grounding
VDD. In case the VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT.
The device has a power-up control that is connected to the 1.8-V supply. This will keep the whole device
disabled until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal
components, including the outputs. If there is a 3.3-V VDDOUT available before the 1.8-V, the outputs stay
disabled until the 1.8-V supply reaches a certain level.
11 Layout
11.1 Layout Guidelines
When the CDCE913 is used as a crystal buffer, any parasitics across the crystal affects the pulling range of the
VCXO. Therefore, take care placing the crystal units on the board. Crystals must be placed as close to the
device as possible, ensuring that the routing lines from the crystal terminals to XIN and XOUT have the same
length.
If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the
device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise
coupling.
Additional discrete capacitors can be required to meet the load capacitance specification of certain crystal. For
example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can
range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an
internal 10-pF capacitor.
To minimize the inductive influence of the trace, TI recommends placing this small capacitor as close to the
device as possible and symmetrically with respect to XIN and XOUT.
Figure 24 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For
component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
26
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11.2 Layout Example
1
4
3
2
1
3
Place crystal with associated load
caps as close to the chip
Place bypass caps close to the device
pins, ensure wide freq. range
2
Place series termination resistors at
Clock outputs to improve signal integrity
4
Use ferrite beads to isolate the device
supply pins from board noise sources
Figure 24. Annotated Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
VCXO Application Guideline for CDCE(L)9xx Family (SCAA085)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 13. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
CDCE913
Click here
Click here
Click here
Click here
Click here
CDCEL913
Click here
Click here
Click here
Click here
Click here
12.4 Trademarks
DaVinci, OMAP, Pro-Clock are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
Ethernet is a trademark of Xerox Corporation.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CDCE913PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE913
Samples
CDCE913PWG4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE913
Samples
CDCE913PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE913
Samples
CDCE913PWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE913
Samples
CDCEL913PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKEL913
Samples
CDCEL913PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKEL913
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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