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CDCE937-Q1, CDCEL937-Q1
SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
CDCEx937-Q1 Programmable 3-PLL VCXO Clock Synthesizer
With 1.8-V, 2.5-V, and 3.3-V LVCMOS Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Setting
Flexible Input Clocking Concept
– External Crystal: 8 MHz to 32 MHz
– On-Chip VCXO: Pull Range ±150 ppm
– Single-Ended LVCMOS up to 160 MHz
Free Selectable Output Frequency up to 230 MHz
Low-Noise PLL Core
– Integrated PLL Loop Filter Components
– Low Period Jitter (Typical 60 ps)
Separate Output Supply Pins
– CDCE937-Q1: 3.3 V and 2.5 V
– CDCEL937-Q1: 1.8 V
Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2]; for Example: SSC Selection,
Frequency Switching, Output Enable or Power
Down
– Generates Highly Accurate Clocks for Video,
Audio, USB, IEEE1394, RFID, Bluetooth™,
WLAN, Ethernet™, and GPS
– Generates Common Clock Frequencies Used
With TI-DaVinci™, OMAP™, DSPs
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
1.8-V Device Power Supply
Wide Temperature Range –40°C to 125°C
Packaged in TSSOP
Development and Programming Kit for Easy PLL
Design and Programming (TI Pro-Clock™)
Clusters
Head Units
Navigation Systems
Advanced Driver Assistance Systems (ADAS)
3 Description
The CDCE937-Q1 and CDCEL937-Q1 devices are
modular,
phase-locked
loop
(PLL)
based
programmable clock synthesizers. These devices
provide flexible and programmable options, such as
output clocks, input signals, and control pins, so that
the user can configure the CDCEx937-Q1 for their
own specifications.
The CDCEx937-Q1 generates up to seven output
clocks from a single input frequency to enable both
board space and cost savings. Additionally, with
multiple outputs, the clock generator can replace
multiple crystals with one clock generator. This
makes the device well-suited for head unit and
telematics applications in infotainment and camera
systems in ADAS as these platforms are evolving into
smaller and more cost effective systems.
Device Information(1)
PART NUMBER
PACKAGE
CDCE937-Q1,
CDCEL937-Q1
TSSOP (20)
BODY SIZE (NOM)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
VDD
Vddout
GND
Vctr
Crystal or
Clock Input
1
S2/S1/S0 or
SDA/SCL
VCXO
LV
CMOS
Y1
LV
CMOS
Y2
LV
CMOS
Y3
LV
CMOS
Y4
LV
CMOS
Y5
LV
CMOS
Y6
LV
CMOS
Y7
XO
LVCMOS
3
EEPROM
PLL1
with SSC
Programming
and
Control Register
PLL2
with SSC
Divider
and
Output
Control
PLL3
with SSC
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCE937-Q1, CDCEL937-Q1
SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
5
8.1
8.2
8.3
8.4
8.5
8.6
8.7
5
5
5
6
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
9 Parameter Measurement Information ................ 10
10 Detailed Description ........................................... 11
10.1 Overview ............................................................... 11
10.2 Functional Block Diagram ..................................... 12
10.3 Feature Description............................................... 12
10.4 Device Functional Modes...................................... 14
10.5 Programming......................................................... 15
10.6 Register Maps ....................................................... 17
11 Application and Implementation........................ 24
11.1 Application Information.......................................... 24
11.2 Typical Application ................................................ 24
12 Power Supply Recommendations ..................... 28
13 Layout................................................................... 29
13.1 Layout Guidelines ................................................. 29
13.2 Layout Example .................................................... 29
14 Device and Documentation Support ................. 30
14.1
14.2
14.3
14.4
14.5
14.6
14.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
31
15 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2010) to Revision C
Page
•
Changed Applications............................................................................................................................................................. 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
Changes from Revision A (March 2010) to Revision B
Page
•
Changed the PACKAGE THERMAL RESISTANCE table ..................................................................................................... 6
•
Changed RID default in Generic Configuration Register table From: 0h To: Xb ................................................................. 18
•
Added note to PWDN description in Generic Configuration Register table ......................................................................... 18
•
Changed SLAVE_ADR default value in Generic Configuration Register table From: 00b To: 01b ..................................... 18
2
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: CDCE937-Q1 CDCEL937-Q1
CDCE937-Q1, CDCEL937-Q1
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SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
5 Description (continued)
Furthermore, each output can be programmed in-system for any clock frequency up to 230 MHz through the
integrated, configurable PLL. The PLL also supports spread-spectrum clocking (SSC) with programmable down
and center spread. This provides better electromagnetic interference (EMI) performance to enable customers to
pass industry standards such as CISPR-25.
Customization of frequency programming and SSC are accessed using three user-defined control pins. This
eliminates the additional interface requirement to control the clock. Specific power-up and power-down
sequences can also be defined to the user's needs.
6 Device Comparison Table
DEVICE
SUPPLY (V)
PLL
OUTPUT
CDCE913-Q1
2.5 to 3.3
1
3
CDCEL913-Q1
1.8
1
3
CDCE937-Q1
2.5 to 3.3
3
7
CDCEL937-Q1
1.8
3
7
CDCE949-Q1
2.5 to 3.3
4
9
CDCEL949-Q1
1.8
4
9
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: CDCE937-Q1 CDCEL937-Q1
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CDCE937-Q1, CDCEL937-Q1
SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
www.ti.com
7 Pin Configuration and Functions
PW Package
20-Pin TSSOP
Top View
Xin/Clk
S0
Vdd
Vctr
GND
Vddout
Y4
Y5
GND
Vddout
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Xout
S1/SDA
S2/SCL
Y1
GND
Y2
Y3
Vddout
Y6
Y7
Pin Functions
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
1
Xin/CLK
I
Crystal oscillator input or LVCMOS clock input (selectable through SDA and SCL bus)
2
S0
I
User-programmable control input S0; LVCMOS inputs; Internal pullup 500 k
3
VDD
P
1.8-V power supply for the device
4
VCtrl
I
VCXO control voltage (leave open or pull up to approximately 500 k when not used)
5
GND
G
Ground
6
Vddout
P
CDCE937-Q1: 3.3-V or 2.5-V supply for all outputs
CDCEL937-Q1: 1.8-V supply for all outputs
7
Y4
O
LVCMOS outputs
8
Y5
O
LVCMOS outputs
9
GND
G
Ground
10
Vddout
P
CDCE937-Q1: 3.3-V or 2.5-V supply for all outputs
CDCEL937-Q1: 1.8-V supply for all outputs
11
Y7
O
LVCMOS outputs
12
Y6
O
LVCMOS outputs
13
Vddout
P
CDCE937-Q1: 3.3-V or 2.5-V supply for all outputs
CDCEL937-Q1: 1.8-V supply for all outputs
14
Y3
O
LVCMOS outputs
15
Y2
O
LVCMOS outputs
16
GND
G
Ground
17
Y1
O
LVCMOS outputs
18
SCL/S2
I
SCL: serial clock input(default configuration), LVCMOS internal pullup 500 k; or
S2: user-programmable control input, LVCMOS inputs, and internal pullup 500 k
19
SDA/S1
I/O or I
20
Xout
O
(1)
4
SDA: bidirectional serial data input/output (default configuration). LVCMOS internal pullup 500 k; or
S1: user-programmable control input, LVCMOS inputs, and internal pullup 500 k
Crystal oscillator output (leave open or pull up to approximately 500 k when not used)
G = Ground, I = Input, O = Output, P = Power
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: CDCE937-Q1 CDCEL937-Q1
CDCE937-Q1, CDCEL937-Q1
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SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VDD
MIN
MAX
UNIT
–0.5
2.5
V
V
(2) (3)
–0.5
VDD + 0.5
Output voltage, VO (2)
–0.5
Vddout + 0.5
V
20
mA
50
mA
150
°C
Input voltage, VI
Input current, II (VI < 0 and VI > VDD)
Continuous output current, IO
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions.
8.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM),
per AEC Q100-011
UNIT
±2000
All pins
±500
Corner pins
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Device supply voltage
VO
Output Yx supply voltage, Vddout
VIL
Low-level input voltage LVCMOS
VIH
High-level input voltage LVCMOS
MIN
NOM
MAX
1.7
1.8
1.9
CDCE937-Q1
2.3
3.6
CDCEL937-Q1
1.7
1.9
0.3 × VDD
0.7 × VDD
VI(thresh) Input voltage threshold LVCMOS
VIS
Input voltage
VI(CLK)
Input voltage range CLK
IOH /IOL
CL
Output load LVCMOS
TA
Ambient temperature
V
V
V
V
0.5 × VDD
V
S0
0
1.9
S1, S2, SDA, SCL; VI(thresh) = 0.5 VDD
0
3.6
0
Output current
UNIT
1.9
Vddout = 3.3 V
±12
Vddout = 2.5 V
±10
Vddout = 1.8 V
±8
–40
V
V
mA
10
pF
125
°C
32
MHz
CRYSTAL/VCXO (1)
fXtal
Crystal input frequency (fundamental mode)
ESR
Effective series resistance
fPR
Pulling range (0 V ≤ Vctrl ≤ 1.8 V) (2)
Vctrl
Frequency control voltage
C0/C1
Pullability ratio
CL
On-chip load capacitance at Xin and Xout
(1)
(2)
8
27
100
±120
0
±150
Ω
ppm
VDD
V
220
0
20
pF
For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family
(SCAA085).
Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ± 120 ppm
applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: CDCE937-Q1 CDCEL937-Q1
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CDCE937-Q1, CDCEL937-Q1
SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
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8.4 Thermal Information
over operating free-air temperature range (unless otherwise noted) (1)
CDCE937-Q1, CDCEL937-Q1
THERMAL METRIC
(2)
PW (TSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
Airflow = 0 lfm
89
Airflow = 150 lfm
75
Airflow = 200 lfm
74
Airflow = 250 lfm
74
Airflow = 500 lfm
69
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31
°C/W
RθJB
Junction-to-board thermal resistance
55
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
49
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
(2)
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
over recommended operating ambient temperature range (unless otherwise noted)
PARAMETER
IDD
IDDOUT
TEST CONDITIONS
Supply current (see Figure 1)
All outputs off, f(CLK) = 27 MHz, All PLLS on
f(VCO) = 135 MHz
Per PLL
Output supply current (see Figure 2)
No load, all outputs on,
fOUT = 27 MHz
Power-down current
V(PUC)
Supply voltage Vdd threshold for power-up
control circuit
f(VCO)
VCO frequency range of PLL
LVCMOS output frequency
TYP (1)
MAX
29
CDCE937,
VDDOUT = 3.3 V
3.1
CDCEL937,
VDDOUT = 1.8 V
1.5
UNIT
mA
9
mA
Every circuit powered down except SDA and SCL,
fIN = 0 MHz, VDD = 1.9 V
IDD(PD)
fOUT
MIN
50
µA
0.85
1.45
V
80
230
MHz
Vddout = 3.3 V
230
Vddout = 1.8 V
230
MHz
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VDD = 1.7 V, II = –18 mA
II
LVCMOS input current
VI = 0 V or VDD, VDD = 1.9 V
IIH
LVCMOS input current for S0/S1/S2
IIL
LVCMOS input current for S0/S1/S2
Input capacitance at Xin/Clk
VI(Clk) = 0 V or VDD
6
Input capacitance at Xout
VI(Xout) = 0 V or VDD
2
Input capacitance at S0/S1/S2
VIS = 0 V or VDD
3
CI
–1.2
V
±5
µA
VI = VDD, VDD = 1.9 V
5
µA
VI = 0 V, VDD = 1.9 V
–6
µA
pF
LVCMOS PARAMETER, Vddout = 3.3 V (CDCE937)
VOH
VOL
LVCMOS high-level output voltage
LVCMOS low-level output voltage
Vddout = 3 V, IOH = –0.1 mA
2.9
Vddout = 3 V, IOH = –8 mA
2.4
Vddout = 3 V, IOH = –12 mA
2.2
V
Vddout = 3 V, IOL = 0.1 mA
0.1
Vddout = 3 V, IOL = 8 mA
0.5
Vddout = 3 V, IOL = 12 mA
0.8
V
tPLH,
tPHL
Propagation delay
All PLL bypass
3.2
ns
tr/tf
Rise and fall time
Vddout= 3.3 V (20%–80%)
0.6
ns
(1)
6
All typical values are at respective nominal VDD.
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SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
Electrical Characteristics (continued)
over recommended operating ambient temperature range (unless otherwise noted)
TYP (1)
MAX
1 PLL switching, Y2-to-Y3
60
90
3 PLL switching, Y2-to-Y7
100
150
1 PLL switching, Y2-to-Y3
70
100
3 PLL switching, Y2-to-Y7
120
180
PARAMETER
tjit(cc)
Cycle-to-cycle jitter (2) (3)
tjit(per)
Peak-to-peak period jitter (3)
tsk(o)
Output skew (see Table 2) (4)
odc
Output duty cycle (5)
TEST CONDITIONS
MIN
fOUT = 50 MHz, Y1-to-Y3
60
fOUT = 50 MHz, Y2-to-Y5
160
fVCO = 100 MHz, Pdiv = 1
45%
UNIT
ps
ps
ps
55%
LVCMOS PARAMETER, Vddout = 2.5 V (CDCE937)
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
Vddout = 2.3 V, IOH = –0.1 mA
2.2
Vddout = 2.3 V, IOH = –6 mA
1.7
Vddout = 2.3 V, IOH = –10 mA
1.6
V
Vddout = 2.3 V, IOL = 0.1 mA
0.1
Vddout = 2.3 V, IOL = 6 mA
0.5
Vddout = 2.3 V, IOL = 10 mA
0.7
tPLH,
tPHL
Propagation delay
All PLL bypass
3.4
tr/tf
Rise and fall time
Vddout = 2.5 V (20%–80%)
0.8
1 PLL switching, Y2-to-Y3
60
90
3 PLL switching, Y2-to-Y7
100
150
1 PLL switching, Y2-to-Y3
70
100
3 PLL switching, Y2-to-Y7
120
180
tjit(cc)
Cycle-to-cycle jitter (2)
(3)
tjit(per)
Peak-to-peak period jitter (4)
tsk(o)
Output skew (see Table 2) (4)
odc
Output duty cycle (5)
ns
ns
fOUT = 50 MHz, Y1-to-Y3
60
fOUT = 50 MHz, Y2-to-Y5
160
f(VCO) = 100 MHz, Pdiv = 1
45%
V
ps
ps
ps
55%
LVCMOS PARAMETER, Vddout = 1.8 V (CDCEL937)
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
Vddout = 1.7 V, IOH = –0.1 mA
1.6
Vddout = 1.7 V, IOH = –4 mA
1.4
Vddout = 1.7 V, IOH = –8 mA
1.1
V
Vddout = 1.7 V, IOL = 0.1 mA
0.1
Vddout = 1.7 V, IOL = 4 mA
0.3
Vddout = 1.7 V, IOL = 8 mA
0.6
tPLH,
tPHL
Propagation delay
All PLL bypass
2.6
tr/tf
Rise and fall time
Vddout= 1.8 V (20%–80%)
0.7
1 PLL switching, Y2-to-Y3
70
120
3 PLL switching, Y2-to-Y7
100
150
1 PLL switching, Y2-to-Y3
90
140
3 PLL switching, Y2-to-Y7
120
190
tjit(cc)
Cycle-to-cycle jitter (2)
(3)
tjit(per)
Peak-to-peak period jitter (3)
tsk(o)
Output skew (see Table 2) (4)
odc
Output duty cycle (5)
ns
ns
fOUT = 50 MHz, Y1-to-Y3
60
fOUT = 50 MHz, Y2-to-Y5
160
f(VCO) = 100 MHz, Pdiv = 1
45%
V
ps
ps
ps
55%
SDA and SCL PARAMETER
VIK
SCL and SDA input clamp voltage
VDD = 1.7 V, II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD, VDD = 1.9 V
±10
µA
VIH
SDA and SCL input high voltage (6)
(2)
(3)
(4)
(5)
(6)
0.7 × VDD
V
10000 cycles.
Jitter depends on configuration. Data is taken under the following conditions: 1-PLL : fIN = 27MHz, Y2/3 = 27 MHz, (measured at Y2), 3PLL: fIN = 27 MHz, Y2/3 = 27 MHz (measured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz
The tsk(o) specification is only valid for equal loading of each bank of outputs, and outputs are generated from the same divider; data
taking on rising edge (tr).
odc depends on output rise and fall time (tr / tf).
SDA and SCL pins are 3.3 V tolerant.
Copyright © 2010–2016, Texas Instruments Incorporated
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CDCE937-Q1, CDCEL937-Q1
SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
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Electrical Characteristics (continued)
over recommended operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
(6)
VIL
SDA and SCL input low voltage
VOL
SDA low-level output voltage
IOL = 3 mA, VDD = 1.7 V
CI
SCL/SDA Input capacitance
VI = 0 V or VDD
MAX
0.3 × VDD
UNIT
V
0.2 × VDD
V
10
pF
3
EEPROM
EEcyc
Programming cycles of EEPROM
EEret
Data retention
1000
cycles
10
years
8.6 Timing Requirements
over recommended ranges of supply voltage, load, and operating ambient temperature (see Figure 12)
MIN
NOM
MAX
UNIT
CLK_IN
fCLK
LVCMOS clock input frequency
tr / tf
Rise and fall time CLK signal (20% to 80%)
dutyCLK
Duty cycle CLK at VDD/2
PLL bypass mode
0
160
PLL mode
8
160
40%
60%
Standard mode
0
100
Fast mode
0
400
3
MHz
ns
SDA and SCL
fSCL
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
SCL high-pulse duration
th(SDA)
SDA hold time (SDA valid after SCL low)
tsu(SDA)
SDA setup time
tr
SCL/SDA input rise time
tf
SCL/SDA input fall time, standard mode and fast mode
0.6
Standard mode
Fast mode
0.6
Standard mode
4.7
Fast mode
1.3
µs
µs
0.6
Standard mode
0
3.45
Fast mode
0
0.9
Standard mode
250
Fast mode
100
300
300
Standard mode
4
Fast mode
0.6
Standard mode
4.7
Fast mode
1.3
µs
ns
1000
Fast mode
Bus free time between a STOP and START condition
µs
4
Standard mode
tBUS
µs
4
Fast mode
STOP setup time
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4.7
Fast mode
Standard mode
tsu(STOP)
8
Standard mode
kHz
ns
ns
µs
µs
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8.7 Typical Characteristics
30
80
VDD = 1.8 V
70
25
7 Outputs on
60
20
2 PLL on
50
IDDOUT - mA
IDD - Supply Current - mA
3 PLL on
VDD = 1.8 V,
VDDOUT = 3.3 V,
No Load
40
30
1 PLL on
5 Outputs on
15
1 Output on
10
3 Outputs on
20
all PLL off
5
10
0
10
60
110
160
fVCO - Frequency - MHz
All Outputs off
0
10
210
30
50 70 90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 2. CDCE937-Q1 Output Current
vs Output Frequency
Figure 1. CDCEx937-Q1 Supply Current
vs PLL Frequency
12
10
VDD = 1.8 V,
VDDOUT = 1.8 V,
No Load
7 Outputs
IDDOUT - mA
8
5 Outputs on
6
3 Output on
4
1 Output on
2
0
10
all Outputs
30
50
70
90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 3. CDCEL937-Q1 Output Current vs Output Frequency
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9 Parameter Measurement Information
CDCE937
CDCEL937
1k
LVCMOS
1k
10 pF
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Figure 4. Test Load
CDCE937
CDCEL937
LVCMOS
LVCMOS
Typical Driver
Impedance
~ 32 :
Series
Termination
~ 18 :
Line Impedance
Zo = 50 :
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Figure 5. Test Load for 50-Ω Board Environment
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10 Detailed Description
10.1 Overview
The CDCE937-Q1 and CDCEL937-Q1 devices are modular PLL-based low-cost high-performance
programmable clock synthesizers, multipliers, and dividers. It generates up to seven output clocks from a single
input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to
three independent configurable PLLs.
The CDCEx937-Q1 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL937-Q1 and from 2.5 V
to 3.3 V for CDCE937-Q1.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.
Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external
control signal (that is, PWM signal).
The deep M/N divider ratio allows the generation of zero ppm audio or video, networking (WLAN, Bluetooth,
Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as
27 MHz.
All PLLs supports SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking which is
a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports non-volatile EEPROM programming for ease-customized application. It is preset to a factory
default configuration (see Default Device Setting). It can be reprogrammed to a different application configuration
before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable
through SDA and SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including
frequency selection changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing
between low level or 3-state for output-disable function.
The CDCEx937-Q1 operates in 1.8-V environment. It is characterized for operation from –40°C to 125°C.
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10.2 Functional Block Diagram
VDD
Vddout
GND
Input Clock
LV
CMOS
Y1
M2
LV
CMOS
Y2
M3
LV
CMOS
Y3
M4
LV
CMOS
Y4
M5
LV
CMOS
Y5
M6
Xin/CLK
LV
CMOS
Y6
M7
Pdiv1
M1
Vctr
LV
CMOS
Y7
10-Bit
VCXO
XO
Xout
Pdiv2
MUX1
PLL1
with SSC
LVCMOS
7-Bit
Pdiv3
S0
S1/SDA
S2/SCL
Programming
and
SDA/SCL
Register
PLL Bypass
7-Bit
PLL 2
Pdiv4
with SSC
7-Bit
MUX2
EEPROM
Pdiv6
MUX3
PLL 3
with SSC
Pdiv5
7-Bit
PLL Bypass
7-Bit
Pdiv7
7-Bit
PLL Bypass
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10.3 Feature Description
10.3.1 Control Terminal Setting
The CDCEx937-Q1 has three user-definable control terminals (S0, S1, and S2) that allow external control of
device settings. They can be programmed to any of the following setting:
• Spread spectrum clocking selection → spread type and spread amount selection
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
EXTERNAL
CONTROL
BITS
Control
Function
12
PLL1 SETTING
PLL
Frequency
Selection
SSC
Selection
PLL2 SETTING
Output
Y2/Y3
Selection
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PLL
Frequency
Selection
SSC
Selection
PLL3 SETTING
Output
Y4/Y5
Selection
PLL
Frequency
Selection
SSC
Selection
Y1 SETTING
Output
Y6/Y7
Selection
Output Y1 and
Power-Down
Selection
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Table 2. PLLx Setting (Can Be Selected For Each PLL Individual) (1)
SSC SELECTION (CENTER/DOWN)
SSCx [3-BITS]
CENTER
DOWN
0
0
0
0% (off)
0% (off)
0
0
1
±0.25%
–0.25%
0
1
0
±0.5%
–0.5%
0
1
1
±0.75%
–0.75%
1
0
0
±1.0%
–1.0%
1
0
1
±1.25%
–1.25%
1
1
0
±1.5%
–1.5%
1
1
1
±2.0%
–2.0%
FREQUENCY SELECTION (2)
FSx
FUNCTION
0
Frequency0
1
Frequency1
OUTPUT SELECTION (3) (Y2 ... Y7)
(1)
(2)
(3)
YxYx
FUNCTION
0
State0
1
State1
Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;
Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low or active
Table 3. Y1 Setting (1)
Y1 SELECTION
(1)
Y1
FUNCTION
0
State 0
1
State 1
State0 and State1 are user definable in Generic Configuration
Register and can be power down, 3-state, low, or active.
S1/SDA and S2/SCL pins of the CDCEx937-Q1 are dual function pins. In default configuration they are defined
as SDA and SCL for the serial interface. They can be programmed as control-pins (S1/S2) by setting the relevant
bits in the EEPROM. Note that the changes to the Control register (Bit [6] of Byte [02]) have no effect until they
are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins (SDA and SCL).
S0 is not a multi-use pin, it is a control pin only.
10.3.2 Default Device Setting
The internal EEPROM of CDCEx937-Q1 is preconfigured as shown in Figure 6. The input frequency is passed
through to the output as a default. This allows the device to operate in default mode without the extra production
step of program it. The default setting appears after power is supplied or after power-down or power-up
sequence until it is re-programmed by the user to a different application configuration. A new register setting is
programmed through the serial SDA and SCL interface.
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VDD
Vddout
GND
PLL 2
power down
Pdiv4 = 1
Pdiv5 = 1
PLL Bypass
PLL3
LV
CMOS
Y4 = 27 MHz
LV
CMOS
Y5 = 27 MHz
Pdiv6 = 1
LV
CMOS
Y6 = 27 MHz
LV
CMOS
Y7 = 27 MHz
MUX3
power down
M2
SCL
M3
SDA
Programming Bus
Y3 = 27 MHz
MUX2
“0” = outputs 3-State
LV
CMOS
M4
Programming
and
SDA/SCA
Register
S0
Pdiv3 = 1
PLL Bypass
EEPROM
“1” = outputs enabled
Pdiv2 = 1
MUX1
Xout
Y2 = 27 MHz
M5
PLL1
LV
CMOS
Pdiv1 =1
X-tal
power down
Y1 = 27MHz
M6
27 MHz
Crystal
LV
CMOS
M7
M1
Input Clock
Xin
Pdiv7 = 1
PLL Bypass
Figure 6. Default Device Setting
Table 4 shows the factory default setting for the Control Terminal Register (external control pins). In normal
operation, all 8 register settings are available, but in the default configuration only the first two settings (0 and 1)
can be selected with S0, as S1 and S2 configured as programming pins in default mode.
Table 4. Factory Default Setting for Control Terminal Register (1)
Y1
EXTERNAL CONTROL PINS
OUTPUT
SELECT
PLL1 SETTINGS
FREQ.
SELECT
SSC
SELECT
PLL2 SETTINGS
OUTPUT
SELECT
FREQ.
SELECT
SSC
SELECT
PLL3 SETTINGS
OUTPUT
SELECT
FREQ.
SELECT
SSC
SELECT
OUTPUT
SELECT
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
SCL (I2C)
SDA (I2C)
0
3-state
fVCO1_0
off
3-state
fVCO2_0
off
3-state
fVCO1_0
off
3-state
SCL (I2C)
SDA (I2C)
1
Enabled
fVCO1_0
off
Enabled
fVCO2_0
off
Enabled
fVCO1_0
off
Enabled
(1)
In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA and SCL. They do not have
any control-pin function but they are internally interpreted as if S1 = 0 and S2 = 0. However, S0 is a control-pin which in the default
mode switches all outputs ON or OFF (as previously predefined).
10.4 Device Functional Modes
10.4.1 SDA and SCL Serial Interface
The CDCEx937-Q1 operates as a slave device of the 2-wire serial SDA and SCL bus, compatible with the
popular SMBus or I2C specification. It operates in the standard-mode transfer (up to 100kbit/s) and fast-mode
transfer (up to 400kbit/s) and supports 7-bit addressing.
The S1/SDA and S2/SCL pins of the CDC9xx are dual function pins. In the default configuration they are used as
SDA and SCL serial programming interface. They can be re-programmed as general purpose control pins, S1
and S2, by changing the corresponding EEPROM setting, Byte 02, Bit [6].
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10.5 Programming
10.5.1 Data Protocol
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of
Bytes read-out are defined by Byte Count in the Generic Configuration Register. At Block Read instruction all
bytes defined in the Byte Count has to be readout to correctly finish the read cycle.
Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to
each transferred byte independent of whether this is a Byte Write or a Block Write sequence.
If the EEPROM Write Cycle is initiated, the internal SDA register contents are written into the EEPROM. During
this write cycle, data is not accepted at the SDA and SCL bus until the write cycle is completed. However, data
can be read during the programming sequence (Byte Read or Block Read). The programming status can be
monitored by reading EEPIP, Byte 01–Bit [6].
The offset of the indexed byte is encoded in the command code, as described in Table 5.
Table 5. Slave Receiver Address (7 Bits)
(1)
DEVICE
A6
A5
A4
A3
A2
A1 (1)
A0 (1)
R/W
CDCEx913
1
1
0
0
1
0
1
1/0
CDCEx925
1
1
0
0
1
0
0
1/0
CDCEx937
1
1
0
1
1
0
1
1/0
CDCEx949
1
1
0
1
1
0
0
1/0
Address bits A0 and A1 are programmable through the SDA and SCL bus (Byte 01, Bit [1:0]). This allows addressing up to 4 devices
connected to the same SDA and SCL bus. The least-significant bit of the address byte designates a write or read operation.
10.5.2 Command Code Definition
Table 6. Command Code Definition
BIT
7
(6:0)
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
10.5.3 Generic Programming Sequence
1
S
7
Slave Address
MSB
LSB
S
Start Condition
Sr
Repeated Start Condition
R/W
1
R/W
1
A
8
Data Byte
MSB
1
A
1
P
LSB
1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx
A
Acknowledge (ACK = 0 and NACK =1)
P
Stop Condition
Master-to-Slave Transmission
Slave-to-Master Transmission
Figure 7. Generic Programming Sequence
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10.5.4 Byte Write Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
CommandCode
1
A
8
Data Byte
1
A
1
P
7
Slave Address
1
Rd
1
A
1
A
1
P
Figure 8. Byte Write Protocol
10.5.5 Byte Read Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
Data Byte
1
A
1
P
8
CommandCode
1
A
1
S
Figure 9. Byte Read Protocol
10.5.6 Block Write Programming Sequence
1
S
(1)
7
Slave Address
1
Wr
8
Data Byte 0
1
A
1
A
8
CommandCode
8
Data Byte 1
1
A
1
A
8
Byte Count = N
1
A
8
Data Byte N-1
…
Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose
and must not be overwritten.
Figure 10. Block Write Protocol
10.5.7 Block Read Programming Sequence
1
S
7
Slave Address
1
Wr
8
Byte Count N
1
A
1
A
8
CommandCode
8
Data Byte 0
1
A
1
A
1
Sr
…
7
Slave Address
1
Rd
1
A
8
Data Byte N-1
1
A
1
P
Figure 11. Block Read Protocol
10.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
P
S
tw(SCLL)
Bit 7 (MSB)
tw(SCLH)
Bit 6
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tsu(START)
th(START)
tsu(SDA)
th(SDA)
t(BUS)
tr
tsu(STOP)
tf
VIH
SDA
VIL
Figure 12. Timing Diagram for SDA and SCL Serial Control Interface
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10.5.9 SDA and SCL Hardware Interface
Figure 13 shows how the CDCEx937-Q1 clock synthesizer is connected to the SDA and SCL serial interface
bus. Multiple devices can be connected to the bus but the speed may require reduction if many devices are
connected (400 kHz is the maximum).
Note that the pullup resistors (RP) depends on the supply voltage, bus capacitance, and number of connected
devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at VOLmax =
0.4 V for the output stages (for more details see SMBus or I2C Bus specification).
CDCE937
CDCEL937
RP
Slave
RP
Master
SDA
SCL
CBUS
CBUS
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Figure 13. SDA and SCL Hardware Interface
10.6 Register Maps
10.6.1 SDA and SCL Configuration Registers
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCEx937-Q1. All settings can be manually written
into the device through the SDA and SCL bus or easily programmed by using the TI Pro-Clock software. TI ProClock software allows the user to quickly make all settings and automatically calculates the values for optimized
performance at lowest jitter.
Table 7. SDA and SCL Registers
ADDRESS OFFSET
REGISTER DESCRIPTION
TABLE
00h
Generic Configuration Register
Table 9
10h
PLL1 Configuration Register
Table 10
20h
PLL2 Configuration Register
Table 11
30h
PLL3 Configuration Register
Table 12
The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the
Control Terminal Register. The user can predefine up to eight different control settings. These settings then can
be selected by the external control pins, S0, S1, and S2 (see the Control Terminal Configuration section).
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Table 8. Configuration Register, External Control Terminals
Y1
EXTERNAL
CONTROL
PINS
OUTPUT
SELECT
PLL1 SETTINGS
FREQ.
SELECT
SSC
SELECT
PLL2 SETTINGS
OUTPUT
SELECT
FREQ.
SELECT
SSC
SELECT
PLL3 SETTINGS
OUTPUT
SELECT
FREQ.
SELECT
SSC
SELECT
OUTPUT
SELECT
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
FS2
SSC2
Y4Y5
FS3
SSC3
Y6Y7
0
0
0
0
Y1_0
FS1_0
SSC1_0
Y2Y3_0
FS2_0
SSC2_0
Y4Y5_0
FS3_0
SSC3_0
Y6Y7_0
1
0
0
1
Y1_1
FS1_1
SSC1_1
Y2Y3_1
FS2_1
SSC2_1
Y4Y5_1
FS3_1
SSC3_1
Y6Y7_1
2
0
1
0
Y1_2
FS1_2
SSC1_2
Y2Y3_2
FS2_2
SSC2_2
Y4Y5_2
FS3_2
SSC3_2
Y6Y7_2
3
0
1
1
Y1_3
FS1_3
SSC1_3
Y2Y3_3
FS2_3
SSC2_3
Y4Y5_3
FS3_3
SSC3_3
Y6Y7_3
4
1
0
0
Y1_4
FS1_4
SSC1_4
Y2Y3_4
FS2_4
SSC2_4
Y4Y5_4
FS3_4
SSC3_4
Y6Y7_4
5
1
0
1
Y1_5
FS1_5
SSC1_5
Y2Y3_5
FS2_5
SSC2_5
Y4Y5_5
FS3_5
SSC3_5
Y6Y7_5
6
1
1
0
Y1_6
FS1_6
SSC1_6
Y2Y3_6
FS2_6
SSC2_6
Y4Y5_6
FS3_6
SSC3_6
Y6Y7_6
7
1
1
1
Y1_7
FS1_7
SSC1_7
Y2Y3_7
FS2_7
SSC2_7
Y4Y5_7
FS3_7
SSC3_7
Y6Y7_7
04h
13h
10h to 12h
15h
23h
20h to 22h
25h
33h
30h to 32h
35h
Address Offset (1)
(1)
Address Offset refers to the byte address in the Configuration Register in the following pages.
Table 9. Generic Configuration Register
OFFSET (1)
00h
BIT (2)
ACRONYM
DEFAULT (3)
7
E_EL
Xb
Device identification (read-only): 1 is CDCE937-Q1 (3.3 V), 0 is CDCEL937-Q1 (1.8 V)
6:4
RID
Xb
Revision Identification Number (read only)
3:0
VID
1h
Vendor Identification Number (read only)
7
–
0b
Reserved – always write 0
6
EEPIP
0b
5
EELOCK
0b
DESCRIPTION
EEPROM Programming Status: (4) (read only)
0 – EEPROM programming is completed
1 – EEPROM is in programming mode
Permanently Lock EEPROM Data (5)
0 – EEPROM is not locked
1 – EEPROM is permanently locked
Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
01h
4
PWDN
0b
0 – device active (PLL1 and all outputs are enabled)
1 – device power down (PLL1 in power down and all outputs in 3-state)
3:2
INCLK
00b
Input clock selection:
1:0
SLAVE_AD
R
01b
Programmable Address Bits A0 and A1 of the Slave Receiver Address
00 – Xtal
01 – VCXO
10 – LVCMOS
7
M1
1b
Clock source selection for output Y1:
0 – input clock
11 – reserved
1 – PLL1 clock
Operation mode selection for pin 18/19 (6)
02h
6
SPICON
0b
5:4
Y1_ST1
11b
3:2
Y1_ST0
01b
1:0
Pdiv1 [9:8]
7:0
Pdiv1 [7:0]
(1)
(2)
(3)
(4)
(5)
(6)
18
Y1-State0/1 Definition
00 – device power down (all PLLs in power down and all outputs in 3State)
01 – Y1 disabled to 3-state
10-Bit Y1-Output-Divider Pdiv1:
001h
03h
0 – serial programming interface SDA (pin 19) and SCL (pin 18)
1 – control pins S1 (pin 19) and S2 (pin 18)
10 – Y1 disabled to low
11 – Y1 enabled
0 – divider reset and stand-by
1-to-1023 – divider value
Writing data beyond ‘40h’ may affect device function.
All data transferred with the MSB first.
Unless customer-specific setting.
During EEPROM programming, no data is allowed to be sent to the device through the SDA and SCL bus until the programming
sequence is completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).
If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. There is no further programming
possible. Data, however can still be written through SDA and SCL bus to the internal register to change device function on the fly. But
new data can no longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM!
Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no
longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA
and SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
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SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
Table 9. Generic Configuration Register (continued)
OFFSET
(1)
ACRONYM
DEFAULT (3)
7
Y1_7
0b
6
Y1_6
0b
5
Y1_5
0b
4
Y1_4
0b
3
Y1_3
0b
2
Y1_2
0b
1
Y1_1
1b
0
Y1_0
0b
BIT
(2)
DESCRIPTION
Y1_ST0/Y1_ST1 State Selection (7)
0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
04h
Crystal Load Capacitor
Selection (8)
7:3
XCSEL
0Ah
00h → 0 pF
01h → 1 pF
02h → 2 pF
:
14h-to-1Fh → 20 pF
Vctr
Xin
20pF
6pF*
C1
05h
XO
Xout
2pF*
2:0
0b
Reserved – do not write other than 0
BCOUNT
40h
7-Bit Byte Count (defines the number of bytes which is sent from this device at the next Block Read transfer); all bytes have to
be read out to correctly finish the read cycle.)
0
EEWRITE
0b
Initiate EEPROM Write
Cycle(4) (9)
—
0h
Unused address range
07h-0Fh
(9)
20pF
7:1
06h
(8)
i.e.
XCSEL = 10pF
C2
* Input Capacitance
(7)
VCXO
0– no EEPROM write cycle
1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)
These are the bits of the Control Terminal Register. The user can predefine up to eight different control settings. These settings then
can be selected by the external control pins, S0, S1, and S2.
The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors must be used only to
finely adjust CL by a few pF's. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF.
For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which always
adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see VCXO
Application Guideline for CDCE(L)9xx Family (SCAA085).
Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The
EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The
EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out
EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
Table 10. PLL1 Configuration Register
OFFSET
10h
11h
12h
(1)
(2)
(3)
(4)
(1)
ACRONYM
DEFAULT (3)
7:5
SSC1_7 [2:0]
000b
4:2
SSC1_6 [2:0]
000b
1:0
SSC1_5 [2:1]
7
SSC1_5 [0]
6:4
SSC1_4 [2:0]
000b
3:1
SSC1_3 [2:0]
000b
0
SSC1_2 [2]
7:6
SSC1_2 [1:0]
5:3
SSC1_1 [2:0]
000b
2:0
SSC1_0 [2:0]
000b
BIT
(2)
000b
000b
DESCRIPTION
SSC1: PLL1 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
Writing data beyond 40h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 10. PLL1 Configuration Register (continued)
OFFSET
13h
14h
15h
16h
17h
18h
19h
1Ah
(1)
ACRONYM
DEFAULT (3)
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
7
MUX1
1b
PLL1 Multiplexer:
0 – PLL1
1 – PLL1 Bypass (PLL1 is in power down)
6
M2
1b
Output Y2 Multiplexer:
0 – Pdiv1
1 – Pdiv2
5:4
M3
10b
Output Y3 Multiplexer:
00 –
01 –
10 –
11 –
3:2
Y2Y3_ST1
11b
00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State
10–Y2/Y3 disabled to low
11 – Y2/Y3 enabled
BIT
(2)
1Dh
1Eh
Pdiv1-Divider
Pdiv2-Divider
Pdiv3-Divider
reserved
1:0
Y2Y3_ST0
01b
7
Y2Y3_7
0b
Y2Y3_x Output State Selection (4)
6
Y2Y3_6
0b
5
Y2Y3_5
0b
4
Y2Y3_4
0b
3
Y2Y3_3
0b
2
Y2Y3_2
0b
1
Y2Y3_1
1b
0
Y2Y3_0
0b
7
SSC1DC
0b
PLL1 SSC down/center selection:
0 – down
6:0
Pdiv2
01h
7-Bit Y2-Output-Divider Pdiv2:
0 – reset and stand-by
7
—
0b
Reserved – do not write others than 0
6:0
Pdiv3
01h
7-Bit Y3-Output-Divider Pdiv3:
7:0
PLL1_0N [11:4]
7:4
PLL1_0N [3:0]
004h
PLL1_0: 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information, see PLL Multiplier or Divider Definition).
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
010b
1:0
VCO1_0_RANGE
00b
7:0
PLL1_1N [11:4]
7:4
PLL1_1N [3:0]
3:0
PLL1_1R [8:5]
7:3
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
010b
1:0
VCO1_1_RANGE
00b
0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
0 – reset and stand-by
1-to-127 is divider value
1-to-127 is divider value
10h
fVCO1_0 range selection:
004h
00 –
01 –
10 –
11 –
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
PLL1_1: 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information, see PLL Multiplier or Divider Definition).
000h
10h
fVCO1_1 range selection:
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1 – center
000h
1Fh
20
0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
Y2, Y3State0/1definition:
1Bh
1Ch
DESCRIPTION
FS1_x: PLL1 Frequency Selection (4)
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
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SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
Table 11. PLL2 Configuration Register
OFFSET
20h
21h
22h
23h
24h
25h
26h
27h
(1)
(2)
(3)
(4)
(1)
ACRONYM
DEFAULT (3)
7:5
SSC2_7 [2:0]
000b
4:2
SSC2_6 [2:0]
000b
1:0
SSC2_5 [2:1]
7
SSC2_5 [0]
6:4
SSC2_4 [2:0]
000b
3:1
SSC2_3 [2:0]
000b
0
SSC2_2 [2]
7:6
SSC2_2 [1:0]
5:3
SSC2_1 [2:0]
000b
2:0
SSC2_0 [2:0]
000b
7
FS2_7
0b
6
FS2_6
0b
5
FS2_5
0b
4
FS2_4
0b
3
FS2_3
0b
2
FS2_2
0b
1
FS2_1
0b
0
FS2_0
0b
7
MUX2
1b
6
M4
1b
Output Y4 Multiplexer: 0 – Pdiv2
1 – Pdiv4
5:4
M5
10b
Output Y5 Multiplexer: 00 –
01 –
10 –
11 –
3:2
Y4Y5_ST1
11b
1:0
Y4Y5_ST0
01b
7
Y4Y5_7
0b
6
Y4Y5_6
0b
5
Y4Y5_5
0b
4
Y4Y5_4
0b
3
Y4Y5_3
0b
2
Y4Y5_2
0b
1
Y4Y5_1
1b
0
Y4Y5_0
0b
7
SSC2DC
0b
6:0
Pdiv4
7
—
6:0
Pdiv5
BIT
(2)
000b
000b
DESCRIPTION
SSC2: PLL2 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS2_x: PLL2 Frequency Selection (4)
0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
PLL2 Multiplexer:
Y4, Y5State0/1definition:
0 – PLL2
1 – PLL2 Bypass (PLL2 is in power down)
Pdiv2-Divider
Pdiv4-Divider
Pdiv5-Divider
reserved
00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State
10–Y4/Y5 disabled to low
11 – Y4/Y5 enabled
Y4Y5_x Output State Selection (4)
0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
PLL2 SSC down/center selection:
0 – down
1 – center
01h
7-Bit Y4-Output-Divider Pdiv4:
0 – reset and stand-by
0b
Reserved – do not write others than 0
01h
7-Bit Y5-Output-Divider Pdiv5:
0 – reset and stand-by
1-to-127 – divider value
1-to-127 – divider value
Writing data beyond 40h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 11. PLL2 Configuration Register (continued)
OFFSET
(1)
28h
29h
2Ah
BIT
(2)
ACRONYM
DEFAULT (3)
7:0
PLL2_0N [11:4
7:4
PLL2_0N [3:0]
3:0
PLL2_0R [8:5]
7:3
PLL2_0R[4:0]
2:0
PLL2_0Q [5:3]
7:5
PLL2_0Q [2:0]
4:2
PLL2_0P [2:0]
010b
1:0
VCO2_0_RANGE
00b
7:0
PLL2_1N [11:4]
7:4
PLL2_1N [3:0]
3:0
PLL2_1R [8:5]
7:3
PLL2_1R[4:0]
2:0
PLL2_1Q [5:3]
7:5
PLL2_1Q [2:0]
4:2
PLL2_1P [2:0]
010b
1:0
VCO2_1_RANGE
00b
004h
DESCRIPTION
PLL2_0: 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information, see PLL Multiplier or Divider Definition).
000h
10h
2Bh
fVCO2_0 range selection:
2Ch
2Dh
2Eh
004h
00 –
01 –
10 –
11 –
fVCO2_0 < 125 MHz
125 MHz ≤ fVCO2_0 < 150 MHz
150 MHz ≤ fVCO2_0 < 175 MHz
fVCO2_0 ≥ 175 MHz
PLL2_1: 30-Bit Multiplier/Divider value for frequency fVCO2_1
(for more information, see PLL Multiplier or Divider Definition).
000h
10h
2Fh
fVCO2_1 range selection:
00 –
01 –
10 –
11 –
fVCO2_1 < 125 MHz
125 MHz ≤ fVCO2_1 < 150 MHz
150 MHz ≤ fVCO2_1 < 175 MHz
fVCO2_1 ≥ 175 MHz
Table 12. PLL3 Configuration Register
OFFSET
30h
31h
32h
33h
(1)
(2)
(3)
(4)
22
(1)
ACRONYM
DEFAULT (3)
7:5
SSC3_7 [2:0]
000b
4:2
SSC3_6 [2:0]
000b
1:0
SSC3_5 [2:1]
7
SSC3_5 [0]
6:4
SSC3_4 [2:0]
000b
3:1
SSC3_3 [2:0]
000b
0
SSC3_2 [2]
7:6
SSC3_2 [1:0]
5:3
SSC3_1 [2:0]
000b
2:0
SSC3_0 [2:0]
000b
7
FS3_7
0b
6
FS3_6
0b
5
FS3_5
0b
4
FS3_4
0b
3
FS3_3
0b
2
FS3_2
0b
1
FS3_1
0b
0
FS3_0
0b
BIT
(2)
000b
000b
DESCRIPTION
SSC3: PLL3 SSC Selection (Modulation Amount) (4)
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS3_x: PLL3 Frequency Selection (4)
0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value)
1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value)
Writing data beyond 40h may affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
These are the bits of the Control Terminal Register. The user can pre-define up to eight different control settings. At normal device
operation, these setting can be selected by the external control pins, S0, S1, and S2.
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SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
Table 12. PLL3 Configuration Register (continued)
OFFSET
34h
35h
36h
37h
38h
39h
3Ah
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
DESCRIPTION
7
MUX3
1b
PLL3 Multiplexer:
0 – PLL3
1 – PLL3 Bypass (PLL3 is in power down)
6
M6
1b
Output Y6 Multiplexer:
0 – Pdiv4
1 – Pdiv6
5:4
M7
10b
Output Y7 Multiplexer:
00 –
01 –
10 –
11 –
3:2
Y6Y7_ST1
11b
00 – Y6/Y7 disabled to 3-State and PLL3 power down
01 – Y6/Y7 disabled to 3-State
10 –Y6/Y7 disabled to low
11 – Y6/Y7 enabled
1:0
Y6Y7_ST0
01b
Y6, Y7State0/1definition:
7
Y6Y7_7
0b
Y6Y7_x Output State Selection (4)
6
Y6Y7_6
0b
5
Y6Y7_5
0b
4
Y6Y7_4
0b
3
Y6Y7_3
0b
2
Y6Y7_2
0b
1
Y6Y7_1
1b
0
Y6Y7_0
0b
7
SSC3DC
0b
PLL3 SSC down/center selection:
0 – down
6:0
Pdiv6
01h
7-Bit Y6-Output-Divider Pdiv6:
0 – reset and stand-by
7
—
0b
Reserved – do not write others than 0
6:0
Pdiv7
01h
7-Bit Y7-Output-Divider Pdiv7:
7:0
PLL3_0N [11:4]
7:4
PLL3_0N [3:0]
004h
PLL3_0: 30-Bit Multiplier/Divider value for frequency fVCO3_0
(for more information, see PLL Multiplier or Divider Definition).
3:0
PLL3_0R [8:5]
7:3
PLL3_0R[4:0]
2:0
PLL3_0Q [5:3]
7:5
PLL3_0Q [2:0]
4:2
PLL3_0P [2:0]
010b
1:0
VCO3_0_RANGE
00b
7:0
PLL3_1N [11:4]
7:4
PLL3_1N [3:0]
3Dh
3:0
PLL3_1R [8:5]
7:3
3Eh
PLL3_1R[4:0]
2:0
PLL3_1Q [5:3]
7:5
PLL3_1Q [2:0]
4:2
PLL3_1P [2:0]
010b
1:0
VCO3_1_RANGE
00b
0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
1 – center
0 – reset and stand-by
1-to-127 – divider value
1-to-127 – divider value
000h
10h
3Bh
3Ch
Pdiv4-Divider
Pdiv6-Divider
Pdiv7-Divider
reserved
fVCO3_0 range selection:
004h
00 –
01 –
10 –
11 –
fVCO3_0 < 125 MHz
125 MHz ≤ fVCO3_0 < 150 MHz
150 MHz ≤ fVCO3_0 < 175 MHz
fVCO3_0 ≥ 175 MHz
PLL3_1: 30-Bit Multiplier/Divider value for frequency fVCO3_1
(for more information, see PLL Multiplier or Divider Definition).
000h
10h
3Fh
fVCO3_1 range selection:
00 –
01 –
10 –
11 –
fVCO3_1 < 125 MHz
125 MHz ≤ fVCO3_1 < 150 MHz
150 MHz ≤ fVCO3_1 < 175 MHz
fVCO3_1 ≥ 175 MHz
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The CDCE937-Q1 device is an easy-to-use, high-performance, programmable CMOS clock synthesizer which
can be used as a crystal buffer, clock synthesizer with separate output supply pin. The CDCE937-Q1 device
features an on-chip loop filter and spread-spectrum modulation. Programming can be done through the I2C
interface, or previously saved settings can be loaded from on-chip EEPROM. The pins S0, S1, and S2 can be
programmed as control pins to select various output settings. This section shows some examples of using the
CDCE937-Q1 device in various applications.
11.2 Typical Application
Figure 14 shows the use of the CDCE937-Q1 device in an infotainment system, such as in head unit or
telematics applications, using a 1.8-V single supply. Note that bypass capacitors are not shown in this schematic.
27MHz
Crystal
Control Pin
1.8V
PWM Signal
3.3V
XOUT
20
S0
S1/SDA
19
3
VDD
4
VCTRL
S2/SCL 18
Y1 17
1
Xin/CLK
2
5
GND
6
VDDOUT
CLK output
7
CLK output
8
9
3.3V
10
CDCE937-Q1
Y4
Y5
GND
VDDOUT
I2C or Control Pin
CLK output
16
GND
15
Y2
Y3
I2C or Control Pin
CLK output
14
VDDOUT
Y6
Y7
13
12
11
CLK output
3.3V
CLK output
CLK output
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Figure 14. Single-Chip Solution Using a CDCE937-Q1 Device for Generating Clocking Frequencies
24
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Typical Application (continued)
11.2.1 Design Requirements
The CDCE937-Q1 device supports spread-spectrum clocking (SSC) with multiple control parameters:
• Modulation amount (%)
• Modulation frequency (>20 kHz)
• Modulation shape (triangular, hershey, and others)
• Center spread or down spread (± or –)
For sample calculations of PLL constants, see PLL Multiplier or Divider Definition.
Figure 15. Modulation Frequency (fm) and Modulation Amount
11.2.2 Detailed Design Procedure
11.2.2.1 Spread-Spectrum Clock (SSC)
Spread-spectrum modulation is a method to spread emitted energy over a larger bandwidth. In clocking, spread
spectrum can reduce electromagnetic interference (EMI) by reducing the level of emission from clock distribution
network.
CDCS502 with a 25-MHz Crystal, FS = 1, fOUT = 100 MHz, and 0%, ±0.5, ±1%, and ±2% SSC
Figure 16. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock
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Typical Application (continued)
Spread spectrum clocking can be used to help reduce EMI to meet design specifications. For example, a
specified EMI threshold of 55 dB/mV would require ±1% spread spectrum clocking to meet this requirement.
11.2.2.2 PLL Multiplier or Divider Definition
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCEx937-Q1 can be calculated with
Equation 1.
f IN N
f OUT =
x
Pdiv M
where
•
•
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL
Pdiv (1 to 127) is the output divider
The target VCO frequency (ƒVCO) of each PLL can be calculated with Equation 2.
N
f VCO = f IN ´
M
(1)
(2)
The PLL internally operates as fractional divider and requires the following multiplier and divider settings:
N
Nö
æ
ç log 2 M ÷ [if P < 0 then P = 0]
ø
P = 4 – int è
æ N' ö
ç ÷
Q = int è M ø
R = N′ – M × Q
where
N′ = N × 2P
N≥M
100 MHz < ƒVCO > 200 MHz
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2;
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2;
→ fOUT = 54 MHz
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ P = 4 – int(log25.5) = 4 – 2 = 2
2
→ N′ = 4 × 2 = 16
→ N′ = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ is automatically calculated when using TI Pro-Clock™ software.
11.2.2.3 Crystal Oscillator Start-Up
When the CDCE937-Q1 or CDCEL937-Q1 device is used as a crystal buffer, crystal oscillator start-up dominates
the start-up time compared to the internal PLL lock time. The following diagram shows the oscillator start-up
sequence for a 27-MHz crystal input with an 8-pF load. The start-up time for the crystal is on the order of
approximately 250 µs compared to approximately 10 µs of lock time. In general, lock time is an order of
magnitude less compared to the crystal start-up time.
26
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SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
Typical Application (continued)
Figure 17. Crystal Oscillator Start-Up vs PLL Lock Time
11.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
The frequency for the CDCE937-Q1 or CDCEL937-Q1 device is adjusted for media and other applications with
the VCXO control input Vctr. If a PWM-modulated signal is used as a control signal for the VCXO, an external
filter is required.
LP
PWM
Control
Signal
Vctr
CDCE(L)937-Q1
Xin/CLK
Xout
Figure 18. Frequency Adjustment Using PWM Input to the VCXO Control
11.2.2.5 Unused Inputs and Outputs
If VCXO-pulling functionality is not required, Vctr must be left floating. All other unused inputs must be set to
GND. Unused outputs must be left floating.
If one output block is not used, TI recommends disabling it. However, TI recommends providing a supply for all
output blocks, even if they are disabled.
11.2.2.6 Switching Between XO and VCXO Mode
When the CDCEx937-Q1 device is in the crystal-oscillator or VCXO configuration, the internal capacitors require
different internal capacitance. The following steps are recommended to switch to VCXO mode when the
configuration for the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:
1. While in XO mode, put Vctr = VDD / 2
2. Switch from XO mode to VCXO mode
3. Program the internal capacitors to obtain 0 ppm at the output.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: CDCE937-Q1 CDCEL937-Q1
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CDCE937-Q1, CDCEL937-Q1
SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
www.ti.com
Typical Application (continued)
11.2.3 Application Curves
Figure 19, Figure 20, Figure 21, and Figure 22 show CDCE937-Q1 measurements with the SSC feature enabled.
Device configuration: 27-MHz input, 27-MHz output.
Figure 19. fOUT = 27 MHz,
VCO frequency < 125 MHz, SSC (2% Center)
Figure 20. fOUT = 27 MHz,
VCO frequency > 175 MHz, SSC (1%, Center)
Figure 21. Output Spectrum With SSC Off
Figure 22. Output Spectrum With SSC On,
2% Center
12 Power Supply Recommendations
There is no restriction on the power-up sequence. In case VDDOUT is applied first, TI recommends grounding VDD.
In case VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT pins.
The device has a power-up control that is connected to the 1.8-V supply. This keeps the whole device disabled
until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal components,
including the outputs. If a 3.3-V VDDOUT is available before the 1.8-V, the outputs stay disabled until the 1.8-V
supply has reached a certain level.
28
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Product Folder Links: CDCE937-Q1 CDCEL937-Q1
CDCE937-Q1, CDCEL937-Q1
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SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
13 Layout
13.1 Layout Guidelines
When the CDCEx937-Q1 device is used as a crystal buffer, any parasitics across the crystal affect the pulling
range of the VCXO. Therefore, take care in placing the crystal units on the board. Crystals must be placed as
close to the device as possible, ensuring that the routing lines from the crystal terminals to Xin and Xout have the
same length.
If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the
device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise
coupling.
Additional discrete capacitors can be required to meet the load capacitance specification of certain crystals. For
example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can
range from 0 pF to 20 pF with steps of 1 pF. Therefore, the 0.7-pF capacitor can be discretely added on top of
an internal 10 pF.
To minimize the inductive influence of the trace, TI recommends placing this small capacitor as close to the
device as possible and symmetrically with respect to Xin and Xout.
Figure 23 shows a conceptual layout detailing recommended placement of power-supply bypass capacitors. For
component-side mounting, use 0402 body-size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
13.2 Layout Example
Place the crystal with
associated load caps as
close to the chip as
possible
To VIO
To 1.8V
Use ferrite beads to
isolate the device supply
pins from board noise
sources
Xin/CLK
XOUT
S0
S1/SDA
VDD
S2/SCL
VCTRL
Y1
GND
GND
VDDOUT
Y4 Output
Y4
Y5 Output
Y5
CDCE937-Q1
SDA
SCL
Y1 Output
Y2
Y2 Output
Y3
Y3 Output
VDDOUT
GND
Y6
Y6 Output
VDDOUT
Y7
Y7 Output
To 3.3V
Legend
Place bypass caps close to
the device pins, ensure
wide frequency range
Place series termination
resistors at clock outputs
to improve signal integrity
Via
Copper trace/pour
Copyright © 2016, Texas Instruments Incorporated
Figure 23. CDCE937-Q1 Layout Example
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: CDCE937-Q1 CDCEL937-Q1
Submit Documentation Feedback
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CDCE937-Q1, CDCEL937-Q1
SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
www.ti.com
14 Device and Documentation Support
14.1 Documentation Support
14.1.1 Related Documentation
For related documentation see the following:
• CDCE(L)9xx and CDCEx06 Programming Evaluation Module (SCAU026)
• VCXO Application Guideline for CDCE(L)9xx Family (SCAA085)
• General I2C/EEPROM Usage for the CDCE(L)9xx Family (SCAA104)
• Crystal Or Crystal Oscillator Replacement with Silicon Devices (SNAA217)
• Troubleshooting I2C Bus Protocol (SCAA106)
• Usage of I2C™ for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 (SCAA105)
• Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency Word Clock (SCAA088)
14.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 13. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
CDCE937-Q1
Click here
Click here
Click here
Click here
Click here
CDCEL937-Q1
Click here
Click here
Click here
Click here
Click here
14.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
14.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
14.5 Trademarks
DaVinci, OMAP, Pro-Clock, E2E are trademarks of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG.
Ethernet is a trademark of Xerox Corporattion.
All other trademarks are the property of their respective owners.
14.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
30
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: CDCE937-Q1 CDCEL937-Q1
CDCE937-Q1, CDCEL937-Q1
www.ti.com
SCAS892C – FEBRUARY 2010 – REVISED DECEMBER 2016
14.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: CDCE937-Q1 CDCEL937-Q1
Submit Documentation Feedback
31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCE937QPWRQ1
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CDCE937Q
CDCEL937QPWRQ1
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CEL937Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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