CDCLVD1216
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SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011
2:16 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD1216
FEATURES
1
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2:16 Differential Buffer
Low Additive Jitter: 3000
V
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
The outputs can handle permanent short.
RECOMMENDED OPERATING CONDITIONS
Device supply voltage, VCC
Ambient temperature, TA
MIN
TYP
MAX
2.375
2.5
2.625
V
85
°C
–40
UNIT
THERMAL INFORMATION
CDCLVD1216
THERMAL METRIC (1)
RGZ(48 PINS)
θJA
Junction-to-ambient thermal resistance
30.6
θJC(top)
Junction-to-case(top) thermal resistance
28.5
θJB
Junction-to-board thermal resistance
10.5
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
10.2
θJC(bottom)
Junction-to-case(bottom) thermal resistance
3.1
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
At VCC = 2.375V to 2.625V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IN_SEL CONTROL INPUT CHARACTERISTICS
VdI3
3 State
VdIH
Input high voltage
Open
VdIL
Input low voltage
IdIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
IdIL
Input low current
VCC = 2.625 V, VIL= 0V
Rpull(IN_SEL)
Input pull-up/ pull-down resistor
0.5×VCC
V
0.7×VCC
V
0.2×VCC
V
30
μA
–30
μA
200
kΩ
2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS
fIN
Input frequency
External threshold voltage applied to
complementary input
200
MHz
1.5
V
Vth + 0.1
VCC
V
0
Vth – 0.1
V
10
μA
Vth
Input threshold voltage
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
IIL
Input low current
VCC = 2.625 V, VIL = 0 V
ΔV/ΔT
Input edge rate
20%–80%
CIN
Input capacitance
2.5
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1.1
–10
1.5
μA
V/ns
pF
CDCLVD1216
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SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS (continued)
At VCC = 2.375V to 2.625V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIFFERENTIAL INPUT CHARACTERISTICS
fIN
Input frequency
Clock input
800
MHz
VIN,
Differential input voltage peak-to-peak
VICM = 1.25 V
0.3
1.6
VPP
VICM
Input common mode voltage range
VIN, DIFF, PP > 0.4 V
1.0
VCC – 0.3
V
IIH
Input high current
VCC = 2.625 V, VIH = 2.625 V
10
μA
IIL
Input low current
VCC = 2.625, VIL = 0 V
ΔV/ΔT
Input edge rate
20%–80%
CIN
Input capacitance
DIFF
–10
0.75
μA
V/ns
2.5
pF
LVDS OUTPUT CHARACTERISTICS
|VOD|
Differential output voltage magnitude
ΔVOD
Change in differential output voltage
magnitude
VOC(SS)
Steady-state common mode output
voltage
ΔVOC(SS)
Steady-state common mode output
voltage
VIN, DIFF, PP = 0.6V, RL = 100 Ω
Vring
Output overshoot and undershoot
Percentage of output amplitude VOD
VOS
Output ac common mode
VIN, DIFF, PP = 0.6V, RL = 100 Ω
IOS
Short-circuit output current
VOD = 0 V
tPD
Propagation delay
VIN, DIFF, PP = 0.3 V
tSK, PP
Part-to-part skew
tSK, O
Output skew
VIN, DIFF, PP = 0.3V, RL = 100 Ω
tSK,P
Pulse skew(with 50% duty cycle input)
Crossing-point-to-crossing-point
distortion
tRJIT
Random additive jitter (with 50% duty
cycle input)
Edge speed 0.75 V/ns,
10 kHz – 20 MHz
tR/tF
Output rise/fall time
20% to 80%, 100 Ω, 5 pF
ICCSTAT
Static supply current
Outputs unterminated, f = 0 Hz
ICC100
Supply current
ICC800
Supply current
250
450
mV
–15
15
mV
1.1
1.375
–15
15
V
mV
10%
40
1.5
–50
50
70
mVPP
±24
mA
2.5
ns
600
ps
55
ps
50
ps
0.3
ps,
RMS
300
ps
17
28
mA
All outputs, RL = 100 Ω, f = 100 MHz
107
140
mA
All outputs, RL = 100 Ω, f = 800 MHz
147
180
mA
1.25
1.35
V
VAC_REF CHARACTERISTICS
VAC_REF
Reference output voltage
VCC = 2.5 V Iload = 100 µA
1.1
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Typical Additive Phase Noise Characteristics for 100 MHz Clock
PARAMETER
MIN
TYP
MAX
UNIT
phn100
Phase noise at 100 Hz offset
-132.9
dBc/Hz
phn1k
Phase noise at 1 kHz offset
-138.8
dBc/Hz
phn10k
Phase noise at 10 kHz offset
-147.4
dBc/Hz
phn100k
Phase noise at 100 kHz offset
-153.6
dBc/Hz
phn1M
Phase noise at 1 MHz offset
-155.2
dBc/Hz
phn10M
Phase noise at 10 MHz offset
-156.2
dBc/Hz
phn20M
Phase noise at 20 MHz offset
-156.6
dBc/Hz
tRJIT
Random additive jitter from 10 kHz to 20 MHz
171
fs, RMS
Typical Additive Phase Noise Characteristics for 737.27 MHz Clock
PARAMETER
phn100
Phase noise at 100 Hz offset
phn1k
Phase noise at 1 kHz offset
phn10k
Phase noise at 10 kHz offset
phn100k
MIN
TYP
MAX
UNIT
-80.2
dBc/Hz
-114.3
dBc/Hz
-138
dBc/Hz
Phase noise at 100 kHz offset
-143.9
dBc/Hz
phn1M
Phase noise at 1 MHz offset
-145.2
dBc/Hz
phn10M
Phase noise at 10 MHz offset
-146.5
dBc/Hz
phn20M
Phase noise at 20 MHz offset
-146.6
dBc/Hz
tRJIT
Random additive jitter from 10 kHz to 20 MHz
65
fs, RMS
6
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SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS
Phase Noise - dBc/Hz
INPUT- AND OUTPUT-CLOCK PHASE NOISES
vs
FREQUENCY FROM the CARRIER
(TA = 25°C and VCC = 2.5V)
Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs
Figure 3. 100 MHz Input and Output Phase Noise Plot
spacer
VOD − Differential Output Voltage − mV
350
TA = 25oC
340
2.625V
330
320
2.5V
310
300
2.375V
290
280
270
260
250
0
100
200
300
400
500
600
700
800
Frequency − MHz
Figure 4. Differential Output Voltage vs Frequency
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SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011
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TYPICAL CHARACTERISTICS (continued)
TEST CONFIGURATIONS
Oscilloscope
100 W
LVDS
Figure 5. LVDS Output DC Configuration During Device Test
Phase Noise
Analyzer
LVDS
50 W
Figure 6. LVDS Output AC Configuration During Device Test
VIH
Vth
IN
VIL
IN
Vth
Figure 7. DC Coupled LVCMOS Input During Device Test
VOH
OUTNx
VOD
OUTPx
VOL
80%
VOUT,DIFF,PP (= 2 x VOD)
20%
0V
tr
tf
Figure 8. Output Voltage and Rise/Fall Time
8
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SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS (continued)
INNx
INPx
tPLH0
tPHL0
tPLH1
tPHL1
OUTN0
OUTP0
OUTN1
OUTP1
tPLH2
tPHL2
OUTN2
OUTP2
OUTN15
tPHL15
tPLH15
OUTP15
A.
Output skew is calculated as the greater of the following: As of the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..15)
B.
Part to part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..15)
Figure 9. Output Skew and Part-to-Part Skew
Vring
OUTNx
VOD
0 V Differential
OUTPx
Figure 10. Output Overshoot and Undershoot
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SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011
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TYPICAL CHARACTERISTICS (continued)
VOS
GND
Figure 11. Output AC Common Mode
APPLICATION INFORMATION
THERMAL MANAGEMENT
For reliability and performance reasons, the die temperature should be limited to a maximum of +125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be
soldered down to ensure adequate heat conduction to of the package. Check the mechanical data at the end of
the data sheet for land and via pattern examples.
POWER SUPPLY FILTERING
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is critical to the application.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they
must be placed close to the power-supply pins and laid out with short loops to minimize inductance. It is
recommended to add as many high-frequency (for example, 0.1 μF) bypass capacitors as there are supply pins
in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and
the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip
supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for
proper operation.
Board
Supply
Chip
Supply
Ferrite Bead
1 µF
10µF
0.1 µF (x6)
Figure 12. Power Supply Filtering
10
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SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011
LVDS OUTPUT TERMINATION
The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the
receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is
recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage
different than the output common mode voltage of the CDCLVD1216, ac-coupling should be used. If the LVDS
receiver has internal 100 Ω termination, external termination must be omitted.
Unused outputs can be left open without connecting any trace to the output pins.
Z = 50 W
100 W
CDCLVD1216
LVDS
Z = 50 W
Figure 13. LVDS Output DC Termination
100 nF
Z = 50 W
100 W
CDCLVD1216
LVDS
Z = 50 W
100 nF
Figure 14. LVDS Output AC Termination with Receiver Internally Biased
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CDCLVD1216
SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011
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INPUT TERMINATION
The CDCLVD1216 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.
LVDS Driver can be connected to CDCLVD1216 inputs with dc or ac coupling as shown Figure 15 and Figure 16
respectively.
Z = 50 W
100 W
LVDS
CDCLVD1216
Z = 50 W
Figure 15. LVDS Clock Driver Connected to CDCLVD1216 Input (DC coupled)
100 nF
Z = 50 W
LVDS
CDCLVD1216
Z = 50 W
100 nF
50 W
50 W
VAC_REF
Figure 16. LVDS Clock Driver Connected to CDCLVD1216 Input (AC coupled)
Figure 17 shows how to connect LVPECL inputs to the CDCLVD1216. The series resistors are required to
reduce the LVPECL signal swing if the signal swing is >1.6 VPP.
75 W
100 nF
Z = 50 W
CDCLVD1216
LVPECL
Z = 50 W
75 W
150 W
150 W
100 nF
50 W
50 W
VAC_REF
Figure 17. LVPECL Clock Driver Connected to CDCLVD1216 Input
12
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SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011
Figure 18 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD1216 directly. The series
resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs
to be limited to VIH ≤ VCC.
RS
LVCMOS
(2.5V)
Z = 50 W
CDCLVD1216
V
V
Vth = IH + IL
2
Figure 18. 2.5V LVCMOS Clock Driver Connected to CDCLVD1216 Input
For unused inputs, it is recommended to ground both input pins (INP, INN) using 1 kΩ resistors.
Spacer
REVISION HISTORY
Changes from Original (October 2010) to Revision A
Page
•
Changed Feature - Low Output Skew of 45 ps (Max) To: Low Output Skew of 55 ps (Max) .............................................. 1
•
Changed tSK, O Output Skew From: 45 ps (Max) To: 55 ps (Max) ........................................................................................ 5
•
Deleted the Recommended PCB Layout illustration .......................................................................................................... 10
Changes from Revision A (November 2010) to Revision B
•
Page
Changed the device status From: Product Preview To: Production ..................................................................................... 1
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCLVD1216RGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CDCLVD
1216
CDCLVD1216RGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CDCLVD
1216
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of