CDCLVP2106RHAR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CDCLVP2106 SCAS887B – SEPTEMBER 2009 – REVISED JANUARY 2016 CDCLVP2106 12-LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description • • • The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications. 1 • • • • • • • • • • • • Dual 1:6 Differential Buffer Two Clock Inputs Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL 12 LVPECL Outputs Maximum Clock Frequency: 2 GHz Maximum Core Current Consumption: 92 mA Very Low Additive Jitter: