CDCVF2509PW

NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 www.ti.com SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 3.3-V PHASE-LOCK LOOP CLOCK DRIVER Check for Samples: CDCVF2509 FEATURES 1 • • • • • • • • • • • • Use CDCVF2509A (SCAS765) as a Replacement for This Device Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible Operating Frequency 50 MHz to 175 MHz Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps Jitter (cyc - cyc) at 66 MHz to 166 MHz Is Typ = 70 ps Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input • • • 25-Ω On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V APPLICATIONS • • • DRAM Applications PLL Based Clock Distributors Non-PLL Clock Buffer PW PACKAGE (TOP VIEW) AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC 1G FBOUT 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CLK AVCC VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 2G FBIN DESCRIPTION The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2010, Texas Instruments Incorporated NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED Because it is based on PLL circuitry, the CDCVF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground. The CDCVF2509A is characterized for operation from 0°C to 85°C. For application information, see application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (SCAA039). FUNCTION TABLE INPUTS OUTPUTS 1G 2G CLK 1Y (0:4) 2Y (0:3) X X L L L FBOUT L L L H L L H L H H L H H H L H H L H H H H H H H FUNCTIONAL BLOCK DIAGRAM 1G 11 3 4 5 8 9 2G CLK AVCC 2 1Y1 1Y2 1Y3 1Y4 14 24 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ PLL FBIN 1Y0 13 21 20 17 16 12 2Y0 2Y1 2Y2 2Y3 FBOUT 23 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 www.ti.com SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (PW) 0°C to 85°C CDCVF2509PWR CDCVF2509PW PACKAGE THERMAL RESISTANCE (1) CDCVF2509APW 24-PIN TSSOP RqJA High K RqJC High K (1) THERMAL AIRFLOW (CFM) 0 150 250 500 88 83 81 77 26.5 UNIT °C/W The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). Pin Functions PIN NAME NO. TYPE DESCRIPTION CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CDCVF2509A clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. 1G 11 I Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same frequency as CLK. 2G 14 I Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25-Ω series-damping resistor. 1Y (0:4) 3, 4, 5, 8, 9 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each output has an integrated 25-Ω series-damping resistor. 2Y (0:3) 16, 17, 21, 20 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each output has an integrated 25-Ω series-damping resistor. AVCC 23 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC 2, 10, 15, 22 Power GND 6, 7, 18, 19 Ground Ground Power supply Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 3 NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT AVCC Supply voltage range VCC Supply voltage range VI Input voltage range (2) AVCC < VCC +0.7 V –0.5 V to 4.3 V (3) –0.5 V to 4.6 V (3) (4) VO Voltage range applied to any output in the high or low state IIK Input clamp current (VI< 0) –0.5 V to VCC + 0.5 V –50 mA IOK Output clamp current (VO< 0 or VO > VCC) ±50 mA IO Continuous output current (VO = 0 to VCC) ±50 mA Continuous current through each VCC or GND ±100 mA Maximum power dissipation at TA = 55°C (in still air) (5) Tstg (1) (2) (3) (4) (5) 0.7 W Storage temperature range –65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. AVCC must not exceed VCC+ 0.7 V The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 4.6 V maximum. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, see the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book (SCBD002). DISSIPATION RATINGS TA ≤ 25°C POWER RATING PACKAGE BOARD TYPE RqJA PW JEDEC low-K 114.5°C/W JEDEC high-K 62.1°C/W DERATING FACTORS ABOVE TA ≤ 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING 920 mW 8.7 mW/°C 520 mW 390 mW 1690 mW 16.1 mW/°C 960 mW 720 mW RECOMMENDED OPERATING CONDITIONS (1) MIN MAX VCC, AVCC Supply voltage 3 3.6 VIH High-level input voltage 2 VIL Low-level input voltage VI Input voltage IOH IOL TA Operating free-air temperature (1) UNIT V V 0.8 V VCC V High-level output current –12 mA Low-level output current 12 mA 85 °C 0 0 Unused inputs must be held high or low to prevent them from floating. TIMING REQUIREMENTS over recommended ranges of supply voltage and operating free-air temperature fclk Clock frequency Input clock duty cycle Stabilization time (1) (1) 4 MIN MAX UNIT 50 175 MHz 40% 60% 1 ms The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 www.ti.com SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS Input clamp voltage VOH II = -18 mA High-level output voltage VOL Low-level output voltage IOH High-level output current MIN TYP (1) VCC, AVCC 3V MAX UNIT –1.2 V IOH = -100 µA MIN to MAX IOH = -12 mA 3V 2.1 IOH = -6 mA 3V 2.4 IOL = 100 µA MIN to MAX 0.2 IOL = 12 mA 3V 0.8 IOL = 6 mA 3V VO= 1 V 3V VO = 1.65 V 3.3 V VO = 3.135 V 3.6 V VCC–0.2 V V 0.55 –28 –36 mA -8 VO= 1.95 V 3V VO = 1.65 V 3.3 V VO = 0.4 V 3.6 V 10 Input current VI = VCC or GND 3.6 V ±5 µA Supply current (static, output not switching) VI = VCC or GND, IO = 0, Outputs: low or high 3.6 V, 0 V 40 µA ΔICC Change in supply current One input at VCC - 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V 500 µA Ci Input capacitance VI = VCC or GND 3.3 V 2.5 pF Co Output capacitance VO = VCC or GND 3.3 V 2.8 pF IOL Low-level output current II ICC (1) (2) (2) 30 40 mA For conditions shown as MIN or MAX, use the appropriate value specified under the recommended operating conditions section. For dynamic ICC vs Frequency, see Figure 8 and Figure 9. SWITCHING CHARACTERISTICS over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Figure 1 and Figure 2) (1) FROM (INPUT) PARAMETER t(f) Phase error time- static (normalized) (see Figure 3 through Figure 6) CLK↑ = 66 MHz to 166 MHz tsk(o) Output skew time (3) Any Y Phase error time-jitter (4) CLK = 66 MHz to 100 MHz CLK = 66 MHz to 100 MHz Jitter(cycle-cycle) (see Figure 7) CLK = 100 MHz to 166 MHz TO (OUTPUT) FBIN↑ VCC, AVCC = 3.3 V ± 0.3 V UNIT MIN TYP MAX –125 125 ps 100 ps 50 ps Any Y Any Y or FBOUT (2) –50 -70 Any Y or FBOUT ps -65 Duty cycle f(CLK) > 60 MHz Any Y or FBOUT 45% 55% tr Rise time VO = 0.4 V to 2 V Any Y or FBOUT 0.3 1.1 ns/V tf Fall time VO = 2 V to 0.4 V Any Y or FBOUT 0.3 1.1 ns/V tPLH Low-to-high propagation delay time, bypass mode CLK Any Y or FBOUT 1.8 3.9 ns tPHL High-to-low propagation delay time, bypass mode CLK Any Y or FBOUT 1.8 3.9 ns (1) (2) (3) (4) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. These parameters are not production tested. The tsk(o) specification is only valid for equal loading of all outputs. Calculated per PC DRAM SPEC (tphase error, static-jitter(cycle-to-cycle)). Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 5 NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION 3V Input 50% VCC 0V tpd From Output Under Test 500 W 2V 0.4 V Output 25 pF 50% VCC tr LOAD CIRCUIT FOR OUTPUTS VOH 2V 0.4 V VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms CLKIN FBIN tphase error FBOUT Any Y tsk(o) Any Y Any Y tsk(o) Figure 2. Skew Calculations 6 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 www.ti.com SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS STATIC PHASE ERROR vs LOAD CAPACITANCE 600 600 VCC = 3.3 V fc = 100 MHz C(LY1−n) = 25 pF || 500 Ω TA = 25°C See Notes A, B, and C 200 VCC = 3.3 V fc = 133 MHz C(LY1−n) = 25 pF || 500 Ω TA = 25°C See Notes A, B, and C 400 Static Phase Error − ps 400 Static Phase Error − ps STATIC PHASE ERROR vs LOAD CAPACITANCE CLK to Y1−n 0 −200 200 CLK to Y1−n 0 −200 CLK to FBOUT CLK to FBOUT −400 −400 −600 −600 3 8 13 18 23 28 33 38 3 8 13 C(LF) − Load Capacitance − pF 23 28 33 38 175 200 C(LF) − Load Capacitance − pF Figure 3. Figure 4. STATIC PHASE ERROR vs SUPPLY VOLTAGE AT FBOUT STATIC PHASE ERROR vs CLOCK FREQUENCY 0 0 fc = 133 MHz C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes A, B, and C −100 −150 CLK to FBOUT −200 −250 −100 −150 −250 −300 −350 −350 −400 −400 3.1 3.2 3.3 3.4 3.5 3.6 CLK to FBOUT −200 −300 3 VCC = 3.3 V C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes A, B, and C −50 Static Phase Error − ps −50 Static Phase Error − ps 18 50 VCC − Supply Voltage at FBOUT − V Figure 5. 75 100 125 150 fc − Clock Frequency − MHz Figure 6. a. Trace length FBOUT to FBIN = 5 mm, ZO = 50Ω b. C(LY) = Lumped capacitive load Y1-n c. C(LFx) = Lumped feedback capacitance at FBOUT = FBIN Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 7 NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 www.ti.com JITTER vs CLOCK FREQUENCY AT FBOUT ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY 140 AI CC − Analog Supply Current − mA 120 25 VCC = 3.3 V C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes C and D Jitter − ps 100 80 60 Cycle to Cycle 40 20 0 50 75 100 125 150 175 AVCC = VCC = 3.6 V Bias = 0/3 V C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes A and B 20 15 10 5 0 200 0 25 fc − Clock Frequency at FBOUT − MHz 50 75 100 125 150 175 200 fc − Clock Frequency − MHz Figure 7. Figure 8. SUPPLY CURRENT vs CLOCK FREQUENCY 250 AVCC = VCC = 3.6 V Bias = 0/3 V C(LY) = 25 pF || 500 Ω C(LF) = 12 pF || 500 Ω TA = 25°C See Notes A and B I CC − Supply Current − mA 200 150 100 50 0 0 25 50 75 100 125 150 175 200 fc − Clock Frequency − MHz Figure 9. a. b. c. d. 8 Trace length FBOUT to FBIN = 5 mm, ZO = 50 Ω C(LY) = Lumped capacitive load Y1-n C(LFx) = Lumped feedback capacitance at FBOUT = FBIN C(LFx) = Lumped feedback capacitance at FBOUT = FBIN. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 www.ti.com SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 REVISION HISTORY Changes from Original (April 2004) to Revision A • Page Added CDCVF2509PW package number to the AVAILABLE OPTIONS table .................................................................... 3 Changes from Revision A (July 2004) to Revision B Page • Changed Rise time values in the Switching Characteristics table From: Min =0.5 Max = 2.5 To: Min = 0.3 Max = 1.1 ..... 5 • Changed Fall time values in the Switching Characteristics table From: Min =0.5 Max = 2.5 To: Min = 0.3 Max = 1.1 ....... 5 • Changed Low-to-high propagation delay time values in the Switching Characteristics table From: Min =0.4 Max = 2.3 To: Min = 1.8 Max = 3.9 ................................................................................................................................................. 5 • Changed High-to-low propagation delay time values in the Switching Characteristics table From: Min =0.4 Max = 2.3 To: Min = 1.8 Max = 3.9 ........................................................................................................................................................ 5 Changes from Revision B (June 2005) to Revision C • Page Added NOT RECOMMENDED FOR NEW DESIGNS ......................................................................................................... 1 Changes from Revision C (January 2009) to Revision D • Page Added the PACKAGE THERMAL RESISTANCE table ........................................................................................................ 3 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): CDCVF2509 9 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) CDCVF2509PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 85 CKV2509 CDCVF2509PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 85 CKV2509 CDCVF2509PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 85 CKV2509 CDCVF2509PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 85 CKV2509 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDCVF2509PWR Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCVF2509PWR TSSOP PW 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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