CLC006BM/NOPB

CLC006 www.ti.com SNLS015G – AUGUST 1998 – REVISED APRIL 2013 CLC006 Serial Digital Cable Driver with Adjustable Outputs Check for Samples: CLC006 FEATURES DESCRIPTION • • • • • • Texas Instruments' Comlinear CLC006 is a monolithic, high-speed cable driver designed for the SMPTE 259M serial digital video data transmission standard. The CLC006 drives 75Ω transmission lines (Belden 8281 or equivalent) at data rates up to 400 Mbps. Controlled output rise and fall times (650 ps typical) minimize transition-induced jitter. The output voltage swing, typically 1.65V, set by an accurate, low-drift internal bandgap reference, delivers an 800 mV swing to back-matched and terminated 75Ω cable. Output swing is adjustable from 0.7 VP-P to 2 VP-P using external resistors. 1 2 No External Pull-down Resistors Adjustable Output Amplitude Differential Input and Output Low Power Dissipation Single +5V or −5.2V Supply Replaces GS9008 in Most Applications APPLICATIONS • • • • • • Digital Routers and Distribution Amplifiers Coaxial Cable Driver for Digital Transmission Line Twisted Pair Driver Serial Digital Video Interfaces for the Commercial and Broadcast Industry SMPTE, Sonet/SDH, and ATM Compatible Driver Buffer Applications The CLC006’s class AB output stage consumes less power than other designs, 185 mW with both outputs terminated, and requires no external bias resistors. The differential inputs accept a wide range of digital signals from 200 mVP-P to ECL levels within the specified common-mode limits. All this make the CLC006 an excellent general purpose high speed driver for digital applications. The CLC006 is powered from a single +5V or −5.2V supply and comes in an 8-pin SOIC package. KEY SPECIFICATIONS • • • • 650 ps Rise and Fall Times Data Rates to 400 Mbps 200 mV Differential Input Low Residual Jitter (25 pspp) Typical Application VCC REXT 75: 75: 8 4 7 + VIN- 3 1 75: 0.1 PF 75: Coax CLC006 6 VIN+ - V0 V0 2 75: 0.1 PF 75: Coax 75: 75: 5 154: 154: 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2013, Texas Instruments Incorporated CLC006 SNLS015G – AUGUST 1998 – REVISED APRIL 2013 www.ti.com Connection Diagram 270 Mbps Eye Pattern 0 1 2 3 4 5 Q0 1 8 VCC Q0 2 7 VIN+ REXT-H 3 6 VIN- REXT-L 4 5 VEE 6 TIME (1 ns/Div) Figure 2. 8-Pin SOIC See Package Number D Figure 1. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage 6V Output Current 30 mA Maximum Junction Temperature +125°C −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering 10 Seconds) +300°C ESD Rating (Human Body Model) Package Thermal Resistance Reliability Information (1) (2) 1000V θJA 8–pin SOIC +160°C/W θJC 8–pin SOIC +105°C/W MTTF 254 Mhr Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Recommended Operating Conditions Supply Voltage Range (VCC – VEE) 2 +4.5V to +5.5V Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC006 CLC006 www.ti.com SNLS015G – AUGUST 1998 – REVISED APRIL 2013 Electrical Characteristics (VCC = 0V, VEE = −5V; unless otherwise specified). Parameter Condition Typ +25°C Min/Max +25°C (1) Min/Max 0°C to +70°C (1) Min/Max −40°C to +85°C (1) Units 37 — — — mA STATIC DC PERFORMANCE Supply Current, Loaded 150Ω @ 270 Mbps (2) Supply Current, Unloaded (3) 34 28/45 26/47 26/47 mA Output HIGH Voltage (VOH) (3) −1.7 −2.0/1.4 −2.0/1.4 −2.0/1.4 V Output LOW Voltage (VOL) (3) −3.3 −3.6/3.0 −3.6/3.0 −3.6/3.0 V 10 30 50 50 μA 1.65 1.55/1.75 1.53/1.77 1.51/1.79 V 1.30 — — — V Common Mode Input Range Upper Limit −0.7 −0.8 −0.8 −0.8 V Common Mode Input Range Lower Limit −2.6 −2.5 −2.5 –2.5 V Minimum Differential Input Swing 200 200 200 200 mV 26 20 20 20 dB 650 425/825 400/850 400/850 ps Input Bias Current (3) Output Swing REXT = ∞ Output Swing REXT = 10 kΩ Power Supply Rejection Ratio (3) AC PERFORMANCE Output Rise and Fall Time (3) (4) (2) Overshoot 5 % Propagation Delay 1.0 ns Duty Cycle Distortion 50 Residual Jitter 25 ps — — — pspp MISCELLANEOUS PERFORMANCE Input Capacitance 1.0 Output Resistance 10 Ω Output Inductance 6 nH (1) (2) (3) (4) pF Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Measured with both outputs driving 150Ω, AC coupled at 270 Mbps. Spec is 100% tested at +25°C Measured between the 20% and 80% levels of the waveform. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC006 3 CLC006 SNLS015G – AUGUST 1998 – REVISED APRIL 2013 www.ti.com Operation INPUT INTERFACING The CLC006 has high impedance, emitter-follower buffered, differential inputs. Single-ended signals may also be input. Transmission lines supplying input signals must be properly terminated close to the CLC006. Either A.C. or D.C. coupling as in Figure 4 or Figure 5 may be used. Figure 4, Figure 6 and Figure 7 show how Theveninequivalent resistor networks are used to provide input termination and biasing. The input D.C. common-mode voltage range is 0.8V to 2.5V below the positive power supply (VCC). Input signals plus bias should be kept within the specified common-mode range. For an 800 mVP-P input signal, typical input bias levels range from 1.2V to 2.1V below the positive supply. Resistor to VCC (R1) Resistor to VEE (R2) ECL, 50Ω, 5V, VT=2V Load Type 82.5Ω 124Ω ECL, 50Ω, 5.2V, VT=2V 80.6Ω 133Ω ECL, 75Ω, 5V, VT=2V 124Ω 187Ω ECL, 75Ω, 5.2V, VT=2V 121Ω 196Ω 800 mVP-P, 50Ω, 5V, VT=1.6V 75.0Ω 154Ω 800 mVP-P, 75Ω, 5V, VT=1.6V 110Ω 232Ω 800 mVP-P, 2.2KΩ, 5Ω, VT=1.6V 3240Ω 6810Ω VCC VIN+ VIN- To next stage VEE Figure 3. Input Stage VCC VCC ECL Output Z0 R1 R1 0.1 PF 8 4 7 3 + 1 CLC006 6 VTT Z0 2 - 0.1 PF 5 R2 R2 VTT VEE VEE Figure 4. AC Coupled Input 4 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC006 CLC006 www.ti.com SNLS015G – AUGUST 1998 – REVISED APRIL 2013 VCC ECL Output Z0 8 4 7 3 + 1 CLC006 6 Z0 = Z0 = Z0 VTT 2 5 VEE Figure 5. DC Coupled Input VCC R5 75: R4 75: VCC R5 75: U1 8 4 7 J1 3 + 1 R4 75: U1 8 4 7 J1 VIN+ CLC006 R3 154: 6 - R1 154: 5 3 + 1 CLC006 2 J2 VINR3 154: VEE 6 - R1 154: 5 2 VEE Figure 6. Single Ended 50Ω ECL input Figure 7. Differential 50Ω ECL Input OUTPUT INTERFACING The CLC006’s class AB output stage, Figure 8, requires no standing current in the output transistors and therefore requires no biasing or pull-down resistors. Advantages of this arrangement are lower power dissipation and fewer external components. The output may be either D.C. or A.C. coupled to the load. A bandgap voltage reference sets output voltage levels which are compatible with F100K and 10K ECL when correctly terminated. The outputs do not have the same output voltage temperature coefficient as 10K. Therefore, noise margins will be reduced over the full temperature range when driving 10K ECL. Noise margins will not be affected when interfacing to F100K since F100K is fully voltage and temperature compensated. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC006 5 CLC006 SNLS015G – AUGUST 1998 – REVISED APRIL 2013 www.ti.com VCC VEE VCC VEE Figure 8. Output Stage VCC VCC - VEE = +5V for 75: input: R1 = R3 = 232: R4 = R5 = 110: R5 75: C6 33 pF C5 33 pF R4 75: 8 4 7 J1 VIN+ 75: Coax 3 + 1 R6 75: CLC006 J2 VINR3 154: 6 - R1 154: 5 75: 2 R7 75: 75: Coax 75: RIN = 50: VBIAS = VCC - 1.62V VEE Figure 9. Differential Input DC Coupled Output 6 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC006 CLC006 www.ti.com SNLS015G – AUGUST 1998 – REVISED APRIL 2013 OUTPUT AMPLITUDE ADJUSTMENT The high and low output levels of the CLC006 are set by a circuit shown simplified in Figure 10. Output high and low levels may be set independently with external resistor networks connected between REXT-H (pin 3), REXT-L (pin 4) and the power supplies. The resistor networks affect the high and low output levels by changing the internally generated bias voltages, VH and VL. The nominal high and low output levels are VCC−1.7V and VCC−3.3V, respectively, when the pins REXT-H and REXT-L are left unconnected. Though the internal components which determine output voltage levels have accurate ratios, their absolute values may be controlled only within about ±15% of nominal. Even so, without external adjustment, output voltages are well controlled. A final design should accommodate the variation in externally set output voltages due to the CLC006’s part-to-part and external component tolerances. Output voltage swing may be reduced with the circuit shown in Figure 11. A single resistance chosen with the aid of the graph, Figure 12, is connected between pins 3 and 4. Output voltage swing may be increased with the circuit of Figure 13. Figure 14 is used to estimate a value for resistor R. Note that both of these circuits and the accompanying graphs assume that the CLC006 is loaded with the standard 150Ω. Be aware that output loading will affect the output swing and the high and low levels. It may be necessary to empirically select resistances used to set output levels when the D.C. loading on the CLC006 differs appreciably from 150Ω. VCC REXT-H 3.4 k: 3 VCC - 1.7V VH VCC - 3.3V VL 1 k: REXT-L 3.15 k: 1 k: 4 0.5 mA VEE Figure 10. Equivalent Bias Generation Circuit VCC VR1 10k R5 75: R4 75: 8 4 7 J1 VIN+ 3 + 1 R6 75: C1 0.1 PF J3 R7 75: C2 0.1 PF J4 CLC006 J2 VINR3 154: 6 - R1 154: 5 2 VEE Figure 11. Differential Input Reduced Output Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC006 7 CLC006 SNLS015G – AUGUST 1998 – REVISED APRIL 2013 www.ti.com 1800 OUTPUT VOLTAGE (mV) 1600 Max. 1400 1200 Min. 1000 Typ. 800 600 1 10 100 RESISTANCE (k:) Figure 12. Resistance Pins 3 to 4 vs Output Voltage Reduced Output @ 150Ω Load VCC R12 3k R4 82.5: 7 R5 82.5: J1 VIN+ R11 2.4k R VEE 8 3 4 + 1 R6 75: C1 0.1 PF J3 R7 75: C2 0.1 PF J4 CLC006 J2 VINR3 124: 6 - R1 124: 5 2 VEE Figure 13. Differential Input Increased Output 2500 OUTPUT VOLTAGE (mV) Max. 2000 Min. 1500 Typ. 1000 500 0.1 1 10 100 1000 RESISTANCE (k:) Figure 14. Resistance Pins 3 to 4 vs Output Voltage Increased Output @ 150Ω Load 8 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC006 CLC006 www.ti.com SNLS015G – AUGUST 1998 – REVISED APRIL 2013 OUTPUT RISE AND FALL TIMES Output load capacitance can significantly affect output rise and fall times. The effect of load capacitance, stray or otherwise, may be reduced by placing the output back-match resistor close to the output pin and by minimizing all interconnecting trace lengths. Figure 15 shows the effect on risetime of parallel load capacitance across a 150Ω load. OUTPUT CAPACITANCE (pFd) 50 40 30 20 10 0 500 1000 1500 2000 2500 3000 RISE TIME (ps) Figure 15. Rise Time vs CL PCB Layout Recommendations Printed circuit board layout affects the performance of the CLC006. The following guidelines will aid in achieving satisfactory device performance. • Use a ground plane or power/ground plane sandwich design for optimum performance. • Bypass device power with a 0.01 µF monolithic ceramic capacitor in parallel with a 6.8 µF tantalum electrolytic capacitor located no more than 0.1” (2.5 mm) from the device power pins. • Provide short, symmetrical ground return paths for: – inputs, – supply bypass capacitors and – the output load. • Provide short, grounded guard traces located – under the centerline of the package, – 0.1” (2.5 mm) from the package pins – on both top and bottom of the board with connecting vias. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC006 9 CLC006 SNLS015G – AUGUST 1998 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision F (April 2013) to Revision G • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC006 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CLC006BM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 CLC00 6BM>D CLC006BMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 CLC00 6BM>D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of