CLC406AJ-QML

CLC406 Wideband, Low Power Monolithic Op Amp General Description Features The CLC406 is a wideband monolithic operational amplifier designed for low gain applications where power and cost are of primary concern. Operating from ± 5V supplies, the CLC406 consumes only 50mW of power yet maintains a 160MHz small signal bandwidth and a 1500V/µs slew rate. Benefiting from National’s current feedback architecture, the CLC406 offers a gain range of ± 1 to ± 10 while providing stable, oscillation free operation without external compensation, even at unity gain. With its exceptional differential gain and phase typically 0.02% and 0.02˚ at 3.58MHz, the CLC406 is designed to meet the performance and cost requirements of high volume composite video applications. The CLC406’s large signal bandwidth, high slew rate and high drive capability are features well suited for RGB video applications. Providing a 12ns settling time to 0.05% (1/2 LSB in 10-bit systems) and −68/−75dBc 2nd/3rd harmonic distortion (2VPP at 10MHz, RL = 1kΩ), the CLC406 is an excellent choice as a buffer or driver for high speed A/D and D/A converter systems. Commercial remote sensing applications and battery powered radio transceivers requiring a high performance, low power amplifier will find the CLC406 to be an attractive, cost effective solution. Constructed using an advanced, complementary bipolar process and National’s proven current feedback architectures, the CLC406 is available in several versions to meet a variety of requirements. n n n n n n n 160MHz small signal bandwidth 50mW power ( ± 5V supplies) 0.02%/0.02˚ differential gain/phase 12ns settling to 0.05% 1500V/µs slew rate 2.2ns rise and fall time (2VPP) 70mA output current Applications n n n n n n n Video distribution amp HDTV amplifier Flash A/D driver D/A transimpedance buffer Pulse amplifier Photodiode amp LAN amplifier Small Signal Pulse Response DS012747-17 Connection Diagrams Pinout DIP & SOIC DS012747-16 DS012747-15 Pinout SOT23-5 © 2001 National Semiconductor Corporation DS012747 www.national.com CLC406 Wideband, Low Power Monolithic Op Amp February 2001 CLC406 Ordering Information Package Temperature Range Industrial Part Number Package Marking NSC Drawing 8-pin plastic DIP −40˚C to +85˚C CLC406AJP CLC406AJP N08E 8-pin plastic SOIC −40˚C to +85˚C CLC406AJE CLC406AJE M08A 5-pin SOT −40˚C to +85˚C CLC406AJM5 A17 MA05A www.national.com 2 Operating Temperature Range Storage Temperature Range Lead Solder Duration (+300˚C) EDS rating (human body model) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) IOUT Output is short circuit protected to ground, but maximum reliability will be maintained if IOUT does not exceed... Common Mode Input Voltage Differential Input Voltage Junction Temperature ± 7V −40˚C to +85˚C −65˚C to +150˚C 10 sec 2000V Operating Ratings Thermal Resistance Package MDIP SOIC SOT23-5 70mA ± VCC 10V +150˚C (θJC) 70˚C/W 65˚C/W 130˚C/W (θJA) 125˚C/W 145˚C/W 150˚C/W Electrical Characteristics AV = +6, VCC = ± 5V, RL =100Ω, Rf = 500Ω; unless specified Symbol Parameter Ambient Temperature Conditions Typ Max/Min Ratings (Note 2) Units CLC406AJ +25˚C −40˚C +25˚C +85˚C VOUT < 2VPP 160 130 > 110 > 95 > 90 > 80 MHz VOUT < 5VPP > 110 > 95 < 0.2 < 0.5 < 0.6 < 0.8 < 0.04 < 0.2 < 0.5 < 1.0 < 1.2 < 0.04 dB Ambient Temperature Frequency Domain Response SSBW −3dB Bandwidth LSBW Gain Flatness MHz VOUT < 2VPP LPD Linear Phase Deviation DC to 75MHz 0.2 DG1 Differential Gain, AV = +2 RL = 150Ω, 3.58MHz 0.02 < 0.2 < 0.5 < 0.6 < 0.8 < 0.04 RL = 150Ω, 4.43MHz 0.02 < 0.04 < 0.04 < 0.04 % RL = 150Ω, 3.58MHz 0.02 < 0.04 < 0.04 < 0.08 deg RL = 150Ω, 4.43MHz 0.025 < 0.05 < 0.05 < 0.10 deg < 3.0 < 3.6 < 18 < 15 > 1200 < 3.9 < 5.0 < 20 < 15 > 1000 ns 1500 < 3.0 < 3.6 < 18 < 15 > 1200 V/µs 2VPP, 20MHz RL =100Ω −46 < −42 < −42 < −38 dBc 2VPP, 10MHz RL = 1kΩ −68 < −62 < −62 < −60 dBc 2VPP 20MHz RL = 100Ω −50 < −46 < −46 < −42 dBc 2VPP, 10MHz RL = 1kΩ −75 < −70 < −70 < −65 dBc > 1MHz 2.7 3.4 3.4 3.8 GFPL Peaking DC to 25MHz 0 GFPH Peaking > 25MHz 0 GFR Rolloff DC to 50MHz 0 DG2 DP1 Differential Phase, AV = +2 DP2 dB dB deg % Time Domain Response TRS Rise and Fall Time TRL 2V Step 2.2 4V Step 3.0 TS Settling Time to 0.05 % 2V Step 12 OS Overshoot 2V Step 8 SR Slew Rate ns ns % Distortion And Noise Response HD2 2nd Harmonic Distortion HD2L HD3 3rd Harmonic Distortion HD3L Equivalent Input Noise VN Non Inverting Voltage 3 nV/ www.national.com CLC406 Absolute Maximum Ratings (Note 1) CLC406 Electrical Characteristics (Continued) AV = +6, VCC = ± 5V, RL =100Ω, Rf = 500Ω; unless specified Symbol Parameter Conditions Typ Max/Min Ratings (Note 2) Units Distortion And Noise Response ICN Inverting Current > 1MHz 11.0 13.9 13.9 15.5 pA/ NCN Non Inverting Current > 1MHz 2.1 2.6 2.6 3.0 pA/ SNF Total Noise Floor > 1MHz −157 1MHz to 100MHz < −156 < 38 dBm1Hz Total Integrated Noise < −156 < 38 −155 INV < 42 µV < 10 < 60 46 > 45 < 7.0 > 46 > 45 < 6.7 > 44 > 43 < 6.7 > 500 < 2.0 < 0.3 > 500 < 2.0 < 0.2 kΩ 0.2 > 300 < 2.0 < 0.6 +3.1, −2.7 +1.6, −2.5 ± 2.7 ± 2.7 V ± 2.2 ± 1.4 ± 2.0 ± 2.0 V 70 30 50 50 mA 31 Static, DC Performance VIO Input Offset Voltage (Note 3) 2 DVIO Average Temperature Coefficient 30 IBN Input Bias Current (Note 3) DIBN Average Temperature Coefficient IBI Input Bias Current (Note 3) DIBI Average Temperature Coefficient 20 PSRR Power Supply Rejection Ratio 50 CMRR Common Mode Rejection Ratio 50 ICC Supply Current (Note 3) Non Inverting 5 30 Inverting 3 No Load 5.0 – – mV µA µA nA/˚C dB dB mA Miscellaneous Performance RIN Non Inverting Input Resistance CIN Non Inverting Input Capacitance 1000 RO Output Impedance DC VO Output Voltage Range RL = 100Ω CMIR Common Mode Input Range IO Output Current 1.0 pF Ω Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at + 25˚C. www.national.com 4 TA = 25˚C, AV = +6V, VCC = ± 5V, RL = 100Ω, Rf = 500Ω; un- less specified Non-Inverting Frequency Response Inverting Frequency Response DS012747-1 Large Signal Inverting Frequency Response DS012747-2 Small Signal Pulse Response DS012747-3 DS012747-17 Short-Term Settling Time Long-Term Settling Time DS012747-18 DS012747-19 5 www.national.com CLC406 Typical Performance Characteristics CLC406 Typical Performance Characteristics TA = 25˚C, AV = +6V, VCC = ± 5V, RL = 100Ω, Rf = 500Ω; unless specified (Continued) Harmonic Distortion 2-Tone, 3rd Order, Spurious Levels DS012747-5 DS012747-4 Rs and Settling Time vs. Capacitive Load 2nd Harmonic Distortion vs. Output Power DS012747-7 DS012747-6 3rd Harmonic Distortion vs. Output Power Differential Gain and Phase (4.43MHz Video) DS012747-9 DS012747-8 www.national.com 6 TA = 25˚C, AV = +6V, VCC = ± 5V, RL = 100Ω, Rf = 500Ω; unless specified (Continued) Equivalent Input Noise PSRR, CMRR, and Closed Loop RO DS012747-10 DS012747-11 Open-Loop Transimpedance Gain, Z(s) DS012747-12 7 www.national.com CLC406 Typical Performance Characteristics CLC406 Application Division DS012747-13 FIGURE 1. Recommended Non-Inverting Gain Circuit DS012747-14 FIGURE 2. Recommended Inverting Gain Circuit Feedback Resistor The CLC406 achieves its exceptional AC performance while requiring very low quiescent power by using the current feedback topology and an internal slew rate enhancement circuit. The loop gain and frequency response for a current feedback op amp is predominantly set by the feedback resistor value. The CLC406 is optimized for a gain of +6 to use a 500Ω feedback resistor (for maximally flat response at a gain of +2, use Rf = 1kΩ).Using lower values can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth. Application Note OA-13 provides a more detailed discussion of choosing a feedback resistor. A plot found within the CLC415 data sheet entitled “Recommended Rfvs. Gain” is also applicable to the CLC406. The values of Rf found on this plot will optimize the performance of the CLC406 over its ± 1 to ± 10 gain range. www.national.com The CLC406, like all current feedback op amps, can be operated at higher than recommended gains with an expected reduction in bandwidth. Slew Rate and Harmonic Distortion The current feedback topology yields an inherently high slew rate amplifier. For this reason the CLC406 shows little difference in bandwidth between 2VPP and 5VPP outputs. The dominant slew rate limiting mechanism is the unity gain buffer used internally from the non-inverting to the inverting inputs. Using a slew enhancement circuit to sense the onset of slew limiting, the buffer stage momentarily increases the quiescent current to handle high slew requirements. Slew rates will decrease when operating the CLC406 at lower non-inverting gains due to the increasing signal swing through the buffer stage which is necessary to maintain a fixed desired output swing. Conversely, slew rates are 8 DC Accuracy and Noise (Continued) Equation 1 shows and example of the output offset voltage computation. The calculation is developed using typical bias current and offset voltage specifications at 25˚C, a gain (Av) of +6 and a non-inverting source impedance (Rs) of 25Ω. generally higher and relatively insensitive to gain setting for inverting gain operation. An additional discussion of slew rates can be found in the CLC404 data sheet. As the output signal swing is increased, the slew enhancement circuit found in the buffer stage acts to suppress harmonic distortions. This is one reason the CLC406 does not exhibit a simple relationship between output power and distortion. For example, the 2-tone, 3rd order spurious plot shows the spurious level to remain nearly constant over test tone power. For this reason the CLC406 does not exhibit an intercept type performance where the relative spurious levels change at twice the rate of the test tone power. Differential Gain and Phase Differential gain and phase performance specifications are common to composite video distribution applications. These specifications refer to the change in small signal gain and phase of the color subcarrier frequency (4.43MHz for PAL composite video) as the amplifier output is swept over a range of DC voltages. For this test only, the CLC406 is specified at a gain of +2 while connected to one or more doubly terminated 75Ω loads. Application Note OA-08 provides an additional discussion of differential gain and phase measurements. Non-inverting Source Impedance For best operation, the DC source impedance looking out of the non-inverting input should be less than 3kΩ but greater than 20Ω. Parasitic self oscillations may occur in the input transistors if the DC source impedance is out of this range. This impedance also acts as the gain for the non-inverting input bias and noise currents and therefore can become troublesome for high values of DC source impedance. The inverting configuration of Figure 2 shows a 25Ω resistor to ground on the non-inverting input which insures stability but does not provide bias current cancellation. The input bias currents are unrelated for a current feedback amplifier which eliminates the need for source impedance matching to achieve bias current cancellation. Equation 1: Output Offset Voltage Calculation Output Offset Voltage VO =( ± IbnRin ± Vio)(1+Rf/Rg) ± IbiRf VO =( ± 5µA(25Ω) ± 2mV)(6) ± 3µA(500Ω)= ± 14.25mV Improved output offset voltage is possible using the composite circuits shown in Application Note OA-07. The total output spot noise is computed in a similar fashion to the output offset voltage. Using the input spot noise voltage and the two input spot noise currents, the total output spot noise is developed through the same gain equations for each term but combined as the square root of the sum of squared contributing elements. Application Note OA-12 provides a more detailed discussion of noise calculations for current feedback amplifiers. Printed Circuit Layout As with any high speed component, a careful attention to the board layout is necessary for optimum performance. Of particular importance is the careful control of parasitic capacitances on the output pin. As the output impedance plot shows, the closed loop output of the CLC406 eventually becomes inductive as the loop gain rolls off with increasing frequency. Direct capacitive loading on the output pin can quickly lead to peaking in the frequency response, overshoot in the pulse response, ringing or even sustained oscillations. The “Suggested Series Rs vs. C” plot should be used as a starting point when a capacitive load must be driven. Evaluation boards (CLC730013-DIP,CLC730027-SOIC, and CLC730068-SOT) for the CLC406 are available. Further layout suggestions can be found in Application Note OA-15. 9 www.national.com CLC406 Application Division CLC406 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin MDIP NS Package Number N08E 8-Pin SOIC NS Package Number M08A www.national.com 10 CLC406 Wideband, Low Power Monolithic Op Amp Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 5-Pin SOT23 NS Package Number MA05A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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