CLC426AJP

CLC426 Wideband, Low Noise, Voltage Feedback Op Amp General Description The National CLC426 combines an enhanced voltage feedback architecture with an advanced complimentary bipolar process to provide a high speed op amp with very low noise (1.6nV/ & 2.0pA/ ) and distortion (−62dBc/−68dBc 2nd/3rd harmonics at 1VPP and 10MHz). Providing a wide 230MHz gain bandwidth product, a fast 400V/µs slew rate and very quick 16ns settling time to 0.05%, the CLC426 is the ideal choice for high speed applications requiring a very wide dynamic range such as an input buffer for high resolution analog-to-digital converters. The CLC426 is internally compensated for gains ≥ 2V/V and can easily be externally compensated for unity gain stability in applications such as wideband low noise integrators. The CLC426 is also equipped with external supply current adjustment which allows the user to optimize power, bandwidth, noise and distortion performance for each application. The CLC426’s combination of speed, low noise and distortion and low dc errors will allow high speed signal conditioning applications to achieve the highest signal-to-noise performance. To reduce design times and assist board layout, the CLC426 is supported by an evaluation board and SPICE simulation model available from National. For even higher gain-bandwidth voltage-feedback op amps see the 1.9GHz CLC425 (AV ≥10V/V) or the 5.0GHz CLC422 (AV ≥ 30V/V). Enhanced Solutions (Military/Aerospace SMD Number: 5962-94597 n n n n n n Ultra low input voltage noise: 1.6nV/ Very low harmonic distortion: −62/−68dBc Fast slew rate: 400V/µs Adjustable supply current Dual ± 2.5 to ± 5V or single 5 to 12V supplies Externally compensatable Applications n n n n n n n Active filters & integrators Ultrasound Low power portable video ADC/DAC buffer Wide dynamic range amp Differential amps Pulse/RF amp Input Voltage Noise Density *Space level versions also available. *For more information, visit http://www.national.com/mil Features DS012709-1 n Wide gain-bandwidth product: 230MHz Connection Diagram Frequency Response DS012709-4 Pinout DIP & SOIC DS012709-3 © 2001 National Semiconductor Corporation DS012709 www.national.com CLC426 Wideband, Low Noise, Voltage Feedback Op Amp July 2001 CLC426 Typical application DS012709-2 Wide Dynamic Range Sallen-Key Band Pass Filter 2nd-Order (20MHz, Q = 10, G = 2) Ordering Information Package Temperature Range Industrial Part Number Package Marking 8-Pin Plastic DIP −40˚C to +85˚C CLC426AJP CLC426AJP N08E 8-Pin Plastic SOIC −40˚C to +85˚C CLC426AJE CLC426AJE M08A www.national.com 2 NSC Drawing Common-Mode Input Voltage Differential Input Voltage Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering 10 sec) ESD If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ± 7V (Note 6) Supply Voltage Short Circuit Current ± Vcc ± 10V +150˚C −65˚C to +150˚C +300˚C 2000V Electrical Characteristics (VCC = ± 5; AV = +2V/V; Rf = 100Ω; RL = 100Ω; unless noted) Notes Parameters Ambient Temperature Conditions CLC426 Typ Max/Min Ratings (Note 2) Units +25˚C +25˚C 0 to+70˚C −40 to+85˚C Frequency Domain Response (Note 4), (Note 5), (Note 8) Gain Bandwidth Product VOUT < 0.5VPP 230 170 120 100 MHz −3dB Bandwidth, AV = +2 VOUT < 0.5VPP 130 90 70 55 MHz VOUT < 5.0VPP 50 25 22 20 MHz Gain Flatness VOUT < 0.5VPP (Note 4), (Note 8) Peaking DC to 200MHz 0.6 1.5 2.2 2.5 dB (Note 4), (Note 8) Rolloff DC to 30MHz 0.0 0.6 1.0 1.0 dB DC to 30MHz 0.2 1.0 1.5 1.5 deg Rise and Fall Time 1V Step 2.3 3.5 5.0 6.5 ns Settling Time 2V Step to 0.05% 16 20 24 24 ns Overshoot 1V Step 5 15 15 18 % Slew Rate 5V Step 400 300 275 250 V/µs Linear Phase Deviation Time Domain Response Distortion And Noise Response (Note 3) 2nd Harmonic Distortion 1VPP,10MHz −62 −52 −47 −45 dBc (Note 3) 3rd Harmonic Distortion 1VPP,10MHz −68 −58 −54 −54 dBc Equivalent Input Noise Op Amp Only Voltage 1MHz to 100MHz 1.6 2.0 2.3 2.6 nV/ Current 1MHz to 100MHz 2.0 3.0 3.6 4.6 pA/ Static DC Performance Open-Loop Gain DC 64 60 54 54 dB 1.0 2.0 2.8 2.8 mV 10 10 µV/˚C 40 65 µA 700 nA/˚C (Note 3) Input Offset Voltage Average Drift 3 – (Note 3) Input Bias Current 5 25 Average Drift 90 – 600 (Note 3) Input Offset Current Average Drift (Note 4) (Note 3) 0.3 3 5 5 µA 5 – 25 50 nA/˚C Power-Supply Rejection Ratio DC 73 65 60 60 dB Common-Mode Rejection Ratio DC 70 62 57 57 dB Supply Current Pin #8 Open, RL = ∞ 11 12 13 15 mA Common-Mode 500 250 125 125 kΩ Differential-Mode 750 200 50 25 kΩ Common-Mode 2.0 3.0 3.0 3.0 pF Differential-Mode 2.0 3.0 3.0 3.0 pF Miscellaneous Performance Input Resistance Input Capacitance 3 www.national.com CLC426 Absolute Maximum Ratings (Note 1) CLC426 Electrical Characteristics (Continued) (VCC = ± 5; AV = +2V/V; Rf = 100Ω; RL = 100Ω; unless noted) Notes Parameters Conditions Typ Max/Min Ratings (Note 2) Units Miscellaneous Performance Output Resistance Closed Loop 0.07 0.1 0.2 0.2 Ω Output Voltage Range RL = ∞ ± 3.8 ± 3.5 ± 3.7 ± 70 ± 3.5 ± 3.2 ± 3.5 ± 50 ± 3.3 ± 2.6 ± 3.3 ± 40 ± 3.3 ± 1.3 ± 3.3 V +35, −20 mA RL = 100Ω Input Voltage Range Common Mode Output Current V V Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: J-level: spec. is 100% tested at +25˚C, sample at 85˚C. L-level: spec. is 100% wafer probed at 25˚C. Note 4: J-level: spec is sample tested at 25˚C Note 5: Minimum table stable gain with out external compensation is +2 or −1V/V, the CLC426 unity-gain stable with external compensation. Note 6: Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 160mA Note 7: See test for compensation techniques. Note 8: Spec is guaranteed to 0.5VPP but tested with 0.1VPP Typical Performance Characteristics (TA = 25˚C, ± VCC = ± 5V, AV = +2, Rf = 100Ω, RL = 100Ω, unless noted) Non-Inverting Frequency Response Inverting Frequency Response DS012709-5 Frequency Response vs. Load Resistance DS012709-6 Open-Loop Gain vs. Supply Current DS012709-7 www.national.com DS012709-8 4 (TA = 25˚C, ± VCC = ± 5V, AV = +2, Rf = 100Ω, RL = 100Ω, unless noted) (Continued) Open-Loop Gain vs. Compensation Cap. Frequency Response vs. Compensation Cap. DS012709-10 DS012709-9 Supply Current vs. Rp Voltage Noise vs. Supply Current DS012709-12 DS012709-11 Frequency Response vs. Output Amplitude Gain-Bandwidth Product vs Supply Current DS012709-14 DS012709-13 5 www.national.com CLC426 Typical Performance Characteristics CLC426 Typical Performance Characteristics (TA = 25˚C, ± VCC = ± 5V, AV = +2, Rf = 100Ω, RL = 100Ω, unless noted) (Continued) Current Noise vs. Supply Current Maximum Output Voltage vs. Load DS012709-15 DS012709-16 CMRR and PSRR Closed-Loop Output Resistance DS012709-18 DS012709-17 Typical DC Errors vs. Temperature Short-Term Settling Time DS012709-20 DS012709-19 www.national.com 6 (TA = 25˚C, ± VCC = ± 5V, AV = +2, Rf = 100Ω, RL = 100Ω, unless noted) (Continued) Frequency Response vs. Capacitive Load Settling Time vs. Capacitive Load DS012709-21 Pulse Response (VOUT = 100mVPP) DS012709-22 Pulse Response (VOUT = 2VPP) DS012709-24 DS012709-23 2nd Harmonic Distortion vs. Output Power 2nd Harmonic Distortion DS012709-25 DS012709-26 7 www.national.com CLC426 Typical Performance Characteristics CLC426 Typical Performance Characteristics (TA = 25˚C, ± VCC = ± 5V, AV = +2, Rf = 100Ω, RL = 100Ω, unless noted) (Continued) 3rd Harmonic Distortion vs. Output Power 3rd Harmonic Distortion DS012709-28 DS012709-27 Application Discussion Introduction The CLC426 is a wide bandwidth voltage-feedback operational amplifier that is optimized for applications requiring wide dynamic range. The CLC426 features adjustable supply current and external compensation for the added flexibility of tuning its performance for demanding applications. The Typical Performance section illustrates many of the performance trade-offs. Although designed to operate from ± 5Volt power supplies, the CLC426 is equally impressive operating from a single +5V supply. The following discussion will enable the proper selection of external components for optimum device performance in a variety of applications. External Compensation The CLC426 is stable for noise gains ≥2V/V. For unity-gain operation, the CLC426 requires an external compensation capacitor (from pin 5 to ground). The plot located in the Typical Performance section labeled “Frequency Response vs. Compensation Cap.” illustrates the CLC426’s typical AC response for different values of compensation capacitor. From the plot it is seen that a value of 15pF produces the optimal response of the CLC426 at unity gain. The plot labeled “Open-Loop Gain vs. Compensation Cap.” illustrates the CLC426’s open-loop behavior for various values of compensation capacitor. This plot also illustrates one technique of bandlimiting the device by reducing the open-loop gain resulting in lower closed-loop bandwidth. Figure 1 shows the effect of external compensation on the CLC426’s pulse response. www.national.com DS012709-29 FIGURE 1. Supply Current Adjustment The CLC426’s supply current can be externally adjusted downward from its nominal value to less than 2mA by adding an optional resistor (Rp) between pin 8 and the negative supply as shown in Figure 2. The plot labeled “Open-Loop Gain vs. Supply Current” illustrates the influence that supply current has over the CLC426’s open-loop response. From the plot it is seen that the CLC426 can be compensated for unity-gain stability by simply lowering its supply current. Therefore lowering the CLC426’s supply current effectively reduces its open-loop gain to the point that there is adequate phase margin at unity gain crossover. The plot labeled “Supply Current vs. Rp” provides the means for selecting the value of Rp that produces the desired supply current. The curve in the plot represents nominal processing but a ± 12% deviation over process can be expected. The two plots labeled “Voltage Noise vs. Supply Current” and “ Current Noise vs. Supply Current” illustrate the CLC426 supply current’s effect over its input-referred noise characteristics. 8 CLC426 Application Discussion (Continued) DS012709-32 FIGURE 4. DS012709-30 Faster Settling The circuit of Figure 5 shows an alternative method for driving capacitive loads that results in quicker settling times. The small series resistor, Rs, is used to decouple the CLC426’s open-loop output resistance, Rout, from the load capacitance. The small feedback capacitance, Cf, is used to provide a high frequency bypass between the output and inverting input. The phase lead introduced by Cf compensates for the phase lag due to CL and therefore restores stability. The following equations provide values of Rs and Cf for a given load capacitance and closed-loop amplifier gain. FIGURE 2. Driving Capacitive Loads The CLC426 is designed to drive capacitive loads with the addition of a small series resistor placed between the output and the load as seen in Figure 3. Two plots located in the Typical Performance section illustrate this technique for both frequency domain and time domain applications. The plot labeled “Frequency Response vs. Capacitive Load” shows the CLC426’s resulting AC response to various capacitive loads. The values of Rs in this plot were chosen to maximize the CLC426’s AC response (limited to ≤1dB peaking). DS012709-33 DS012709-31 FIGURE 5. FIGURE 3. The second plot labeled “Settling Time vs. Capacitive Load” provides the means for the selection of the value of Rs which minimizes the CLC426’s settling time. As seen from the plot, for a given capacitive load Rs is chosen from the curve labeled “Rs”. The resulting settling time to 0.05% can then be estimated from the curve labeled “Ts to 0.05%”. The plot of Figure 4 shows the CLC426’s pulse response for various capacitive loads where Rs has been chosen from the plot labeled “Settling Time vs. Capacitive Load”. (1) (2) The plot in Figure 6 shows the result of the two methods of capacitive load driving mentioned above while driving a 100 pF||1kΩ load. 9 www.national.com CLC426 Application Discussion Equation 3 shows a means of calculating the value of Cf which will provide conditions for a maximally flat signal frequency response with approximately 65˚ phase margin and 5% step response overshoot. Notice that Ct is the sum of the DAC output capacitance and the differential input capacitance of the CLC426 which is located in its Electrical Characteristics Table. Notice also that CLC426’s gain bandwidth product (GBW) is also located in the same table. Equation 5 provides the resulting signal bandwidth. (Continued) (3) DS012709-36 FIGURE 6. Single Supply Operation The CLC426 can be operated with single power supply as shown in Figure 7 . Both the input and output are capacitively coupled to set the dc operating point. (4) Sallen-Key Active Filters The CLC426 is well suited for Sallen-Key type of active filters. shows the 2nd order Sallen-Key band-pass filter topology and design equations. DS012709-43 DS012709-37 FIGURE 7. DAC Output Buffer The CLC426’s quick settling, wide bandwidth and low differential input capacitance combine to form an excellent I-to-V converter for current output DACs in such applications as reconstruction video. The circuit ofFigure 8 implements a low noise transimpedance amplifier commonly used to buffer high speed current output devices. The transimpedance gain is sent by Rf. A feedback capacitor, Cf, is needed in order to compensate for the inductive behavior of the closed-loop frequency response of this type of circuit. DS012709-44 FIGURE 9. To design the band-pass, begin by choosing values for Rf and Rg, for example Rf = Rg = 200Ω. Then chosen reasonable values for C1and C2 (where C1 = 5C2) and then computer R1. R2 and R3 can then be computed. For optimum high frequency performance it is recommended that the resistor values fall in the range of 10Ω to 1kΩ and the capacitors be kept above 10pF. The design can be further DS012709-38 FIGURE 8. www.national.com 10 output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillation, see OA-15 for more information. National suggests the 730013 (through-hole) or the 730027 (SOIC) evaluation board as a guide for high frequency layout and as an aid in device testing and characterization. (Continued) improved by compensating for the delay through the op amp. For further details on this technique, please request Application Note OA−21 from National Semiconductor Corporation. Printed Circuit Layout Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input and 11 www.national.com CLC426 Application Discussion CLC426 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 8-Pin MDIP NS Package Number N08E www.national.com 12 CLC426 Wideband, Low Noise, Voltage Feedback Op Amp Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.