CSD16321Q5
SLPS220E – AUGUST 2009 – REVISED DECEMBER 2023
CSD16321Q5 25-V N-Channel NexFET™ Power MOSFET
Product Summary
1 Features
•
•
•
•
•
•
•
TA = 25°C
Optimized for 5-V Gate Drive
Ultra-Low Qg and Qgd
Low-Thermal Resistance
Avalanche Rated
Lead-Free Terminal Plating
RoHS Compliant
SON 5-mm × 6-mm Plastic Package
TYPICAL VALUE
VDS
Drain-to-Source Voltage
25
V
Qg
Gate Charge Total (4.5 V)
14
nC
Qgd
Gate Charge Gate-to-Drain
•
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
nC
VGS = 3 V
2.8
VGS = 4.5 V
2.1
VGS = 8 V
1.9
mΩ
1.1
V
Device Information(1)
Point-of-Load Synchronous Buck Converter
for Applications in Networking, Telecom, and
Computing Systems
Optimized for Synchronous FET Applications
DEVICE
MEDIA
QTY
PACKAGE
SHIP
CSD16321Q5
13-Inch Reel
2500
CSD16321Q5T
7-Inch Reel
250
SON
5.00-mm × 6.00-mm
Plastic Package
Tape
and
Reel
(1)
3 Description
This 25-V, 1.9-mΩ, 5-mm × 6-mm SON NexFET™
power MOSFET has been designed to minimize
losses in power conversion and optimized for 5-V gate
drive applications.
For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
25
V
VGS
Gate-to-Source Voltage
+10 / –8
V
ID
IDM
PD
Continuous Drain Current (Package Limited)
100
Continuous Drain Current (Silicon Limited),
TC = 25°C
177
Continuous Drain Current(1)
29
Pulsed Drain Current(2)
400
Power Dissipation(1)
3.1
Power Dissipation, TC = 25°C
113
TJ,
Tstg
Operating Junction,
Storage Temperature
EAS
Avalanche Energy, Single Pulse
ID = 66 A, L = 0.1 mH, RG = 25 Ω
Top View
(1)
(2)
A
A
W
–55 to 150
°C
218
mJ
Typical RθJA = 40°C/W on 1-in2, 2-oz Cu pad on 0.06-in thick
FR4 PCB.
Max RθJC = 1.1°C/W, pulse duration ≤ 100 μs, duty cycle ≤
1%.
8
10
TC = 25qC, ID = 25 A
TC = 125qC, ID = 25 A
9
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
2.5
RDS(on)
2 Applications
•
UNIT
8
7
6
5
4
3
2
1
ID = 25 A
7 VDS = 12.5 V
6
5
4
3
2
1
0
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
RDS(ON) vs VGS
9
10
D007
0
3
6
9
12
15
Qg - Gate Charge (nC)
18
21
24
D004
Gate Charge
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD16321Q5
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SLPS220E – AUGUST 2009 – REVISED DECEMBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Specifications.................................................................. 3
4.1 Electrical Characteristics.............................................3
4.2 Thermal Information....................................................3
4.3 Typical MOSFET Characteristics................................ 4
5 Device and Documentation Support..............................7
5.1 Receiving Notification of Documentation Updates......7
2
5.2 Support Resources..................................................... 7
5.3 Trademarks................................................................. 7
5.4 Electrostatic Discharge Caution..................................7
5.5 Glossary......................................................................7
6 Revision History.............................................................. 7
7 Mechanical, Packaging, and Orderable Information.... 9
7.1 Package Option Addendum...................................... 10
7.2 Tape and Reel Information........................................ 11
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4 Specifications
4.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 20 V
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = +10 / –8 V
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = 250 μA
RDS(on)
Drain-to-source on resistance
gfs
Transconductance
25
V
1
μA
100
nA
1.1
1.4
V
VGS = 3 V, ID = 25 A
2.8
3.8
VGS = 4.5 V, ID = 25 A
2.1
2.6
VGS = 8 V, ID = 25 A
1.9
2.4
VDS = 12.5 V, ID = 25 A
150
0.9
mΩ
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
2360
3100
pF
1700
2200
pF
Crss
RG
Reverse transfer capacitance
115
150
pF
Series gate resistance
1.5
3
Ω
Qg
Qgd
Gate charge total (4.5 V)
14
19
nC
Gate charge gate-to-drain
2.5
nC
Qgs
Gate charge gate-to-source
Qg(th)
Gate charge at Vth
Qoss
Output charge
td(on)
Turnon delay time
tr
Rise time
td(off)
Turnoff delay time
tf
Fall time
VGS = 0 V, VDS = 12.5 V, f = 1 MHz
VDS = 12.5 V, ID = 25 A
VDS = 15 V, VGS = 0 V
VDS = 12.5 V, VGS = 4.5 V,
ID = 25 A, RG = 2 Ω
4
nC
2.1
nC
36
nC
9
ns
15
ns
27
ns
17
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
ISD = 25 A, VGS = 0 V
0.8
Qrr
Reverse recovery charge
VDD = 13 V, IF = 25 A, di/dt = 300 A/μs
33
1
nC
V
trr
Reverse recovery time
VDD = 13 V, IF = 25 A, di/dt = 300 A/μs
32
ns
4.2 Thermal Information
TA = 25°C (unless otherwise stated)
MAX
UNIT
R θJC
Junction-to-case thermal resistance(1)
PARAMETER
1.1
°C/W
R θJA
Junction-to-ambient thermal resistance(1) (2)
50
°C/W
(1)
(2)
MIN
TYP
RθJC is determined with the device mounted on a 1-in2, 2-oz Cu pad on a 1.5-in × 1.5-in, 0.06-in thick FR4 board. RθJC is specified by
design while RθJA is determined by the user’s board design.
Device mounted on FR4 Material with 1 in2 of 2-oz Cu.
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GATE
Source
GATE
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RθJA = 50°C/W when
mounted on 1 in2 of 2-oz Cu.
Source
DRAIN
Max RθJA = 125°C/W when
mounted on minimum pad
area of 2-oz Cu.
DRAIN
M0137-01
M0137-02
4.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
Figure 4-1. Transient Thermal Impedance
4
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4.3 Typical MOSFET Characteristics
100
110
90
100
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TA = 25°C (unless otherwise stated)
80
70
60
50
40
30
20
VGS = 3 V
VGS = 4.5 V
VGS = 8 V
10
TC = 125° C
TC = 25° C
TC = -55° C
90
80
70
60
50
40
30
20
10
0
0
0
0.05
0.1
0.15
0.2
0.25
VDS - Drain-to-Source Voltage (V)
0.3
1
1.2
D002
1.4
1.6
1.8
VGS - Gate-to-Source Voltage (V)
Figure 4-2. Saturation Characteristics
2
2.2
D003
VDS = 5 V
Figure 4-3. Transfer Characteristics
10000
7
6
C - Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
8
5
4
3
1000
100
2
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
10
0
0
0
3
6
9
12
15
Qg - Gate Charge (nC)
VDS = 12.5 V
18
21
5
24
D004
10
15
20
VDS - Drain-to-Source Voltage (V)
25
D005
Figure 4-5. Capacitance
ID = 25 A
Figure 4-4. Gate Charge
10
RDS(on) - On-State Resistance (m:)
VGS(th) - Threshold Voltage (V)
1.5
1.3
1.1
0.9
0.7
0.5
-75
TC = 25qC, ID = 25 A
TC = 125qC, ID = 25 A
9
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
175
0
1
D006
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
10
D007
Figure 4-7. On Resistance vs Gate Voltage
ID = 250 µA
Figure 4-6. Threshold Voltage vs Temperature
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4.3 Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
ISD - Source-to-Drain Current (A)
Normalized On-State Resistance
1.8
1.6
1.4
1.2
1
0.8
TC = 25° C
TC = 125° C
10
1
0.1
0.01
0.001
0.0001
0.6
-75
-50
-25
0
25
50
75 100
TC - Case Temperature (°C)
ID = 25 A
125
150
0
175
D008
0.2
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
D009
Figure 4-9. Typical Diode Forward Voltage
VGS = 8 V
Figure 4-8. On Resistance vs Temperature
100
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1000
100
10
1
100 ms
10 ms
0.1
0.1
1 ms
100 µs
1
10
VDS - Drain-to-Source Voltage (V)
100
TC = 125qC
TC = 25qC
10
1
0.01
D010
Single pulse, max RθJC = 1.1°C/W
0.1
1
10
TAV - Time in Avalanche (ms)
100
D011
D012
Figure 4-11. Single Pulse Unclamped Inductive Switching
Figure 4-10. Maximum Safe Operating Area
IDS - Drain-to-Source Current (A)
120
100
80
60
40
20
0
-50
-25
0
25
50
75
100 125
TC - Case Temperature (qC)
150
175
D012
Figure 4-12. Maximum Drain Current vs Temperature
6
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5 Device and Documentation Support
5.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
5.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
5.3 Trademarks
NexFET™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
5.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
5.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
6 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2017) to Revision E (December 2023)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
Changes from Revision C (December 2016) to Revision D (May 2017)
Page
• Changed the RDS(ON) values at 3 V, 4.5 V, 8 V & the Description to match the values on the Electrical
Characteristics table. ......................................................................................................................................... 1
Changes from Revision B (May 2010) to Revision C (December 2016)
Page
• Changed Description text................................................................................................................................... 1
• Added silicon limited continuous drain current to Absolute Maximum Ratings table..........................................1
• Added max power dissipation at TC = 25°C to Absolute Maximum Ratings table..............................................1
• Changed Note 2 in Absolute Maximum Ratings table........................................................................................ 1
• Changed R θJA max from 48°C/W : to 50°C/W...................................................................................................3
• Changed the SOA in Figure 4-10 to reflect measured data............................................................................... 4
• Changed MECHANICAL DATA section to Mechanical, Packaging, and Orderable Information section............9
Changes from Revision A (January 2010) to Revision B (May 2010)
Page
• Changed RDS(on) - VGS = 3 V, ID = 25 A MAX value From: 3.5 To: 3.8...............................................................3
Changes from Revision * (August 2009) to Revision A (January 2010)
Page
• Changed the labels on the Top View pinout image............................................................................................ 1
• Changed Note 1 of the Absolute Maximum Ratings From: RθJA = 39°C/W To: Typical RθJA = 39°C/W.............1
• Changed Figure 4-1 text From: RθJA = 92°C/W To: Typical R θJA = 93°C/W.......................................................4
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•
•
8
Changed Figure 4-10 text From: RθJA = 92°C/W To: Typical R θJA = 93°C/W.....................................................4
Changed Figure 4-11 X-axis values................................................................................................................... 4
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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7.1 Package Option Addendum
Packaging Information
Orderable
Device
Status
Package Type
Package
Drawing
Pins
Package Qty
Eco Plan(2)
Lead/Ball
Finish(6)
MSL Peak
Temp(3)
Op Temp (°C)
Device
Marking(4) (5)
CSD16321Q5
ACTIVE (1)
VSON-CLIP
DQH
8
2500
RoHS-Exempt
& Green
SN
Level-1-260CUNLIM
-55 to 150
CSD16321
CSD16321Q5T
ACTIVE
VSON-CLIP
DQH
8
250
RoHS-Exempt
& Green
SN
Level-1-260CUNLIM
-55 to 150
CSD16321
(1)
(2)
(3)
(4)
(5)
(6)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material).
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on
information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming
materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
10
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7.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
CSD16321Q5T
VSONCLIP
DQH
8
250
178.0
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
12.4
6.3
5.3
1.2
8.0
12.0
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
12
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD16321Q5T
VSON-CLIP
DQH
8
250
180.0
180.0
79.0
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PACKAGE OUTLINE
DQH0008A
VSON-CLIP - 1.05 mm max height
SCALE 2.300
PLASTIC SMALL OUTLINE - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
1.05 MAX
SEATING PLANE
0.05
0.00
0.08 C
4.018
0.1
2.39
EXPOSED
THERMAL PAD
4
2X
3.81
(0.2) TYP
0.05
5
9
SYMM
4.42
0.1
6X 1.27
8
1
4X
0.71
0.51
PKG
4X
0.71
0.51
8X
PIN 1 ID
(OPTIONAL)
0.46
0.36
0.1
0.05
C A B
C
4223292/A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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SLPS220E – AUGUST 2009 – REVISED DECEMBER 2023
EXAMPLE BOARD LAYOUT
DQH0008A
VSON-CLIP - 1.05 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (1.34)
4X (0.81)
2X (1.19)
(0.39) TYP
1
8X (0.41)
8
4X
(1.245)
(R0.05) TYP
(0.715)
TYP
9
SYMM
5
4
METAL UNDER
SOLDER MASK
TYP
(4.42)
( 0.2) VIA
TYP
6X (1.27)
SOLDER MASK
OPENING
TYP
3X
(1.43)
0.05 MIN
TYP
(2.39)
4X (0.81)
PKG
(4.02)
(5.59)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:15X
4223292/A 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
DQH0008A
VSON-CLIP - 1.05 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.28)
8X (0.81)
(1.34) TYP
9
1
SOLDER MASK EDGE
TYP
8
8X (0.41)
(1.43)
TYP
SYMM
6X (1.27)
9X
(1.23)
5
4
(R0.05) TYP
METAL
TYP
PKG
9X (1.14)
(5.59)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4223292/A 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Product Folder Links: CSD16321Q5
15
PACKAGE OPTION ADDENDUM
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15-Sep-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CSD16321Q5
ACTIVE
VSON-CLIP
DQH
8
2500
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-55 to 150
CSD16321
Samples
CSD16321Q5T
ACTIVE
VSON-CLIP
DQH
8
250
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-55 to 150
CSD16321
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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