CSD17318Q2T

Order Now Product Folder Support & Community Tools & Software Technical Documents CSD17318Q2 SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 CSD17318Q2 30-V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • • 1 Product Summary Optimized for 5-V Gate Drive Low Capacitance and Charge Low RDS(ON) Low-Thermal Resistance Lead Free RoHS Compliant Halogen Free SON 2-mm × 2-mm Plastic Package TA = 25°C 30 V Qg Gate Charge Total (4.5 V) 6.0 nC Qgd Gate Charge Gate-to-Drain Drain-to-Source On-Resistance VGS(th) PART NUMBER QTY CSD17318Q2 3000 CSD17318Q2T 12.6 mΩ 0.9 V 250 MEDIA PACKAGE SHIP 7-Inch Reel SON 2.00-mm × 2.00-mm Plastic Package Tape and Reel TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 30 V VGS Gate-to-Source Voltage ±10 V Continuous Drain Current (Package Limited) 21.5 ID IDM PD 1 6 D D 3 13.9 VGS = 8 V Absolute Maximum Ratings Top View G VGS = 4.5 V (1) For all available packages, see the orderable addendum at the end of the data sheet. This 30-V, 12.6-mΩ, 2-mm × 2-mm SON NexFET™ power MOSFET is designed to minimize losses in power conversion applications and optimized for 5-V gate drive applications. The 2-mm × 2-mm SON offers excellent thermal performance for the size of the package. 2 nC 20 Threshold Voltage 3 Description D 1.3 VGS = 2.5 V Device Information(1) Storage, Tablets, and Handheld Devices Optimized for Load Switch Applications DC-DC Converters Battery and Load Management Applications D UNIT Drain-to-Source Voltage RDS(on) 2 Applications • • • • TYPICAL VALUE VDS S 5 D 4 S Continuous Drain Current (Silicon Limited), TC = 25°C 25 Continuous Drain Current(1) 10 Pulsed Drain Current, TA = 25°C(2) 68 Power Dissipation(1) 2.5 Power Dissipation, TC = 25°C 16 TJ, TSTG Operating Junction, Storage Temperature EAS Avalanche Energy, Single Pulse, ID = 12.4 A, L = 0.1 mH, RG = 25 Ω A A W –55 to 150 °C 7.7 mJ (1) Typical RθJA = 55°C/W on a 1-in2, 2-oz Cu pad on a 0.06-in thick FR4 PCB. (2) Max RθJC = 7°C/W, pulse duration ≤ 100 μs, duty cycle ≤ 1%. P0108-01 On-State Resistance vs Gate to Source Voltage Gate Charge 8 TC = 25° C, I D = 8 A TC = 125° C, I D = 8 A 35 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) 40 30 25 20 15 10 5 0 ID = 8 A 7 VDS = 15 V 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 VGS - Gate-To-Source Voltage (V) 9 10 D007 0 2 4 6 8 Qg - Gate Charge (nC) 10 12 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD17318Q2 SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Characteristics ............................................ 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 6.2 6.3 6.4 6.5 7 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 7 Mechanical Data..................................................... 8 7.1 Q2 Package Dimensions .......................................... 8 7.2 Q2 Tape and Reel Information................................ 10 4 Revision History Changes from Original (February 2017) to Revision A • 2 Page Updated the Mechanical Data drawings................................................................................................................................. 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD17318Q2 CSD17318Q2 www.ti.com SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage VGS = 0 V, VDS = 24 V 1 μA IGSS Gate-to-source leakage VDS = 0 V, VGS = 10 V 100 nA VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA V RDS(on) Drain-to-source on-resistance gfs Transconductance 30 0.6 V 0.9 1.2 VGS = 2.5 V, ID = 8 A 20 30 VGS = 4.5 V, ID = 8 A 13.9 16.9 VGS = 8 V, ID = 8 A 12.6 15.1 VDS = 3 V, ID = 8 A 42 mΩ S DYNAMIC CHARACTERISTICS Ciss Input capacitance VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 676 879 pF Coss Output capacitance 71 92 pF Crss Reverse transfer capacitance 39 51 pF RG Series gate resistance 1.0 2.0 Ω Qg Gate charge total (4.5 V) 6.0 nC Qgd Gate charge gate-to-drain 1.3 nC Qgs Gate charge gate-to-source 1.5 nC Qg(th) Gate charge at Vth 0.7 nC Qoss Output charge 2.7 nC td(on) Turnon delay time 5 ns tr Rise time 16 ns td(off) Turnoff delay time 13 ns tf Fall time 4 ns VDS = 15 V, ID = 8 A VDS = 15 V, VGS = 0 V VDS = 15 V, VGS = 4.5 V, ID = 8 A, RG = 2 Ω DIODE CHARACTERISTICS VSD Diode forward voltage Qrr Reverse recovery charge trr Reverse recovery time ISD = 8 A, VGS = 0 V 0.8 VDD= 15 V, IF = 8 A, di/dt = 300 A/μs 2.9 1.0 nC V 12 ns 5.2 Thermal Characteristics TA = 25°C (unless otherwise noted) TYP MAX UNIT RθJC Thermal resistance junction-to-case (1) PARAMETER 7.9 °C/W RθJA Thermal resistance junction-to-ambient (1) (2) 65 °C/W (1) (2) MIN RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-inch (3.81-cm × 3.81cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD17318Q2 3 CSD17318Q2 SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 www.ti.com Max RθJA = 250°C/W when mounted on a minimum pad area of 2-oz (0.071-mm) thick Cu. Max RθJA = 65°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu. G1 D1 S1 G1 S1 D1 M0179-01 M0180-01 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise noted) Figure 1. Transient Thermal Impedance 25 70 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 80 60 50 40 30 20 VGS = 2.5 V VGS = 4.5 V VGS = 8 V 10 0 0 0.25 0.5 0.75 1 1.25 1.5 VDS - Drain-to-Source Voltage (V) 1.75 2 20 TC = 125° C TC = 25° C TC = -55° C 15 10 5 0 0.2 0.4 D002 0.6 0.8 1 1.2 1.4 1.6 VGS - Gate-to-Source Voltage (V) 1.8 2 D003 VDS = 5 V Figure 2. Saturation Characteristics 4 Submit Documentation Feedback Figure 3. Transfer Characteristics Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD17318Q2 CSD17318Q2 www.ti.com SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise noted) 1000 7 6 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 8 5 4 3 2 100 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 1 10 0 0 2 4 6 8 Qg - Gate Charge (nC) ID = 8 A 10 0 12 5 D004 10 15 20 VDS - Drain-to-Source Voltage (V) 40 RDS(on) - On-State Resistance (m:) VGS(th) - Threshold Voltage (V) 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 TC = 25° C, I D = 8 A TC = 125° C, I D = 8 A 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 0 175 1 2 D006 3 4 5 6 7 8 VGS - Gate-To-Source Voltage (V) ID = 250 µA Figure 6. Threshold Voltage vs Temperature 10 D007 Figure 7. On-State Resistance vs Gate-to-Source Voltage 100 VGS = 2.5 V VGS = 4.5 V VGS = 8 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 9 ID = 8 A 1.8 1.4 1.2 1 0.8 0.6 0.4 -75 D005 Figure 5. Capacitance 1.3 1.6 30 VDS = 15 V Figure 4. Gate Charge 0.3 -75 25 TC = 25qC TC = 125qC 10 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (° C) 125 150 175 0 0.2 D008 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) 1 D009 ID = 8 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD17318Q2 5 CSD17318Q2 SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 www.ti.com Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise noted) 100 IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 DC 10 ms 0.1 0.1 1 ms 100 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25q C TC = 125q C 10 1 0.01 0.1 TAV - Time in Avalanche (ms) D010 1 D011 Single pulse, max RθJC = 7.9°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (qC) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD17318Q2 CSD17318Q2 www.ti.com SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.3 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD17318Q2 7 CSD17318Q2 SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 www.ti.com 7 Mechanical Data 7.1 Q2 Package Dimensions 2.1 1.9 A B PIN 1 INDEX AREA 2.1 1.9 0.8 MAX C SEATING PLANE 0.05 0.00 0.75±0.1 PKG (0.2) (0.2) TYP (0.47) 0.3±0.05 3 4 7 4X 0.65 (0.5) PKG 2X 1.3 8 0.95±0.1 6 1 (0.2) PIN 1 ID (45 X0.3) 6X 1±0.1 0.3 6X 0.2 0.35 0.25 0.1 0.05 C A C B 4222322/A 08/2015 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance. 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD17318Q2 CSD17318Q2 www.ti.com SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 Q2 Package Dimensions (continued) 7.1.1 Recommended PCB Pattern (1) PKG 6X (0.45) 1 6 8 6X (0.3) (0.95) (0.325) PKG 4X (0.65) (0.65) 7 4 3 (R0.05) TYP (0.3) (0.095) (0.75) (1.95) 0.05 MIN ALL AROUND 0.05 MAX ALL AROUND SOLDER MASK OPENING METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 1. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB Attachment (SLUA271). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD17318Q2 9 CSD17318Q2 SLPS667A – FEBRUARY 2017 – REVISED JULY 2017 www.ti.com Q2 Package Dimensions (continued) 7.1.2 Recommended Stencil Pattern (0.9) METAL ALL AROUND, TYP PKG 6X (0.45) 1 6 6X (0.3) 8 (0.86) (0.325) PKG 4X (0.65) (0.65) 7 (0.29) 3 (R0.05) TYP 4 (0.095) (0.7) (1.95) 1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7.2 Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket. 2. Cumulative tolerance of 10 sprocket holes is ±0.20. 3. Other material available. 4. Typical SR of form tape Max 109 OHM/SQ. 5. All dimensions are in mm, unless otherwise specified. 10 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD17318Q2 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD17318Q2 ACTIVE WSON DQK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 150 1718 CSD17318Q2T ACTIVE WSON DQK 6 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 150 1718 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of