CY74FCT2573CTSOCG4

CY74FCT2573T 8-BIT LATCH WITH 3-STATE OUTPUTS SCCS075 – OCTOBER 2001 D D D D D D D D D D Q OR SO PACKAGE (TOP VIEW) Function and Pinout Compatible With the Fastest Bipolar Logic 25-Ω Output Series Resistors Reduce Transmission-Line Reflection Noise Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times 3-State Outputs ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Fully Compatible With TTL Input and Output Logic Levels 12-mA Output Sink Current 15-mA Output Source Current OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC O0 O1 O2 O3 O4 O5 O6 O7 LE description The CY74FCT2573T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-Ω termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2573T can replace the CY74FCT573T to reduce noise in an existing design. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE† QSOP – Q SOIC – SO –40°C 40°C to 85°C QSOP – Q SOIC – SO SPEED (ns) ORDERABLE PART NUMBER Tape and reel 4.7 CY74FCT2573CTQCT Tube 4.7 CY74FCT2573CTSOC Tape and reel 4.7 CY74FCT2573CTSOCT Tape and reel 5.2 CY74FCT2573ATQCT Tube 8 CY74FCT2573TSOC Tape and reel 8 CY74FCT2573TSOCT TOP-SIDE MARKING FCT2573C FCT2573C FCT2573A FCT2573 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY74FCT2573T 8-BIT LATCH WITH 3-STATE OUTPUTS SCCS075 – OCTOBER 2001 FUNCTION TABLE INPUTS OE LE D OUTPUT O L H H H L H L L L L X Q0 H X X Z H = High logic level, L = Low logic level, X = Don’t care, Z = High-impedance state, Q0 = Previous state of flip flops (Q0–1) logic diagram OE LE 1 11 CP D0 2 Q 19 O0 D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 2) NOM MAX UNIT 4.75 5 5.25 V VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current –15 mA IOL TA Low-level output current 12 mA 85 °C High-level input voltage 2 Operating free-air temperature –40 NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. 2 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V CY74FCT2573T 8-BIT LATCH WITH 3-STATE OUTPUTS SCCS075 – OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.75 V, VCC = 4.75 V, IIN = –18 mA IOH = –15 mA VOL ROUT VCC = 4.75 V, VCC = 4.75 V, IOL = 12 mA IOL = 12 mA Vhys II All inputs IIH IIL IOZH IOZL IOS‡ Ioff ICC ∆ICC ICCD¶ IC# MIN 2.4 20 TYP† MAX UNIT –0.7 –1.2 V 3.3 V 0.3 0.55 V 28 40 Ω 5 µA ±1 µA ±1 µA 10 µA 0.2 VCC = 5.25 V, VCC = 5.25 V, VIN = VCC VIN = 2.7 V VCC = 5.25 V, VCC = 5.25 V, VIN = 0.5 V VOUT = 2.7 V VCC = 5.25 V, VCC = 5.25 V, VOUT = 0.5 V VOUT = 0 V –60 VCC = 0 V, VCC = 5.25 V, –120 V –10 µA –225 mA ±1 µA VOUT = 4.5 V VIN ≤ 0.2 V, VIN ≥ VCC – 0.2 V VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.1 0.2 mA 0.5 2 mA VCC = 5.25 V, One input switching at 50% duty cycle, Outputs open, OE = GND, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.06 0.12 mA/ MHz 0.7 1.4 1 2.4 1.3 2.6|| 3.3 10.6|| 6 10 25 V VCC = 5 5.25 V, Outputs open,, OE = GND, LE = VCC One input switching at f1 = 10 MHz at 50% duty cycle Eight bits switching at f1 = 2.5 MHz at 50% duty cycle VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VIN = 3.4 V or GND Ci mA pF Co 8 12 pF † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND ¶ This parameter is derived for use in total power-supply calculations. # IC = ICC + ∆ICC × DH × NT + ICCD(f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY74FCT2573T 8-BIT LATCH WITH 3-STATE OUTPUTS SCCS075 – OCTOBER 2001 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) CY74FCT2573T MIN MAX CY74FCT2573AT MIN MAX CY74FCT2573CT MIN MAX UNIT tw tsu Pulse duration, LE high 6 5 5 ns Setup time, D to LE High to low 2 2 2 ns th Hold time, D to LE High to low 1.5 1.5 1.5 ns switching characteristics over operating free-air temperature range (see Figure 1) 4 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D O tPLH tPHL LE O tPZH tPZL OE O tPHZ tPLZ OE O POST OFFICE BOX 655303 CY74FCT2573T CY74FCT2573AT CY74FCT2573CT MIN MAX MIN MAX MIN MAX 1.5 8 1.5 5.2 1.5 4.7 1.5 8 1.5 5.2 1.5 4.7 2 13 2 8.5 2 5.5 2 13 2 8.5 2 5.5 1.5 11 1.5 6.5 1.5 5.5 1.5 11 1.5 6.5 1.5 5.5 1.5 7 1.5 5.5 1.5 5 1.5 7 1.5 5.5 1.5 5 • DALLAS, TEXAS 75265 UNIT ns ns ns ns CY74FCT2573T 8-BIT LATCH WITH 3-STATE OUTPUTS SCCS075 – OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CY74FCT2573ATQCT ACTIVE SSOP DBQ 20 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT2573A Samples CY74FCT2573CTQCT ACTIVE SSOP DBQ 20 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT2573C Samples CY74FCT2573CTSOC ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT2573C Samples CY74FCT2573CTSOCT ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT2573C Samples CY74FCT2573TSOC ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT2573 Samples CY74FCT2573TSOCT ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT2573 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of