CY74FCT2652ATQCT

CY74FCT2652T 8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS044B – MAY 1994 – REVISED NOVEMBER 2001 D D D D D D D D D D D D Q PACKAGE (TOP VIEW) Function and Pinout Compatible With FCT and F Logic 25-Ω Output Series Resistors Reduce Transmission-Line Reflection Noise Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully Compatible With TTL Input and Output Logic Levels ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 12-mA Output Sink Current 15-mA Output Source Current Independent Register for A and B Buses Multiplexed Real-Time and Stored Data Transfer 3-State Outputs CPAB SAB GAB A1 A2 A3 A4 A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CPBA SBA GBA B1 B2 B3 B4 B5 B6 B7 B8 description The CY74FCT2652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. Control (GAB and GBA) inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time or stored data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during transition between stored and real-time data. A low input level selects real-time data, and a high level selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CPAB or CPBA) inputs, regardless of levels at the select- or enable-control inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2652T can replace the CY74FCT652T to reduce noise in existing designs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY74FCT2652T 8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS044B – MAY 1994 – REVISED NOVEMBER 2001 ORDERING INFORMATION PACKAGE† TA –40°C 40°C to 85°C QSOP – Q Tape and reel SPEED (ns) ORDERABLE PART NUMBER TOP-SIDE MARKING 5.4 CY74FCT2652CTQCT FCT2652C QSOP – Q Tape and reel 6.3 CY74FCT2652ATQCT FCT2652A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS DATA I/O GAB GBA CPAB CPBA SAB SBA A1–A8 B1–B8 L H H or L H or L X X Input Input OPERATION OR FUNCTION Isolation L H ↑ ↑ X X Input X H ↑ H or L X Input Input Unspecified§ H H ↑ ↑ X X‡ X Input Output X X‡ Unspecified§ Input Hold A data, store B data Output Input Store B data in both registers Store A and B data Store A data, hold B data Store A data in both registers L X H or L ↑ X L L ↑ ↑ X L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus H L H or L H or L H H Output Output Stored A data to B bus and stored B data to A bus H = High logic level, L = Low logic level, X = Don’t care, ↑ = Low-to-high clock transition ‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers. § The data output functions can be enabled or disabled by various signals at GAB or GBA. Data input functions always are enabled, i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT2652T 8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 21 GBA L 1 CPAB X 23 CPBA X 2 SAB X 22 SBA L 3 GAB H 21 GBA H X H 1 CPAB ↑ X ↑ 23 CPBA X ↑ ↑ 23 CPBA X 2 SAB L BUS A BUS A 3 1 CPAB X 22 SBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A GAB X L L BUS B 21 GBA H BUS B 3 GAB L BUS A BUS A BUS B SCCS044B – MAY 1994 – REVISED NOVEMBER 2001 2 22 SAB SBA X X X X X X STORAGE FROM A AND/OR B 3 GAB H 21 GBA L 1 23 2 22 CPAB CPBA SAB SBA H or L H or L H H TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY74FCT2652T 8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS044B – MAY 1994 – REVISED NOVEMBER 2001 logic diagram CPBA GAB SBA SAB GBA CPBA One of Eight Channels B Register D C A1 A Register B1 D C To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT2652T 8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS044B – MAY 1994 – REVISED NOVEMBER 2001 recommended operating conditions (see Note 2) MIN NOM MAX UNIT 4.75 5 5.25 V VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current –15 mA IOL TA Low-level output current 12 mA 85 °C High-level input voltage 2 Operating free-air temperature –40 V NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CY74FCT2652T 8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS044B – MAY 1994 – REVISED NOVEMBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.75, VCC = 4.75, IIN = –18 mA IOH = –15 mA VOL Rout VCC = 4.75, VCC = 4.75, IOL = 12 mA IOL = 12 mA Vhys II All inputs IIH IIL IOZH IOZL IOS‡ Ioff ICC MIN 2.4 20 TYP† MAX UNIT –0.7 –1.2 V 3.3 V 0.3 0.55 V 25 40 Ω 5 µA ±1 µA ±1 µA 10 µA 0.2 VCC = 5.25 V, VCC = 5.25 V, VIN = VCC VIN = 2.7 V VCC = 5.25 V, VCC = 5.25 V, VIN = 0.5 V VOUT = 2.7 V VCC = 5.25 V, VCC = 5.25 V, VOUT = 0.5 V VOUT = 0 V –60 –10 µA –225 mA ±1 µA VOUT = 4.5 V VIN ≤ 0.2 V, VIN ≥ VCC – 0.2 V VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.1 0.2 mA 0.5 2 mA ICCD¶ VCC = 5.25 V, One input switching at 50% duty cycle, Outputs open, GAB = GBA = GND, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.06 0.12 mA/ MHz 0.7 1.4 IC# VCC = 5.25 V, Outputs open, GAB = GBA = GND GND, SAB = CPAB = GND, SBA = VCC VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 1.2 3.4 2.8 5.6|| VIN = 3.4 V or GND 5.1 14.6|| 5 10 ∆ICC VCC = 0 V, VCC = 5.25 V, –120 V One bit switching at f1 = 5 MHz at 50% duty cycle Eight bits switching at f1 = 5 MHz at 50% duty cycle VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V Ci mA pF Co 9 12 pF † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND ¶ This parameter is derived for use in total power-supply calculations. # IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT2652T 8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS044B – MAY 1994 – REVISED NOVEMBER 2001 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) CY74FCT2652AT MIN tw† tsu Pulse duration, clock Setup time, before clock↑ th Hold time, after clock↑ † With one data channel switching, tw(L) = tw(H) = 4 ns and tr = tf = 1 ns. MAX CY74FCT2652CT MIN MAX UNIT 2 2 ns A or B 1.5 1.5 ns A or B 5 5 ns switching characteristics over operating free-air temperature range (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL GAB or GBA B or A tPHZ tPLZ GAB or GBA B or A tPLH tPHL CPAB or CPBA B or A tPLH tPHL SAB or SBA B or A POST OFFICE BOX 655303 CY74FCT2652AT • DALLAS, TEXAS 75265 CY74FCT2652CT MIN MAX MIN MAX 1.5 6.3 1.5 5.4 1.5 6.3 1.5 5.4 1.5 9.8 1.5 7.8 1.5 9.8 1.5 7.8 1.5 6.3 1.5 6.3 1.5 6.3 1.5 6.3 1.5 6.3 1.5 5.7 1.5 6.3 1.5 5.7 1.5 7.7 1.5 6.2 1.5 7.7 1.5 6.2 UNIT ns ns ns ns ns 7 CY74FCT2652T 8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCCS044B – MAY 1994 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CY74FCT2652ATQCT ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT2652A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of