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DAC5672A
SLAS528B – AUGUST 2017 – REVISED JANUARY 2018
DAC5672A 14-BIT 275 MSPS Digital-to-Analog Converter
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
•
•
14-Bit Dual Transmit Digital-to-Analog Converter
(DAC)
275 MSPS Update Rate
Single-Supply: 3 V to 3.6 V
High Spurious-Free Dynamic Range (SFDR): 84
dBc at 5 MHz
High Third-Order Two-Tone Intermodulation
(IMD3): 79 dBc at 15.1 MHz and 16.1 MHz
WCDMA Adjacent Channel Leakage Ratio
(ACLR): 78 dB at Baseband
WCDMA ACLR: 73 dB at 30.72 MHz
Independent or Single Resistor Gain Control
Dual or Interleaved Data
On-Chip 1.2-V Reference
Low Power: 330 mW
Power-Down Mode: 9 mW
Package: 48-Pin Thin-Quad Flat Pack (TQFP)
2 Applications
•
•
•
•
•
Cellular Base Transceiver Station Transmit
Channel
– CDMA: W-CDMA, CDMA2000, IS-95
– TDMA: GSM, IS-136, EDGE and UWC-136
Medical and Test Instrumentation
Arbitrary Waveform Generators (ARB)
Direct Digital Synthesis (DDS)
Cable Modem Termination System (CMTS)
Each DAC has a high-impedance, differential-current
output, suitable for single-ended or differential
analog-output configurations. External resistors allow
scaling the full-scale output current for each DAC
separately or together, typically between 2 mA and
20 mA. An accurate on-chip voltage reference is
temperature-compensated and delivers a stable 1.2-V
reference voltage. Optionally, an external reference
may be used.
The DAC5672A has two, 14-bit, parallel input ports
with separate clocks and data latches. For flexibility,
the DAC5672A supports multiplexed data for each
DAC on one port when operating in the interleaved
mode.
The DAC5672A is specifically designed for a
differential transformer-coupled output with a 50-Ω
doubly-terminated load. For a 20-mA full-scale output
current, a 4:1 impedance ratio (resulting in an output
power of 4 dBm) and 1:1 impedance ratio transformer
(–2 dBm output power) are supported.
The DAC5672A is available in a 48-pin TQFP
package. Pin compatibility between family members
provides 12-bit (DAC5662) and 14-bit (DAC5672A)
resolutions. Furthermore, the DAC5672A is pin
compatible to the DAC2904 and AD9767 dual DACs.
The device is characterized for operation over the
industrial temperature range of –40°C to 85°C.
Device Information(1)
PART NUMBER
DAC5672A
TQFP (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
Functional Block Diagram
The DAC5672A device is a monolithic, dual-channel,
14-bit, high-speed DAC with on-chip voltage
reference.
Operating with update rates of up to 275 MSPS, the
DAC5672A offers exceptional dynamic performance,
tight-gain, and offset matching characteristics that
make the device well-suited in I/Q baseband or direct
IF communication applications.
PACKAGE
WRTB
WRTA
CLKB
CLKA
DEMUX
IOUTA1
Latch A
14−b DAC
DA[13:0]
IOUTA2
BIASJ_A
IOUTB1
Latch B
DB[13:0]
14−b DAC
MODE
IOUTB2
BIASJ_B
GSET
1.2 V Reference
EXTIO
SLEEP
DVDD
DGND
AVDD
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC5672A
SLAS528B – AUGUST 2017 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Electrical Characteristics........................................... 7
Electrical Characteristics: AC Characteristics........... 7
Electrical Characteristics: Digital Characteristics...... 9
Switching Characteristics .......................................... 9
Typical Characteristics .......................................... 10
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2
7.3
7.4
7.5
8
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
14
15
16
20
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2009) to Revision B
Page
•
Added Device Information table ............................................................................................................................................ 1
•
Added Temperature Coefficients Offset Drift and Gain Drift to Electrical Characteristics section ........................................ 1
•
Added Feature Description section ........................................................................................................................................ 1
•
Added fDATA = 200 MSPS, fOUT = 1 MHz to Power Supply in the Electrical Characteristics section....................................... 1
•
Changed Dual-Bus Data Interface and Timing in Programming section................................................................................ 1
•
Added 3.3 MAX and 0.8 MAX to Digital Input in Electrical Characteristics section ............................................................... 1
•
Deleted Available Options table ............................................................................................................................................. 1
•
Reformatted pinout diagram and pin table in Pin Configuration and Functions section ........................................................ 1
•
Added ESD Ratings table ...................................................................................................................................................... 1
•
Added Recommended Operating Conditions table ............................................................................................................... 1
•
Added Thermal Information table .......................................................................................................................................... 1
•
Changed formatting of Table 1 ............................................................................................................................................... 1
•
Added Application Information and Typical Application sections ........................................................................................... 1
•
Added Power Supply Recommendations section ................................................................................................................. 1
•
Added Layout section ............................................................................................................................................................ 1
Changes from Original (September 2007) to Revision A
Page
•
Added Internal pulldown. ........................................................................................................................................................ 3
•
Added Internal pulldown. ........................................................................................................................................................ 4
•
Added The pullup and pulldown circuitry is approximately equivalent to 100 kΩ. ............................................................... 20
•
Added resistor values ........................................................................................................................................................... 21
•
Added resistor values ........................................................................................................................................................... 21
2
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SLAS528B – AUGUST 2017 – REVISED JANUARY 2018
5 Pin Configuration and Functions
GSET
BIASJ_B
IOUTB2
IOUTB1
AGND
SLEEP
40
39
38
37
43
41
EXTIO
44
42
IOUTA2
BIASJ_A
45
AVDD
IOUTA1
46
MODE
47
48
PFB Package
48-Pin TQFP
Top View
DB7
DA5
9
28
DB8
DA4
10
27
DB9
DA3
11
26
DB10
DA2
12
25
DB11
DGND
DGND
24
29
DB12
8
23
DB6
DA6
DB13 (MSB)
30
22
7
21
DB5
DA7
DVDD
31
20
6
WRTB/SELECTIQ
DB4
DA8
19
32
18
5
CLKA/CLKIQ
DB3
DA9
CLKB/RESETIQ
33
17
4
16
DB2
DA10
DVDD
34
WRTA/WRTIQ
3
15
DB1
DA11
14
DB0 (LSB)
35
13
36
2
DA1
1
DA12
DA0 (LSB)
DA13 (MSB)
Not to scale
Pin Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
38
I
Analog ground
AVDD
47
I
Analog supply voltage
BIASJ_A
44
O
Full-scale output current bias for DACA
BIASJ_B
41
O
Full-scale output current bias for DACB
CLKA/CLKIQ
18
I
Clock input for DACA, CLKIQ in interleaved mode
CLKB/RESETIQ
19
I
Clock input for DACB, RESETIQ in interleaved mode
I
Data port A. DA13 is MSB and DA0 is LSB. Internal pulldown.
1
2
3
4
5
6
DA[13:0]
7
8
9
10
11
12
13
14
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Pin Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
23
24
25
26
27
28
DB[13:0]
29
30
I
Data port B. DB13 is MSB and DB0 is LSB. Internal pulldown.
I
Digital ground
I
Digital supply voltage
31
32
33
34
35
36
15
DGND
21
16
DVDD
22
EXTIO
43
I/O
GSET
42
I
Gain-setting mode: H – 1 resistor, L – 2 resistors. Internal pullup.
IOUTA1
46
O
DACA current output. Full-scale with all bits of DA high.
IOUTA2
45
O
DACA complementary current output. Full-scale with all bits of DA low.
IOUTB1
39
O
DACB current output. Full-scale with all bits of DB high.
IOUTB2
40
O
DACB complementary current output. Full-scale with all bits of DB low.
MODE
48
I
Mode Select: H – Dual Bus, L – Interleaved. Internal pullup.
SLEEP
37
I
Sleep function control input: H – DAC in power-down mode, L – DAC in operating mode.
Internal pulldown.
WRTA/WRTIQ
17
I
Input write signal for PORT A (WRTIQ in interleaving mode)
WRTB/SELECTIQ
20
I
Input write signal for PORT B (SELECTIQ in interleaving mode)
4
Internal reference output (bypass with 0.1 μF to AGND) or external reference input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
4
V
Voltage between AGND and DGND
–0.5
0.5
V
Voltage between AVDD and DVDD
–4
4
V
–0.5
DVDD + 0.5
V
–0.5
DVDD + 0.5
V
–1
AVDD + 0.5
V
–0.5
AVDD + 0.5
Supply voltage
AVDD
(2)
DVDD
(3)
DA [13:0] and DB [13:0]
(3)
MODE, SLEEP, CLKA, CLKB, WRTA, WRTB
(3)
Supply voltage
IOUTA1, IOUTA2, IOUTB1, IOUTB2
EXTIO, BIASJ_A, BIASJ_B, GSET
(2)
(2)
V
Peak input current (any input)
20
mA
Peak total input current (all inputs)
–30
mA
Operating free-air temperature range
–40
85
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to AGND.
Measured with respect to DGND.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±2000
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD
3.0
3.3
3.6
DVDD
3.0
3.3
3.6
V
I(AVDD) Analog supply current
75
90
mA
I(DVDD) Digital supply current
25
38
mA
2
20
mA
–1
1.25
V
275
MHz
Supplies
V
Analog Output
IO(FS) Full-scale output current
Output voltage compliance range
Clock Interface (CLK, CLKC)
CLKINPUT Frequency
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6.4 Thermal Information
DAC5672A
THERMAL METRIC (1)
PFB (TQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
64.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.7
°C/W
RθJB
Junction-to-board thermal resistance
27.7
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
27.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
Resolution
DC ACCURACY
14
Bits
(1)
INL
Integral nonlinearity
DNL
Differential nonlinearity
1 LSB = IOUTFS / 214, TMIN to TMAX
–4
±1.1
4
LSB
–3
±0.75
3
LSB
ANALOG OUTPUT
Offset error
Midscale value
±0.03
%FSR
Offset mismatch
Midscale value
±0.03
%FSR
With external reference
±0.25
%FSR
With internal reference
±0.25
%FSR
Gain error
Minimum full-scale output current
Maximum full-scale output current
(2)
(2)
Gain mismatch
Output voltage compliance range
RO
Output resistance
CO
Output capacitance
2
mA
20
mA
With external reference
–2
0.2
2
%FSR
With internal reference
–2
0.2
2
%FSR
(3)
–1
1.25
V
300
kΩ
5
pF
REFERENCE OUTPUT
Reference voltage
Reference output current
1.14
(4)
1.2
1.26
100
V
nA
REFERENCE INPUT
VEXTIO
Input voltage
RI
Input resistance
CI
0.1
1.25
V
1
MΩ
Small signal bandwidth
300
kHz
Input capacitance
100
pF
TEMPERATURE COEFFICIENTS
Offset drift
(1)
(2)
(3)
(4)
6
2
10
ppm of
FSR/°C
Measured differently through 50 Ω to AGND.
Nominal full-scale current (IOUTFS) equals 32 times the IBIAS current
The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5672A device. The upper limit of the output compliance is determined by the load resistors and
ful-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
Use an external buffer amplifier with high-impedance input to drive any external load.
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Electrical Characteristics (continued)
over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Gain drift
MIN
TYP
MAX
With external reference (DACA)
10
43
With external reference (DACB)
20
80
With internal reference
40
160
Reference voltage drift
20
UNIT
ppm of
FSR/°C
ppm of
FSR/°C
ppm /°C
6.6 Electrical Characteristics
over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, fDATA = 200 MSPS, fOUT = 1 MHz, independent gain set mode, (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD
Analog supply voltage
3
3.3
3.6
V
DVDD
Digital supply voltage
3
3.3
3.6
V
Including output current through load
resistor
75
90
mA
Sleep mode with clock
2.5
6
mA
Sleep mode without clock
2.5
fDATA = 200 MSPS, fOUT = 1 MHz
25
38
mA
13.4
18
mA
IAVDD
IDVDD
Analog supply current
Digital supply current
Sleep mode with clock
Power dissipation
Sleep mode without clock
0.6
fDATA = 200 MSPS, fOUT = 1 MHz
330
Sleep mode with clock
53
Sleep mode without clock
9.2
fDATA = 275 MSPS, fOUT = 20 MHz
350
mA
mA
390
mW
APSRR
Analog power supply rejection ratio
–0.2
–0.01
0.2
%FSR/V
DPSRR
Digital power supply rejection ratio
–0.2
0
0.2
%FSR/V
TA
Operating free-air temperature
–40
85
°C
6.7 Electrical Characteristics: AC Characteristics
AC specifications over TA , AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, differential 1:1 impedance ratio transformer coupled
output, 50-Ω doubly terminated load (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT
(1)
fclk
Maximum output update rate
ts
Output settling time to 0.1% (DAC) Midscale transition
20
ns
tr
Output rise time 10% to 90%
(OUT)
1.4
ns
tf
Output fall time 10% to 90% (OUT)
1.5
ns
IOUTFS = 20 mA
55
pA/√Hz
IOUTFS = 2 mA
30
pA/√Hz
Output noise
275
MSPS
AC LINEARITY
(1)
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Electrical Characteristics: AC Characteristics (continued)
AC specifications over TA , AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, differential 1:1 impedance ratio transformer coupled
output, 50-Ω doubly terminated load (unless otherwise noted)
PARAMETER
SFDR
Spurious-free dynamic range
TEST CONDITIONS
Signal-to-noise ratio
1st Nyquist zone:
TA = 25°C fDATA = 50 MSPS
fOUT = 1 MHz
IOUTFS = –6 dB
80
1st Nyquist zone:
TA = 25°C
fDATA = 50 MSPS
fOUT = 1 MHz
IOUTFS = –12 dB
79
1st Nyquist zone:
TA = 25°C
fDATA = 100 MSPS
fOUT = 5 MHz
84
1st Nyquist zone, TA = 25°C, fDATA = 100
MSPS, fOUT = 20 MHz
79
IMD3
IMD
8
Adjacent channel leakage ratio
Third-order two-tone
intermodulation
Four-tone intermodulation
MAX
UNIT
dBc
68
75
1st Nyquist zone, TA = 25°C, fDATA = 200
MSPS, fOUT = 41 MHz
72
1st Nyquist zone, TA = 25°C, fDATA = 275
MSPS, fOUT = 20 MHz
74
1st Nyquist zone, TA = 25°C, fDATA = 100
MSPS, fOUT = 5 MHz
77
dB
1st Nyquist zone, TA = 25°C, fDATA = 160
MSPS, fOUT = 20 MHz
70
dB
W-CDMA signal with 3.84-MHz
bandwidth, fDATA = 61.44 MSPS, IF =
15.360 MHz
ACLR
TYP
83
1st Nyquist zone, TMIN to TMAX, fDATA =
200 MSPS, fOUT = 20 MHz
SNR
MIN
1st Nyquist zone:
TA = 25°C
fDATA = 50 MSPS
fOUT = 1 MHz
IOUTFS = 0 dB
75
dB
W-CDMA signal with 3.84-MHz
bandwidth, fDATA = 122.88 MSPS, IF =
30.72 MHz
73
dB
W-CDMA signal with 3.84-MHz
bandwidth, fDATA = 61.44 MSPS,
baseband
78
dB
W-CDMA signal with 3.84-MHz
bandwidth, fDATA = 122.88 MSPS,
baseband
78
dB
Each tone at –6 dBFS, TA = 25°C, fDATA =
200 MSPS, fOUT = 45.4 MHz and 46.4
MHz
65
dBc
Each tone at –6 dBFS, TA = 25°C, fDATA =
100 MSPS, fOUT = 15.1 MHz and 16.1
MHz
79
dBc
Each tone at –12 dBFS, TA = 25°C, fDATA
= 100 MSPS, fOUT = 15.6, 15.8, 16.2, and
16.4 MHz
79
dBc
Each tone at –12 dBFS, TA = 25°C, fDATA
= 165 MSPS, fOUT = 68.8, 69.6, 71.2, and
72 MHz
61
dBc
Each tone at –12 dBFS, TA = 25°C, fDATA
= 165 MSPS, fOUT = 19, 19.1, 19.3, and
19.4 MHz
73
dBc
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Electrical Characteristics: AC Characteristics (continued)
AC specifications over TA , AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, differential 1:1 impedance ratio transformer coupled
output, 50-Ω doubly terminated load (unless otherwise noted)
PARAMETER
Channel isolation
TEST CONDITIONS
MIN
TA = 25°C, fDATA = 165 MSPS, fOUT (CH1)
= 20 MHz, fOUT (CH2) = 21 MHz
TYP
MAX
UNIT
95
dBc
6.8 Electrical Characteristics: Digital Characteristics
Digital specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT
VIH
High-level input voltage
2
3.3
VIL
Low-level input voltage
0
0.8
V
V
IIH
High-level input current
±50
0.8
µA
IIL
Low-level input current
±10
µA
IIH(GSET)
High-level input current, GSET pin
7
µA
IIL(GSET)
Low-level input current, GSET pin
–80
µA
IIH(MODE)
High-level input current, MODE pin
–30
µA
IIL(MODE)
Low-level input current, MODE pin
–80
µA
CI
Input capacitance
5
pF
6.9 Switching Characteristics
digital specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, (unless otherwise noted)
PARAMETER
tsu
Input setup time
th
Input hold time
tLPH
Input clock pulse high time
tLAT
Clock latency (WRT A/B to outputs)
tPD
Propagation delay time
TEST CONDITIONS
Dual bus mode
MIN
Single-bus interleaved mode
Dual bus mode
TYP
MAX
UNIT
1
ns
0.5
1
Single-bus interleaved mode
ns
0.5
Dual bus mode
1
ns
Single-bus interleaved mode
Dual bus mode
4
4
Single-bus interleaved mode
4
4
Dual bus mode
1.5
Single-bus interleaved mode
1.5
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ns
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1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
0
2000
4000
6000
8000
10000
12000
14000
Input Code
16000
G001
DNL − Differential Nonlinearity Error − LSB
INL − Integral Nonlinearity Error − LSB
6.10 Typical Characteristics
1.0
0.8
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
2000
8000
10000
12000
14000
16000
G002
Figure 2. Differential Nonlinearity vs Input Code
100
SFDR − Spurious-Free Dynamic Range − dBc
100
SFDR − Spurious-Free Dynamic Range − dBc
6000
Input Code
Figure 1. Integral Nonlinearity vs Input Code
95
0 dBfS
90
−6 dBfS
85
80
−12 dBfS
75
70
65
fdata = 52 MSPS
Dual Bus Mode
60
95
0 dBfS
90
−6 dBfS
85
80
−12 dBfS
75
70
65
fdata = 78 MSPS
Dual Bus Mode
60
0
4
8
12
16
fout − Output Frequency − MHz
Figure 3. Spurious-Free Dynamic Range vs Output
Frequency
10
4000
20
0
5
10
15
20
25
fout − Output Frequency − MHz
G003
30
G004
Figure 4. Spurious-Free Dynamic Range vs Output
Frequency
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Typical Characteristics (continued)
100
SFDR − Spurious-Free Dynamic Range − dBc
SFDR − Spurious-Free Dynamic Range − dBc
100
95
0 dBfS
90
85
−6 dBfS
80
−12 dBfS
75
70
65
fdata = 100 MSPS
Dual Bus Mode
60
90
0 dBfS
85
80
−6 dBfS
75
−12 dBfS
70
65
fdata = 165 MSPS
Dual Bus Mode
60
0
5
10
15
20
25
30
fout − Output Frequency − MHz
35
0
5
10 15 20 25 30 35 40 45 50 55 60
fout − Output Frequency − MHz
G005
G006
Figure 5. Spurious-Free Dynamic Range vs Output
Frequency
Figure 6. Spurious-Free Dynamic Range vs Output
Frequency
0
0
fdata = 165 MSPS
fOUT = 30.1 MHz
Dual Bus Mode
fdata = 78 MSPS
fOUT = 15 MHz
Dual Bus Mode
−20
Power − dBm
−20
Power − dBm
95
−40
−60
−60
−80
−80
−100
0.0
−40
7.8
15.6
23.4
31.2
39.0
−100
0.0
16.5
33.0
49.5
66.0
82.5
f − Frequency − MHz
f − Frequency − MHz
G008
G007
Figure 7. Single-Tone Spectrum
Figure 8. Single-Toned Spectrum
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Typical Characteristics (continued)
100
95
95
90
85
Two-Tone IMD3 − dBc
Two-Tone IMD3 − dBc
90
80
75
70
85
80
75
70
65
60
fdata = 78 MSPS
Dual Bus Mode
fout2 = fout1 + 1 MHz
65
50
60
0
5
10
15
20
25
30
0
35
fout1 − Output Frequency − MHz
G009
30
40
G010
fdata = 165 MSPS
fout2 = 31.1 MHz
Dual Bus Mode
Power − dBm
−30
−50
−70
−90
−50
−70
−90
19.5
20.0
20.5
21.0
21.5
−110
29.0
22.0
f − Frequency − MHz
29.5
30.0
30.5
31.0
31.5
32.0
f − Frequency − MHz
G011
Figure 11. Two-Tone Spectrum
12
50
−10 fout1 = 30.1 MHz
−30
Power − dBm
20
Figure 10. Two-Tone IMD3 vs Output Frequency
fdata = 78 MSPS
fout1 = 20.1 MHz
fout2 = 21.1 MHz
Dual Bus Mode
−110
19.0
10
fout1 − Output Frequency − MHz
Figure 9. Two-Tone IMD3 vs Output Frequency
−10
fdata = 165 MSPS
Dual Bus Mode
fout2 = fout1 + 1 MHz
55
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Figure 12. Two-Tone Spectrum
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Typical Characteristics (continued)
−20
−20
fdata = 122.88 MSPS
Baseband Signal
Dual Bus Mode
−40
Power − dBm
Power − dBm
−40
−60
−80
fdata = 61.44 MSPS
IF = 15.36 MHz
ACLR = 75.18 dB
Dual Bus Mode
−60
−80
−100
−100
−120
0
1
2
3
4
5
6
7
8
9
−120
7.6
10
10.1
f − Frequency − MHz
12.6
15.1
17.6
20.1
G013
G014
Figure 13. Power vs Frequency
Figure 14. Power vs Frequency
−20
−20
fdata = 122.88 MSPS
IF = 15.36 MHz
ACLR = 77.16 dB
Dual Bus Mode
−40
Power − dBm
Power − dBm
−40
−60
−80
−100
−120
7.6
22.6
f − Frequency − MHz
fdata = 122.88 MSPS
IF = 30.72 MHz
ACLR = 72.7 dB
Dual Bus Mode
−60
−80
−100
10.1
12.6
15.1
17.6
20.1
22.6
−120
23.0
f − Frequency − MHz
25.5
28.0
30.5
33.0
35.5
38.0
f − Frequency − MHz
G015
Figure 15. Power vs Frequency
G016
Figure 16. Power vs Frequency
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7 Detailed Description
7.1 Overview
The architecture of the DAC5672A uses a current steering technique to enable fast switching and high update
rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to
deliver a full-scale output current of up to 20 mA. An internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output current is formed by steering all currents to either
output summing node, IOUT1 or IOUT2. The complementary outputs deliver a differential output signal, which
improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise),
and double the peak-to-peak output signal swing by a factor of two, as compared to single-ended operation.
The segmented architecture results in a significant reduction of the glitch energy and improves the dynamic
performance (SFDR) and DNL. The current outputs maintain a very high output impedance of greater
than 300 kΩ.
When pin 42 (GSET) is high (simultaneous gain set mode), the full-scale output current for DACs is determined
by the ratio of the internal reference voltage (1.2 V) and an external resistor (RSET) connected to BIASJ_A. When
GSET is low (independent gain set mode), the full-scale output current for each DAC is determined by the ratio
of the internal reference voltage (1.2 V) and separate external resistors (RSET) connected to BIASJ_A and
BIASJ_B. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current
that can range from 2 mA to 20 mA, depending on the value of RSET.
The DAC5672A is split into a digital and an analog portion, each of which is powered through its own supply pin.
The digital section includes edge-triggered input latches and the decoder logic, while the analog section
comprises both the current source array with its associated switches, and the reference circuitry.
7.2 Functional Block Diagram
WRTB
WRTA
CLKB
CLKA
DEMUX
IOUTA1
Latch A
14−b DAC
DA[13:0]
IOUTA2
BIASJ_A
IOUTB1
Latch B
DB[13:0]
14−b DAC
MODE
IOUTB2
BIASJ_B
GSET
1.2 V Reference
EXTIO
SLEEP
DVDD
14
DGND
AVDD
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7.3 Feature Description
7.3.1 Input Interfaces
The DAC5672A features two operating modes selected by the MODE pin, as shown in Table 1.
• For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own
separate data input bus, clock input, and data write signal (data latch-in).
• In single-bus interleaved mode, the data must be presented interleaved at the A-channel input bus. The Bchannel input bus is not used in this mode. The clock and write input are now shared by both DACs.
Table 1. Operating Modes
MODE PIN
BUS INPUT
MODE pin connected to DGND
Single-bus interleaved mode, clock and write input equal for both DACs
MODE pin connected to DVDD
Dual-bus mode, DACs operate independently
7.3.2 Dual-Bus Data Interface and Timing
In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5672A
consist of two independent, 14-bit, parallel data ports. Each DAC channel is controlled by its own set of write
(WRTA, WRTB) and clock (CLKA, CLKB) lines. The WRTA, WRTB lines control the channel input latches and
the CLKA, CLKB lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the
WRTA, WRTB line.
The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock
domains having equal periods (but possibly different phases) are input to the DAC5672A. The DAC5672A is
defined by a minimum requirement of the time between the rising edge of the clock and the rising edge of the
write inputs. The rising edge of CLKA, CLKB must occur at the same time or before the rising edge of the WRTA,
WRTB signal. A minimum delay of 2 ns must be maintained if the rising edge of the clock occurs after the rising
edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected
externally. Note that all specifications were measured with the WRTA, WRTB and CLKA, CLKB lines connected
together.
DA[13:0]/DB[13:0]
Valid Data
tsu
th
t1ph
WRTA/WRTB
CLKA/CLKB
tsettle
tpd
tlat
IOUT
or
IOUT
Figure 17. Dual-Bus Mode Operation
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7.3.3 Single-Bus Interleaved Data Interface and Timing
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 18 shows the timing diagram. In
interleaved mode, the A- and B-channels share the write input (WRTIQ) and update clock (CLKIQ and internal
CLKDACIQ). Multiplexing logic directs the input word at the A-channel input bus to either the A-channel input
latch (SELECTIQ is high) or to the B-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data
value in the B-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ is
low, the data value in the A-channel latch is retained by presenting the latch output data to its input.
In interleaved mode, the A-channel input data rate is twice the update rate of the DAC core. As in dual-bus
mode, it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch
the A- and B-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the Aand B-DAC latches on the following falling edge of the write inputs. The DAC5672A clock input is divided by a
factor of two before it is presented to the DAC latches.
Correct pairing of the A- and B-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is
divided by two, which would translate to a non-deterministic relation between the rising edges of the CLKIQ and
CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ with respect
to the data at the input of the DAC latch is determined. CLKDACIQ is disabled (low) when RESETIQ is high.
DA[13:0]
Valid Data
tsu
th
SELECTIQ
WRTIQ
CLKIQ
RESETIQ
tsettle
tpd
tlat
IOUT
or
IOUT
Figure 18. Single-Bus Interleaved Mode Operation
7.4 Device Functional Modes
7.4.1 DAC Transfer Function
Each of the DACs in the DAC5672A has a set of complementary current outputs, IOUT1 and IOUT2. The fullscale output current, IOUTFS, is the summation of the two complementary output currents:
I
+I
)I
OUTFS
OUT1
OUT2
(1)
The individual output currents depend on the DAC code and can be expressed as:
I
OUT1
+I
OUTFS
Code Ǔ
ǒ16384
(2)
æ16383 - Code ÷ö
IOUT2 = IOUTFS x çç
÷÷
çè
ø
16384
16
(3)
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Device Functional Modes (continued)
where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the
reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).
V
REF
I
+ 32 I
+ 32
OUTFS
REF
R
SET
(4)
In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage
develops at each output according to:
V
+I
R
OUT1
OUT1
LOAD
(5)
V
+I
R
OUT2
OUT2
LOAD
(6)
The value of the load resistance is limited by the output compliance specification of the DAC5672A. To maintain
specified linearity performance, the voltage for IOUT1 and IOUT2 must not exceed the maximum allowable
compliance range.
The total differential output voltage is:
V
+V
*V
OUTDIFF
OUT1
OUT2
(2 Code * 16383)
V
+
I
OUTDIFF
OUTFS
16384
(7)
R
LOAD
(8)
7.4.2 Analog Outputs
The DAC5672A provides two complementary current outputs, IOUT1 and IOUT2. The simplified circuit of the
analog output stage representing the differential topology is shown in Figure 19. The output impedance of IOUT1
and IOUT2 results from the parallel combination of the differential switches, along with the current sources and
associated parasitic capacitances.
AVDD
S(1)
IOUT1
RLOAD
S(1)C
IOUT2
S(2)
S(2)C
S(N)
S(N)C
Current Source Array
RLOAD
Figure 19. Analog Outputs
The signal voltage swing that may develop at the two outputs, IOUT1 and IOUT2, is limited by a negative and
positive compliance. The negative limit of –1 V is given by the breakdown voltage of the CMOS process and
exceeding it compromises the reliability of the DAC5672A (or even causes permanent damage). With the fullscale output set to 20 mA, the positive compliance equals 1.2 V. Note that the compliance range decreases to
about 1 V for a selected output current of IOUTFS = 2 mA. Care must be taken that the configuration of DAC5672A
does not exceed the compliance range to avoid degradation of the distortion performance and integral linearity.
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Device Functional Modes (continued)
Best distortion performance is typically achieved with the maximum full-scale output signal limited to
approximately 0.5 VPP. This is the case for a 50-Ω doubly-terminated load and a 20-mA full-scale output current.
A variety of loads can be adapted to the output of the DAC5672A by selecting a suitable transformer while
maintaining optimum voltage levels at IOUT1 and IOUT2. Furthermore, using the differential output configuration
in combination with a transformer is instrumental for achieving excellent distortion performance. Common-mode
errors, such as even-order harmonics or noise, can be substantially reduced. This is particularly the case with
high output frequencies.
For those applications requiring the optimum distortion and noise performance, it is recommended to select a fullscale output of 20 mA. A lower full-scale range of 2 mA may be considered for applications that require low
power consumption, but can tolerate a slight reduction in performance level.
7.4.3 Output Configurations
The current outputs of the DAC5672A allow for a variety of configurations. As mentioned previously, utilizing the
converter’s differential outputs yield the best dynamic performance. Such a differential output circuit may consist
of an RF transformer or a differential amplifier configuration. The transformer configuration is ideal for most
applications with ac coupling, while op amps are suitable for a dc-coupled configuration.
The single-ended configuration may be considered for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs to ground converts the output current into a groundreferenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an I-to-V or op-amp
configuration may be considered.
7.4.4 Differential With Transformer
Using an RF transformer provides a convenient way of converting the differential output signal into a singleended signal while achieving excellent dynamic performance. The appropriate transformer must be carefully
selected based on the output frequency spectrum and impedance requirements.
The differential transformer configuration has the benefit of significantly reducing common-mode signals, thus
improving the dynamic performance over a wide range of frequencies. Furthermore, by selecting a suitable
impedance ratio (winding ratio) the transformer can provide optimum impedance matching while controlling the
compliance voltage for the converter outputs.
Figure 20 and Figure 21 show 50-Ω doubly-terminated transformer configurations with 1:1 and 4:1 impedance
ratios, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable
a dc-current flow. Applying a 20-mA full-scale output current would lead to a 0.5-VPP output for a 1:1 transformer
and a 1-VPP output for a 4:1 transformer. In general, the 1:1 transformer configuration will have slightly better
output distortion, but the 4:1 transformer will have 6 dB higher output power.
50 Ω
1:1
IOUT1
100 Ω
AGND
RLOAD
50 Ω
IOUT2
50 Ω
Figure 20. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
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Device Functional Modes (continued)
100 Ω
4:1
IOUT1
RLOAD
50 Ω
AGND
IOUT2
100 Ω
Figure 21. Driving a Doubly-Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
7.4.5 Single-Ended Configuration
Figure 22 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent
load resistance of 25 Ω. Node IOUT2 must be connected to AGND or terminated with a resistor of 25 Ω to
AGND. The nominal resistor load of 25 Ω gives a differential output swing of 1 VPP when applying a 20-mA fullscale output current.
IOUT1
RLOAD
50 Ω
IOUT2
50 Ω
25 Ω
AGND
Figure 22. Driving a Doubly-Terminated 50-Ω Cable Using a Single-Ended Output
7.4.6 Reference Operation
7.4.6.1 Internal Reference
The DAC5672A has an on-chip reference circuit which comprises a 1.2-V bandgap reference and two control
amplifiers, one for each DAC. The full-scale output current, IOUTFS, of the DAC5672A is determined by the
reference voltage, VREF, and the value of resistor RSET. IOUTFS can be calculated by:
V
IOUTFS 32 u IREF 32 u REF
RSET
(9)
The reference control amplifier operates as a V-to-I converter producing a reference current, IREF, which is
determined by the ratio of VREF and RSET (see Equation 9). The full-scale output current, IOUTFS, results from
multiplying IREF by a fixed factor of 32.
Using the internal reference, a 2-kΩ resistor value results in a full-scale output of approximately 20 mA. Resistors
with a tolerance of 1% or better should be considered. Selecting higher values, the output current can be
adjusted from 20 mA down to 2 mA. Operating the DAC5672A at lower than 20-mA output currents may be
desirable for reasons of reducing the total power consumption, improving the distortion performance, or
observing the output compliance voltage limitations for a given load condition.
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Device Functional Modes (continued)
It is recommended to bypass the EXTIO pin with a ceramic chip capacitor of 0.1 μF or more. The control
amplifier is internally compensated and its small signal bandwidth is approximately 300 kHz.
7.4.6.2 External Reference
The internal reference can be disabled by simply applying an external reference voltage into the EXTIO pin,
which in this case functions as an input. The use of an external reference may be considered for applications that
require higher accuracy and drift performance or to add the ability of dynamic gain control.
While a 0.1-μF capacitor is recommended to be used with the internal reference, it is optional for the external
reference operation. The reference input, EXTIO, has a high input impedance (1 MΩ) and can easily be driven by
various sources. Note that the voltage range of the external reference must stay within the compliance range of
the reference input.
7.4.6.3 Gain Setting Option
The full-scale output current on the DAC5672A can be set two ways: either for each of the two DAC channels
independently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42)
must be low (that is, connected to AGND). In this mode, two external resistors are required — one RSET
connected to the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41). In this configuration, the user
has the flexibility to set and adjust the full-scale output current for each DAC independently, allowing for the
compensation of possible gain mismatches elsewhere within the transmit signal path.
Alternatively, bringing the GSET pin high (that is, connected to AVDD), the DAC5672A switches into the
simultaneous gain set mode. Now the full-scale output current of both DAC channels is determined by only one
external RSET resistor connected to the BIASJ_A pin. The resistor at the BIASJ_B pin may be removed; however,
this is not required since this pin is not functional in this mode and the resistor has no effect on the gain equation.
7.4.6.4 Sleep Mode
The DAC5672A features a power-down function which can reduce the total supply current to approximately 3.1
mA over the specified supply range if no clock is present. Applying a logic high to the SLEEP pin initiates the
power-down mode, while a logic low enables normal operation. When left unconnected, an internal active
pulldown circuit enables the normal operation of the converter.
7.5 Programming
7.5.1 Digital Inputs and Timing
7.5.1.1 Digital Inputs
The data input ports of the DAC5672A accept a standard positive coding with data bits DA13 and DB13 being
the most significant bits (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best
performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may
vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their
specified limits.
All digital inputs of the DAC5672A are CMOS compatible. Figure 23 and Figure 24 show schematics of the
equivalent CMOS digital inputs of the DAC5672A. The pullup and pulldown circuitry is approximately equivalent
to 100 kΩ. The 14-bit digital data input follows the offset positive binary coding scheme. The DAC5672A is
designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.
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Programming (continued)
DVDD
DA[13:0]
DB[13:0]
SLEEP
CLKA/B
WRTA/B
400W
Internal
Digital In
100kW
DGND
Figure 23. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
DVDD
100kW
GSET
MODE
400W
Internal
Digital In
DGND
Figure 24. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application
A typical application for the DAC5672A is as dual or single carrier transmitter. The DAC is provided with some
input digital baseband signal and it outputs an analog carrier. A typical configuration is described below.
WRT B
WRT A
CLK B
CLK A
50
DE-MUX
LATCH A
14-b DAC
1:1
Output
50
100
DA[13:0]
50
50
DB[13:0]
LATCH A
14-b DAC
1:1
Output
50
100
50
EXTIO
1.2 V Reference
0.1 …F
Figure 25. Typical Application Schematic
•
•
•
Clock rate = 122.88 MHz
Input data = WCDMA with IF frequency at 30.72 MHz
AVDD= DVDD = 3.3 V
8.2.1 Design Requirements
The requirements for this design were to generate a single WCDMA signal at an intermediate frequency of 30.72
MHz. The ACLR needs to be better than 72 dBc.
8.2.2 Detailed Design Procedure
The single carrier signal with an intermediate frequency of 30.72 MHz must be created in the digital processor at
a sample rate of 122.88 Msps for DAC. These 14 bit samples are placed on the 14b CMOS input port of the
DAC.
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Typical Application (continued)
A CMOS DAC clock must be generated from a clock source at 122.88 MHz. This must be provided to the CLK
pin of the DAC.
The IOUTA and IOUTB differential connections must be connected to a transformer to provide a single ended
output. A typical 1:1 impedance transformer is used on the device EVM. The DAC5672A EVM provides a good
reference for this design example.
8.2.3 Application Curves
This spectrum analyzer plot shows the ACLR for the transformer output single carrier signal with intermediate
frequency of 30.72 MHz. The results meet the system requirements for a minimum of 72 dBc ACLR.
−20
Power − dBm
−40
fdata = 122.88 MSPS
IF = 30.72 MHz
ACLR = 72.7 dB
Dual Bus Mode
−60
−80
−100
−120
23.0
25.5
28.0
30.5
33.0
35.5
38.0
f − Frequency − MHz
G016
Figure 26. TBD
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9 Power Supply Recommendations
It is recommended that the device be powered with the nominal supply voltages as indicated in the
Recommended Operating Conditions.
In most instances the best performance is achieved with LDO supplies. However the supplies may be driven with
direct outputs from a DC-DC switcher as long as the noise performance of the switcher is acceptable.
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10 Layout
10.1 Layout Guidelines
The DAC5672A EVM layout should be used as a reference for the layout to obtain the best performance. A
sample layout is shown in Figure 27 through Figure 30. Some important layout recommendations are:
1. Use a single ground plane. Keep the digital and analog signals on distinct separate sections of the board.
This may be virtually divided down the middle of the device package when doing placement and layout.
2. Keep the analog outputs as far away from the switching clocks and digital signals as possible. This will keep
coupling from the digital circuits to the analog outputs to a minimum.
3. Decoupling caps should be kept close to the power pins of the device.
10.2 Layout Example
The EVM is constructed on a 4-layer, 5.1-inch x 4.8-inch, 0.062-inch thick PCB using FR−4 material. Figure 27
through Figure 30 show the PCB layout for the EVM.
Figure 27. Top Layer 1
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Layout Example (continued)
Figure 28. Ground Plane Layer 2
26
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Layout Example (continued)
Figure 29. Power Plane Layer 3
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Layout Example (continued)
Figure 30. Bottom Layer 4
28
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC5672AIPFB
ACTIVE
TQFP
PFB
48
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC5672AI
DAC5672AIPFBG4
ACTIVE
TQFP
PFB
48
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC5672AI
DAC5672AIPFBR
ACTIVE
TQFP
PFB
48
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC5672AI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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