DAC5675-EP
www.ti.com
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
14-Bit 400-MSPS Digital-to-Analog Converter
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
400-MSPS Update Rate
Controlled Baseline
– One Assembly
– One Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
LVDS-Compatible Input Interface
Spurious-Free Dynamic Range (SFDR) to
Nyquist
– 69 dBc at 70 MHz IF, 400 MSPS
W-CDMA Adjacent Channel Power Ratio
(ACPR)
– 73 dBc at 30.72-MHz IF, 122.88 MSPS
– 71 dBc at 61.44-MHz IF, 245.76 MSPS
Differential Scalable Current Outputs: 2 mA
to 20 mA
On-Chip 1.2-V Reference
Single 3.3-V Supply Operation
Power Dissipation: 660 mW at
fCLK = 400 MSPS, fOUT = 20 MHz
Package: 48-Pin PowerPAD™
Thermally-Enhanced Thin Quad Flat Pack
(HTQFP) TJA = 29.1°C/W
APPLICATIONS
•
•
•
Cellular Base Transceiver Station Transmit
Channel:
– CDMA: WCDMA, CDMA2000, IS-95
– TDMA: GSM, IS-136, EDGE/GPRS
– Supports Single-Carrier and Multicarrier
Applications
Test and Measurement: Arbitrary Waveform
Generation
Military Communications
DESCRIPTION/ORDERING INFORMATION
The DAC5675 is a 14-bit resolution high-speed digital-to-analog converter (DAC). The DAC5675 is designed for
high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital
synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675 has
excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes it well-suited for
multicarrier transmission in TDMA- and CDMA-based cellular base transceiver stations (BTSs).
The DAC5675 operates from a single-supply voltage of 3.3 V. Power dissipation is 660 mW at
fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675 provides a nominal full-scale differential current output of 20
mA, supporting both single-ended and differential applications. The output current can be directly fed to the load
with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.
The DAC5675 comprises a low-voltage differential signaling (LVDS) interface for high-speed digital data input.
LVDS features a low differential voltage swing with a low constant power consumption across frequency,
allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference
(EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for
high-speed interfacing between the DAC5675 and high-speed low-voltage CMOS ASICs or FPGAs. The
DAC5675 current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered
input latches provide for minimum setup and hold times, thereby relaxing interface timing.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
DAC5675-EP
www.ti.com
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
The DAC5675 has been specifically designed for a differential transformer-coupled output with a 50-Ω
doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an
output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is
preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to
AVDD and have voltage compliance ranges from AVDD – 1 to AVDD + 0.3 V.
An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to
adjust this output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities.
Alternatively, an external reference voltage may be applied. The DAC5675 features a SLEEP mode, which
reduces the standby power to approximately 18 mW.
The DAC5675 is available in a 48-pin PowerPAD™ thermally-enhanced thin quad flat pack (HTQFP). This
package increases thermal efficiency in a standard size IC package. The device is specified for operation over
the military temperature range of –55°C to 125°C.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
DAC5675-EP
48 HTQFP
PHP
DAC5675-EP
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
DAC5675MPHPREP
Tape and reel, 1000
DAC5675MPHPEP
Tray, 250
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
TQFP-48 PACKAGE THERMAL CHARACTERISTICS
PARAMETER
PowerPAD
CONNECTED TO
PCB THERMAL PLANE (1)
RθJA
Thermal resistance, junction to ambient (1) (2)
108.71°C/W
29.11°C/W
RθJC
Thermal resistance, junction to case (1) (2)
18.18°C/W
1.14°C/W
(1)
(2)
2
SAME PACKAGE
FORM WITHOUT
PowerPAD
Airflow is at 0 LFM (no airflow).
Specified with the PowerPAD bond pad on the backside of the package soldered to a 2-oz CU plate PCB thermal plane
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DAC5675-EP
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
FUNCTIONAL BLOCK DIAGRAM
SLEEP
DAC5675-EP
Bandgap
Reference
1.2V
EXTIO
BIASJ
Current
Source
Array
Output
Current
Switches
Decoder
DAC
Latch
+
Drivers
Control Amp
14
D[13:0]A
LVDS
Input
Interface
D[13:0]B
Input
Latches
14
CLK
Clock Distribution
CLKC
AVDD(4x) AGND(4x)
DVDD(2x) DGND(2x)
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
DAC5675-EP
Supply voltage range
AVDD (2)
–0.3 to 3.6
DVDD (3)
–0.3 to 3.6
AVDD to DVDD
–3.6 to 3.6
Voltage between AGND and DGND
CLK, CLKC (2)
Digital input D[13:0]A,
D[13:0]B (3),
SLEEP, DLLOFF
V
–0.3 to 0.5
V
–0.3 to AVDD + 0.3
V
–0.3 to DVDD + 0.3
V
IOUT1, IOUT2 (2)
–1 to AVDD + 0.3
V
EXTIO, BIASJ (2)
–1 to AVDD + 0.3
V
Peak input current (any input)
20
mA
Peak total input current (all inputs)
–30
mA
Operating free-air temperature range, TA
–55 to 125
°C
Storage temperature range
–65 to 150
°C
260
°C
Lead temperature 1,6 mm (1/16 in) from the case for 10 s
(1)
(2)
(3)
4
UNIT
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to AGND
Measured with respect to DGND
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
DC Electrical Characteristics
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
14
UNIT
Bit
DC Accuracy (1)
INL
Integral nonlinearity
DNL
Differential nonlinearity
–4
±1.5
4.6
LSB
–2
±0.6
2.2
LSB
2
20
mA
AVDD – 1
AVDD + 0.3
TMIN to TMAX
Monotonicity
Monotonic 12b Level
Analog Output
IO(FS)
Full-scale output current
Output compliance range
AVDD = 3.15 V to 3.45 V,
IO(FS) = 20 mA
Offset error
0.01
Gain error
%FSR
Without internal reference
–10
5
10
With internal reference
–10
2.5
10
Output resistance
Output capacitance
V
%FSR
300
kΩ
5
pF
Reference Output
V(EXTIO)
Reference voltage
Reference output
1.17
current (2)
1.23
1.29
100
V
nA
Reference Input
V(EXTIO)
Input reference voltage
0.6
Input resistance
1.2
1.25
V
1
MΩ
Small-signal bandwidth
1.4
MHz
Input capacitance
100
pF
12
ppm of FSR/°C
±50
ppm/°C
Temperature Coefficients
Offset drift
∆V(EXTIO)
Reference voltage drift
Power Supply
AVDD
Analog supply voltage
3.15
3.3
3.6
DVDD
Digital supply voltage
3.15
3.3
3.6
I(AVDD)
Analog supply current (3)
I(DVDD)
Digital supply current (3)
PD
Power dissipation
APSRR
Analog and digital
power-supply rejection ratio
DPSRR
(1)
(2)
(3)
Sleep mode
AVDD = 3.15 V to 3.45 V
V
115
mA
85
mA
18
AVDD = 3.3 V, DVDD = 3.3 V
V
660
900
–0.9
±0.1
0.9
–0.9
±0.1
0.9
mW
%FSR/V
Measured differential at IOUT1 and IOUT2: 25 Ω to AVDD
Use an external buffer amplifier with high impedance input to drive any external load.
Measured at fCLK = 400 MSPS and fOUT = 70 MHz
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DAC5675-EP
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
AC Electrical Characteristics
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA, differential
transformer-coupled output, 50-Ω doubly-terminated load (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
400
MSPS
Analog Output
fCLK
Output update rate
ts(DAC)
Output setting time to 0.1%
tPD
tr(IOUT)
tf(IOUT)
12
ns
Output propagation delay
1
ns
Output rise time, 10% to 90%
2
ns
Output fall time, 90% to 10%
2
ns
Output noise
Transition: code x2000 to x23FF
IOUTFS = 20 mA
55
IOUTFS = 2 mA
30
pA/√Hz
AC Linearity
THD
fCLK = 100 MSPS,
fOUT = 19.9 MHz
73
fCLK = 160 MSPS,
fOUT = 41 MHz
72
fCLK = 200 MSPS,
fOUT = 70 MHz
68
fOUT = 20.1 MHz
72
fOUT = 70 MHz
71
fOUT = 140 MHz
58
fCLK = 100 MSPS,
fOUT = 19.9 MHz
73
fCLK = 160 MSPS,
fOUT = 41 MHz
73
fCLK = 200 MSPS,
fOUT = 70 MHz
70
fOUT = 20.1 MHz
73
fOUT = 70 MHz
74
fOUT = 140 MHz
60
fCLK = 100 MSPS,
fOUT = 19.9 MHz
88
fCLK = 160 MSPS,
fOUT = 41 MHz
87
Spurious-free dynamic range fCLK = 200 MSPS,
within a window, 5-MHz span
fOUT = 70 MHz
82
fOUT = 20.1 MHz
87
fCLK = 400 MSPS
fOUT = 70 MHz
82
fOUT = 140 MHz
75
Total harmonic distortion
fCLK = 400 MSPS
SFDR
Spurious-free dynamic range
to Nyquist
fCLK = 400 MSPS
SFDR
fCLK = 122.88 MSPS, IF = 30.72 MHz, See Figure 9
ACPR
IMD
6
Adjacent channel power ratio
WCDM A with 3.84 MHz BW, fCLK = 245.76 MSPS, IF = 61.44 MHz, See Figure 10
5-MHz channel spacing
fCLK = 399.32 MSPS, IF = 153.36 MHz, See Figure 12
Two-tone intermodulation
to Nyquist (each tone at
–6 dBfs)
71
dBc
dB
65
73
fCLK = 400 MSPS, fOUT1 = 140 MHz, fOUT2 = 141 MHz
62
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dBc
73
fCLK = 400 MSPS, fOUT1 = 70 MHz, fOUT2 = 71 MHz
Four-tone intermodulation,
fCLK = 156 MSPS, fOUT = 15.6, 15.8, 16.2, 16.4 MHz
15-MHz span, missing center
tone (each tone at –16 dBfs) fCLK = 400 MSPS, fOUT = 68.1, 69.3, 71.2, 72 MHz
dBc
82
74
dBc
DAC5675-EP
www.ti.com
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
Digital Specifications
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
LVDS Interface: Nodes D[13:0]A, D[13:0]B
VITH+
Positive-going differential input
voltage threshold
VITH–
Negative-going differential input
voltage threshold
ZT
Internal termination impedance
CI
Input capacitance
See LVDS Min/Max Threshold
Voltages table
90
100
mV
–100
mV
110
132
Ω
2
pF
3.3
V
CMOS Interface (SLEEP)
VIH
High-level input voltage
2
VIL
Low-level input voltage
0.8
V
IIH
High-level input current
–100
100
µA
IIL
Low-level input current
–10
10
µA
0
Input capacitance
2
pF
Clock Interface (CLK, CLKC)
|CLK-CLKC|
Clock differential input voltage
0.4
tw(H)
Clock pulse width high
1.25
tw(L)
Clock pulse width low
1.25
Clock duty cycle
VCM
0.8
40%
ns
ns
60%
2 ± 20%
Common-mode voltage range
VPP
V
Input resistance
Node CLK, CLKC
670
Ω
Input capacitance
Node CLK, CLKC
2
pF
Input resistance
Differential
1.3
kΩ
Input capacitance
Differential
1
pF
Timing
tSU
Input setup time
1.5
ns
tH
Input hold time
0.25
ns
tLPH
Input latch pulse high time
tDD
Digital delay time
DLL disabled, DLLOFF = 1
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2
ns
3
clk
7
DAC5675-EP
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
Timing Information
D[13:0]A
Valid Data
D[13:0]B
tH
tSU
tDD
CLK
50%
50%
CLKC
tW (LPH)
tPD
tS(DAC)
0.1%
DAC Output
IOUT1/IOUT2
50%
90%
10%
0.1%
t r(IOUT)
Figure 1. Timing Diagram
Electrical Characteristics (1)
over operating free-air temperature range, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless otherwise noted)
APPLIED
VOLTAGES
RESULTING
DIFFERENTIAL
INPUT VOLTAGE
RESULTING
COMMON-MODE
INPUT VOLTAGE
VA,B (mV)
VCOM (V)
LOGICAL BIT
BINARY
EQUIVALENT
VA (V)
VB (V)
1.25
1.15
100
1.2
1
1.15
1.25
–100
1.2
0
2.4
2.3
100
2.35
1
2.3
2.4
–100
2.35
0
(1)
0.1
0
100
0.05
1
0
0.1
–100
0.05
0
1.5
0.9
600
1.2
1
0.9
1.5
–600
1.2
0
2.4
1.8
600
2.1
1
1.8
2.4
–600
2.1
0
0.6
0
600
0.3
1
0
0.6
–600
0.3
0
COMMENT
Operation with minimum differential voltage
(±100 mV) applied to the complementary inputs
versus common-mode range
Operation with maximum differential voltage
(±600 mV) applied to the complementary inputs
versus common-mode range
Specifications subject to change.
DVDD
DAC5675-EP
VA
1.4 V
VB
1V
VA, B
VA, B
0.4 V
0V
− 0.4 V
VCOM =
VA + VB
2
VA
Logical Bit
Equivalent
VB
DGND
Figure 2. LVDS Timing Test Circuit and Input Test Levels
8
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
DEVICE INFORMATION
PHP PACKAGE
(TOP VIEW)
DAC5675
A.
Thermal pad size: 4,5mm × 4,5mm (min), 5,5mm × 5,5mm (max)
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DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
19, 41, 46, 47
I
Analog negative supply voltage (ground). Pin 47 is internally connected to the heat slug.
AVDD
20, 42, 45, 48
I
Analog positive supply voltage
BIASJ
39
O
Full-scale output current bias
CLK
22
I
External clock input
CLKC
21
I
Complementary external clock
D[13:0]A
1, 3, 5, 7, 9,
11, 13, 23, 25,
27, 29, 31, 33,
35
I
LVDS positive input, data bits 13–0.
D13A is the most significant data bit (MSB).
D0A is the least significant data bit (LSB).
D[13:0]B
2, 4, 6, 8, 10,
12, 14, 24, 26,
28, 30, 32, 34,
36
I
LVDS negative input, data bits 13–0..
D13B is the most significant data bit (MSB).
D0B is the least significant data bit (LSB).
DGND
16, 18
I
Digital negative supply voltage (ground)
DVDD
15, 17
I
Digital positive supply voltage
EXTIO
40
I/O
Internal reference output or external reference input. Requires a 0.1-µF decoupling capacitor to
AGND when used as reference output.
IOUT1
43
O
DAC current output. Full-scale when all input bits are set 1. Connect the reference side of the
DAC load resistors to AVDD.
IOUT2
44
O
DAC complementary current output. Full-scale when all input bits are 0. Connect the reference
side of the DAC load resistors to AVDD.
NC
38
SLEEP
37
10
Not connected in chip. Can be high or low.
I
Asynchronous hardware power-down input. Active high. Internal pulldown.
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TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY (DNL) vs INPUT CODE
INTEGRAL NONLINEARITY (INL) vs INPUT CODE
1.5
1.0
0.8
1.0
0.6
0.5
INL (LSB)
DNL (LSB)
0.4
0.2
0
−0.2
0
−0.5
−0.4
−0.6
−1.0
−0.8
−1.5
−1.0
0
2000
4000
6000
8000 10000 12000 14000 16000
0
2000
Input Code
Figure 4.
TWO-TONE IMD3 vs FREQUENCY
−30
Two-Tone IMD3 (dBc)
Power (dBFS)
−20
−40
−50
−60
−70
−80
−90
−100
65
67
69
71
73
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
75
f2 − f1 = 1 MHz (–6 dBFS each)
VCC = VAA = 3.3 V
fCLK = 200 MHz
5
15
25
35
Frequency (MHz)
−30
−40
−50
40.06 MHz
−60
−3 dBFS
82
85
78
74
−6 dBFS
70
0 dBFS
66
62
60.25 MHz
−70
58
−80
54
−90
75
VCC = VAA = 3.3 V
fCLK = 400 MHz
86
SFDR (dBFS)
Power (dBFS)
−20
65
SPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY
90
VCC = VAA = 3.3 V
fCLK = 400 MHz
fOUT = 20.1 MHz, 0 dBFS
SFDR = 74.75 dBc
20.1 MHz
55
Figure 6.
SINGLE-TONE SPECTRUM
POWER vs FREQUENCY
0
45
Center Frequency (MHz)
Figure 5.
−10
8000 10000 12000 14000 16000
Figure 3.
f1 = 69.5 MHz, −6 dBFS
f2 = 70.5 MHz, −6 dBFS
IMD3 = 77.41 dBc
VCC = VAA = 3.3 V
fCLK = 200 MHz
−10
6000
Input Code
TWO-TONE IMD (POWER) vs FREQUENCY
0
4000
50
0
20
40
60
80
100 120 140
160 180
200
10
20
Frequency (MHz)
30
40
50
60
70
80
90
100 110 120
Output Frequency (MHz)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
W-CDMA TM1 SINGLE CARRIER
POWER vs FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY
90
86
SFDR (dBFS)
78
74
−6 dBFS
70
0 dBFS
66
62
−45
−55
−65
−75
−85
58
−95
54
−105
50
10
20
30
40
50
60
70
80
90
VCC = VAA = 3.3 V
fCLK = 122.88 MHz
fCENTER = 30.72 MHz
ACLR = 72.29 dB
−35
Power (dBm/30kHz)
−3 dBFS
82
−25
VCC = VAA = 3.3 V
fCLK = 200 MHz
−115
100 110 120
23
18
28
Output Frequency (MHz)
−30
W-CDMA TM1 DUAL CARRIER
POWER vs FREQUENCY
W-CDMA TM1 SINGLE CARRIER
ACLR vs OUTPUT FREQUENCY
V CC = V AA = 3.3 V
43
Frequency
Figure 10.
80
fCLK = 368.64 MHz
VCC = VAA = 3.3 V
fCLK = 399.36 MHz
Single Channel
78
ACLR = 65 dBc
92.16 MHz
76
−50
74
ACLR (dBc)
Power (dBm/30kHz)
38
Figure 9.
−40 fCENTER =
−60
−70
−80
72
70
68
66
−90
64
−100
−110
82.2
62
60
87.2
92.2
97.2
10.2
10
30
50
70
90
110
Output Frequency (MHz)
Frequency
Figure 11.
12
33
Figure 12.
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130
150
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION
Detailed Description
Figure 13 shows a simplified block diagram of the current steering DAC5675. The DAC5675 consists of a
segmented array of NPN-transistor current sources, capable of delivering a full-scale output current up to
20 mA. Differential current switches direct the current of each current source to either one of the complementary
output nodes IOUT1 or IOUT2. The complementary current output enables differential operation, canceling out
common-mode noise sources (digital feedthrough, on-chip, and PCB noise), dc offsets, and even-order
distortion components, and doubling signal output power.
The full-scale output current is set using an external resistor (RBIAS) in combination with an on-chip bandgap
voltage reference source (1.2 V) and control amplifier. The current (IBIAS) through resistor RBIAS is mirrored
internally to provide a full-scale output current equal to 16 times IBIAS. The full-scale current is adjustable from
20 mA down to 2 mA by using the appropriate bias resistor value.
SLEEP
3.3 V
(AVDD)
DAC5675-EP
Bandgap
Reference
1.2 V
50 Ω
IOUT
Output
1:1
EXTIO
Current
Source
Array
BIASJ
CEXT
0.1 mF
Output
Current
Switches
Control Amp
RBIAS
1 kΩ
IOUT
50 Ω
RLOAD
50 Ω
3.3 V
(AVDD)
14
D[13:0]A
LVDS
Input
Interface
D[13:0]B
Input
Latches
Decoder
14
DAC
Latch
+
Drivers
3.3 V
(AVDD)
CLK
1:4
Clock
Input
100 Ω
RT
200 Ω
Clock Distribution
CLKC
AVDD(4x)
AGND(4x)
DVDD(2x)
DGND(2x)
Figure 13. Application Schematic
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APPLICATION INFORMATION (continued)
Digital Inputs
The DAC5675 uses a low-voltage differential signaling (LVDS) bus input interface. The LVDS features a low
differential voltage swing with low constant power consumption (4 mA per complementary data input) across
frequency. The differential characteristic of LVDS allows for high-speed data transmission with low
electromagnetic interference (EMI) levels. The LVDS input minimum and maximum input threshold table lists the
LVDS input levels. Figure 14 shows the equivalent complementary digital input interface for the DAC5675, valid
for pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110-Ω resistors for proper
termination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A common-mode level
of 1.2 V and a differential input swing of 0.8 VPP is applied to the inputs.
Figure 15 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675, valid for
the SLEEP pin.
DVDD
DAC5675-EP
D[13..0]A
DAC5675-EP
110-Ω
Termination
Resistor
Internal
Digital In
D[13..0]B
D[13:0]A
D[13:0]B
Internal
Digital In
DGND
Figure 14. LVDS Digital Equivalent Input
DVDD
DAC5675-EP
Internal
Digital In
Digital Input
DGND
Figure 15. CMOS/TTL Digital Equivalent Input
Clock Input
The DAC5675 features differential LVPECL-compatible clock inputs (CLK, CLKC). Figure 16 shows the
equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltage
to approximately 2 V, while the input resistance is typically 670 Ω. A variety of clock sources can be ac-coupled
to the device, including a sine-wave source (see Figure 17).
14
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
AVDD
DAC5675-EP
R1
1 kΩ
R1
1 kΩ
Internal
Clock
CLK
CLKC
R2
2 kΩ
R2
2 kΩ
AGND
Figure 16. Clock Equivalent Input
Optional, may be
bypassed for sinewave input
Swing Limitation
CAC
0.1 mF
1:4
CLK
RT
200 Ω
DAC5675-EP
CLKC
Termination
Resistor
Figure 17. Driving the DAC5675 With a Single-Ended Clock Source Using a Transformer
To obtain best ac performance, the DAC5675 clock input should be driven with a differential LVPECL or
sine-wave source as shown in Figure 18 and Figure 19. Here, the potential of VTT should be set to the
termination voltage required by the driver along with the proper termination resistors (RT). The DAC5675 clock
input can also be driven single ended; this is shown in Figure 20.
Single-Ended
ECL
or
(LV)PECL
Source
CAC
0.01 mF
ECL/PECL
Gate
CLK
CAC
0.01 mF
DAC5675-EP
CLKC
RT
50 Ω
RT
50 Ω
VTT
Figure 18. Driving the DAC5675 With a Single-Ended ECL/PECL Clock Source
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DAC5675-EP
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
CAC
0.01 mF
Differential
ECL
or
(LV)PECL
Source
CLK
+
CAC
0.01 mF
DAC5675-EP
−
RT
50 Ω
CLKC
RT
50 Ω
VTT
Figure 19. Driving the DAC5675 With a Differential ECL/PECL Clock Source
TTL/CMOS
Source
CLK
ROPT
22 Ω
DAC5675-EP
CLKC
0.01 mF
Node CLKC
Internally Biased to
AVDD/2
Figure 20. Driving the DAC5675 With a Single-Ended TTL/CMOS Clock Source
Supply Inputs
The DAC5675 comprises separate analog and digital supplies, that is AVDD and DVDD, respectively. These
supply inputs can be set independently from 3.6 V down to 3.15 V.
DAC Transfer Function
The DAC5675 delivers complementary output currents IOUT1 and IOUT2. The DAC supports straight binary
coding, with D13 being the MSB and D0 the LSB. (For ease of notation, we denote D13–D0 as the logical bit
equivalent of the complementary LVDS inputs D[13:0]A and D[13:0]B). Output current IOUT1 equals the
approximate full-scale output current when all input bits are set high, when the binary input word has the decimal
representation 16383. Full-scale output current flows through terminal IOUT2 when all input bits are set low
(mode 0, straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as:
IOUT1 + IO (FS)*IOUT2
(1)
where IO(FS) is the full-scale output current. The output currents can be expressed as:
IOUT1 +
IOUT2 +
IO (FS)
CODE
16384
IO (FS)
(2)
(16383*CODE)
16384
(3)
where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive
a load RL. RL is the combined impedance for the termination resistance and/or transformer load resistance,
RLOAD (see Figure 22 and Figure 23). This would translate into single-ended voltages VOUT1 and VOUT2 at
terminal IOUT1 and IOUT2, respectively, of Equation 4 and Equation 5:
16
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APPLICATION INFORMATION (continued)
VOUT1 + IOUT1
VOUT2 + IOUT2
RL +
ǒCODE
I O(FS)
R LǓ
16384
(16383*CODE) I O(FS)
RL +
16384
(4)
RL
Thus, the differential output voltage VOUT(DIFF) can be expressed as:
(2CODE * 16383) I O(FS) RL
VOUT (DIFF) + VOUT1*VOUT2 +
16384
(5)
(6)
Equation 6 shows that applying the differential output results in doubling the signal power delivered to the load.
Since the output currents IOUT1 and IOUT2 are complementary, they become additive when processed
differentially. Care should be taken not to exceed the compliance voltages at nodes IOUT1 and IOUT2, which
leads to increased signal distortion.
Reference Operation
The DAC5675 has a bandgap reference and control amplifier for biasing the full-scale output current. The
full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS
is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals
16 times this bias current. The full-scale output current IO(FS) is thus expressed as Equation 7:
16 V EXTIO
I O(FS) + 16 I BIAS +
RBIAS
(7)
where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers a stable voltage of 1.2 V.
This reference can be overridden by applying an external voltage to terminal EXTIO. The bandgap reference
can additionally be used for external reference operation. In such a case, an external buffer amplifier with high
impedance input should be selected in order to limit the bandgap load current to less than 100 nA. The capacitor
CEXT may be omitted. Terminal EXTIO serves as either an input or output node. The full-scale output current is
adjustable from 20 mA down to 2 mA by varying resistor RBIAS.
Analog Current Outputs
Figure 21 shows a simplified schematic of the current source array output with corresponding switches.
Differential NPN switches direct the current of each individual NPN current source to either the positive output
node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the
stack of the current sources and differential switches and is >300 kΩ in parallel with an output capacitance
of 5 pF.
The external output resistors are referred to the positive supply AVDD.
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APPLICATION INFORMATION (continued)
3.3 V
AVDD
RLOAD
RLOAD
IOUT1
IOUT2
DAC5675-EP
S(1)
S(1)C
S(2)
S(2)C S(N)
S(N)C
Current Sink Array
AGND
Figure 21. Equivalent Analog Current Output
The DAC5675 can easily be configured to drive a doubly-terminated 50-Ω cable using a properly selected
transformer. Figure 22 and Figure 23 show the 1:1 and 4:1 impedance ratio configuration, respectively. These
configurations provide maximum rejection of common-mode noise sources and even-order distortion
components, thereby doubling the power of the DAC to the output. The center tap on the primary side of the
transformer is terminated to AVDD, enabling a dc-current flow for both IOUT1 and IOUT2. Note that the ac
performance of the DAC5675 is optimum and specified using a 1:1 differential transformer-coupled output.
3.3 V
AVDD
50 Ω
1:1
IOUT1
DAC5675-EP
100 Ω
RLOAD
50 Ω
IOUT2
50 Ω
3.3 V
AVDD
Figure 22. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
18
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
3.3 V
AVDD
100 Ω
4:1
IOUT1
RLOAD
50 Ω
DAC5675-EP
IOUT2
15 Ω
100 Ω
3.3 V
AVDD
Figure 23. Driving a Doubly-Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
Figure 24(a) shows the typical differential output configuration with two external matched resistor loads. The
nominal resistor load of 25 Ω gives a differential output swing of 1 VPP (0.5 VPP single ended) when applying a
20-mA full-scale output current. The output impedance of the DAC5675 slightly depends on the output voltage at
nodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, the configuration of Figure 24(b)
should be chosen. In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AVDD by the inverting
operational amplifier. The complementary output should be connected to AVDD to provide a dc-current path for
the current sources switched to IOUT1. The amplifier maximum output swing and the full-scale output current of
the DAC determine the value of the feedback resistor RFB. The capacitor CFB filters the steep edges of the
DAC5675 current output, thereby reducing the operational amplifier slew-rate requirements. In this configuration,
the operational amplifier should operate at a supply voltage higher than the resistor output reference voltage
AVDD as a result of its positive and negative output swing around AVDD. Node IOUT1 should be selected if a
single-ended unipolar output is desired.
3.3 V
AVDD
DAC5675-EP
CFB
25 Ω
IOUT1
VOUT1
IOUT2
VOUT2
25 Ω
3.3 V
AVDD
200 Ω (RFB)
DAC5675-EP
IOUT1
VOUT
IOUT2
Optional, for singleended output
referred to AVDD
(a)
3.3 V
AVDD
(b)
Figure 24. Output Configurations
Sleep Mode
The DAC5675 features a power-down mode that turns off the output current and reduces the supply current to
approximately 6 mA. The power-down mode is activated by applying a logic level one to the SLEEP pin, pulled
down internally.
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SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
DEFINITIONS
Definitions of Specifications and Terminology
Gain error is defined as the percentage error in the ratio between the measured full-scale output current and
the value of 16 × V(EXTIO)/RBIAS. A V(EXTIO) of 1.25 V is used to measure the gain error with an external reference
voltage applied. With an internal reference, this error includes the deviation of V(EXTIO) (internal bandgap
reference voltage) from the typical value of 1.25 V.
Offset error is defined as the percentage error in the ratio of the differential output current (IOUT1-IOUT2) and
the half of the full-scale output current for input code 8192.
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental output
signal.
SNR is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral
components below the Nyquist frequency, including noise, but excluding the first six harmonics and dc.
SINAD is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral
components below the Nyquist frequency, including noise and harmonics, but excluding dc.
ACPR or adjacent channel power ratio is defined for a 3.84-Mcps 3GPP W-CDMA input signal measured in a
3.84-MHz bandwidth at a 5-MHz offset from the carrier with a 12-dB peak-to-average ratio.
APSSR or analog power supply ratio is the percentage variation of full-scale output current versus a 5%
variation of the analog power supply AVDD from the nominal. This is a dc measurement.
DPSSR or digital power supply ratio is the percentage variation of full-scale output current versus a 5% variation
of the digital power supply DVDD from the nominal. This is a dc measurement.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DAC5675MPHPEP
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
DC5675MEP
DAC5675MPHPREP
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
DC5675MEP
V62/05619-01XE
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
DC5675MEP
V62/05619-02XE
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
DC5675MEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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