Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
DACx0504 Quad, 16-, 14-, 12-bit, SPI voltage output DACs with internal reference
1 Features
3 Description
•
The DAC80504, DAC70504, and DAC60504
(DACx0504) are a pin-compatible family of lowpower, four-channel, buffered voltage-output, digitalto-analog converters (DACs) with 16-, 14-, and 12-bit
resolution. The DACx0504 includes a low drift, 2.5-V
internal reference, eliminating the need for an
external precision reference in most applications. A
user-selectable gain configuration provides full-scale
output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1),
or 5 V (gain = 2). These devices operate from a
single 2.7-V to 5.5-V supply, are specified monotonic,
and provide high linearity of ±1 LSB INL.
1
•
•
•
•
•
•
•
Performance
– INL: ±1 LSB Maximum at 16-Bit Resolution
– TUE: ±0.1% of FSR Maximum
Integrated 2.5 V Precision Internal Reference
– Initial Accuracy: ±5 mV, Maximum
– Low Drift: 2 ppm/°C Typical
High Drive Capability: 20 mA With 0.5 V From
Supply Rails
Flexible Output Configuration
– User Selectable Gain: 2, 1 or ½
– Reset to Zero Scale or Midscale
Wide Operating Range
– Power Supply: 2.7 V to 5.5 V
– Temperature: –40˚C to +125˚C
50-MHz, SPI-Compatible Serial Interface
– 4-Wire Mode, 1.7 V to 5.5 V Operation
– Daisy-Chain Operation
– CRC Error Check
Low Power: 0.7 mA/Channel at 5.5 V
Small Package: 3-mm × 3-mm, 16-Pin WQFN
Communication to the DACx0504 is performed
through a 4-wire serial interface that operates at clock
rates of up to 50 MHz. The VIO pin enables serial
interface operation from 1.7 V to 5.5 V. The
DACx0504 flexible interface enables operation with a
wide range of industry-standard microprocessors and
microcontrollers.
The DACx0504 incorporate a power-on-reset circuit
that powers up and maintains the DAC outputs at
either zero scale or midscale until a valid code is
written to the device. These device consume a low
current of 0.7 mA/channel at 5.5 V, making these
devices an excellent choice for battery-operated
equipment. A per-channel power-down feature
reduces the device current consumption to 15 µA.
2 Applications
•
•
•
•
Optical Networking
Wireless Infrastructure
Industrial Automation
Data Acquisition Systems
The DACx0504 is characterized for operation over
the temperature range of –40°C to +125°C, and is
available in a small, 3-mm × 3-mm QFN package.
Device Information(1)
PART NUMBER
DACx0504
PACKAGE
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Block Diagram
VIO
VDD
REFDIV
REF
GAIN
Internal
Reference
DACx0504
÷1 or ÷2
GAIN
×1 or ×2
SCLK
DAC
Buffer
CS
LDAC
Interface Logic
SDI
SDO/ALARM
DAC
Register
DAC
OUT0
BUF
Channel 0
Channel 1
OUT1
Channel 2
OUT2
Channel 3
OUT3
Power On Reset
RSTSEL
Power Down Logic
Resistive Network
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
1
1
1
2
4
5
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 10
Detailed Description ............................................ 20
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
21
25
8.5 Programming........................................................... 28
8.6 Register Map........................................................... 30
9
Application and Implementation ........................ 36
9.1 Application Information............................................ 36
9.2 Typical Application .................................................. 38
10 Power Supply Recommendations ..................... 40
11 Layout................................................................... 40
11.1 Layout Guidelines ................................................. 40
11.2 Layout Example .................................................... 40
12 Device and Documentation Support ................. 41
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
41
41
41
41
41
13 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2018) to Revision C
Page
•
Added DAC60504 device to data sheet ................................................................................................................................ 1
•
Changed TUE values for DAC70504 in Electrical Characteristics ......................................................................................... 7
•
Changed Full-scale error values for DAC70504 in Electrical Characteristics ........................................................................ 7
•
Changed Gain error values for DAC70504 in Electrical Characteristics ................................................................................ 7
•
Changed channel-to-channel dc crosstalk values for DAC70504 in Electrical Characteristics.............................................. 8
•
Changed reference output drift values for DAC70504 in Electrical Characteristics ............................................................... 9
•
Changed reference thermal hysteresis values for DAC70504 in Electrical Characteristics................................................... 9
•
Deleted Figure 58, DAC70504 Solder Heat Reflow Reference Voltage Shift ...................................................................... 23
•
Changed reset value for VERSIONID from 10 to 11 in Table 10, DEVICE ID Field Descriptions ...................................... 31
Changes from Revision A (December 2017) to Revision B
Page
•
Changed TUE in Features from ±0.14% to ±0.1% ................................................................................................................. 1
•
Changed Low Drift in Features from 5 ppm/°C to 2 ppm/°C and added DAC80504 ............................................................. 1
•
Deleted Product Preview for DAC80504 from Device Information ........................................................................................ 1
•
Deleted Product Preview for DAC80504 from Device Comparison Table ............................................................................ 4
•
Added Added TUE DAC80504. All Gains row in Electrical Characteristics .......................................................................... 7
•
Added Added Full-scale error DAC80504. All Gains row in Electrical Characteristics ......................................................... 7
•
Added Added Gain error DAC80504. All Gains row in Electrical Characteristics ................................................................. 7
•
Changed Short circuit current, DAC code = full scale, output shorted to GND in Electrical CharacteristicsTYP from
35 mA to 30 mA ..................................................................................................................................................................... 8
•
Changed Short circuit current, DAC code = zero scale, output shorted to VDD in Electrical Characteristics TYP from
30 mA to 35 mA ..................................................................................................................................................................... 8
•
Added Channel-to channel dc crosstalk, Measured channel at midscale. Adjacent channel at full scale. DAC80504
in Electrical Characteristics ................................................................................................................................................... 8
2
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
•
Added Channel-to-channel crosstalk, Measured channel at midscale. All other channels at full scale. DAC80504 in
Electrical Characteristics ....................................................................................................................................................... 8
•
Added Added Reference output drift, DAC80504 in Electrical Characteristics ..................................................................... 9
•
Added Reference thermal hysteresis, DAC80504. First cycle in Electrical Characteristics ................................................... 9
•
Changed some graphs in Typical Characteristics ............................................................................................................... 10
•
Added Figure 59, Solder Heat Reflow Reference Voltage Shift........................................................................................... 23
•
Added tLDACS and tLDACH to Table 7 ...................................................................................................................................... 28
•
Added 010 (12-bit) to D14:12 Description in Table 10 ......................................................................................................... 31
Changes from Original (August 2017) to Revision A
•
Page
Changed from Advance Information to Mixed Status............................................................................................................. 1
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
3
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
5 Device Comparison Table
4
DEVICE
RESOLUTION
REFERENCE
DAC80504
16-Bit
Internal (default) or External
DAC70504
14-Bit
Internal (default) or External
DAC60504
12-Bit
Internal (default) or External
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
6 Pin Configuration and Functions
SDI
SCLK
13
3
10
REFDIV
4
9
RSTSEL
7
8
GAIN
OUT2
14
LDAC
VDD
OUT1
SDO/ALARM
11
Thermal Pad
6
2
15
CS
GND
OUT0
VIO
12
5
1
OUT3
REF
16
RTE Package
16-Pin WQFN
Top View
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
REF
1
I/O
When using internal reference, this is the reference output voltage pin (default). When using an
external reference, this is the reference input pin to the device.
OUT0
2
O
Analog output voltage from DAC 0.
OUT1
3
O
Analog output voltage from DAC 1.
OUT2
4
O
Analog output voltage from DAC 2.
OUT3
5
O
Analog output voltage from DAC 3.
GND
6
GND
Ground reference point for all circuitry on the device.
VDD
7
PWR
Analog supply voltage (2.7 V to 5.5 V).
GAIN
8
I
Sets the gain configuration after a power-up or reset event. When tied to GND, the initial buffer
amplifier gain for all four channels is set to 1. When tied to VIO the initial buffer amplifier gain is 2.
Changing the state of this pin after power-up does not affect the device operation.
RSTSEL
9
I
Reset select pin. When tied to GND all four DACs reset to zero scale. When connected to VIO all four
DACs reset to midscale.
REFDIV
10
I
Sets the reference divider configuration after a power-up or reset event. When tied to GND, the
reference voltage is not divided down. When tied to VIO the reference voltage is divided by 2. Changing
the state of this pin after power-up does not affect the device operation.
LDAC
11
I
A high-to-low transition on the LDAC pin causes the DAC outputs of those channels configured in
synchronous mode to update simultaneously. The pin can be tied permanently to GND.
CS
12
I
Active low serial data enable. This input is the frame synchronization signal for the serial data. When
the signal goes low, it enables the serial interface input shift register.
SCLK
13
I
Serial interface clock.
SDI
14
I
Serial interface data input. Data are clocked into the input shift register on each falling edge of the
SCLK pin.
Serial interface data output (default). The SDO pin is in high impedance when CS pin is high. Data are
clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by
the FSDO bit. Alternatively the pin can be configured as an ALARM open-drain output to indicate a
CRC or reference alarm event. If configured as ALARM a 10 kΩ, pull-up resistor to VIO is required.
SDO/ALARM
15
O
VIO
16
PWR
IO supply voltage (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the serial interface.
Thermal Pad
–
–
The thermal pad is located on the bottom-side of the QFN package. The thermal pad should be
connected to any internal PCB ground plane using multiple vias for good thermal performance.
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
5
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Suppy voltage
Pin voltage
Input current
Temperature
(1)
(1)
MIN
MAX
VDD to GND
–0.3
6
UNIT
VIO to GND
–0.3
6
DAC outputs to GND
–0.3
VDD + 0.3
REF to GND
–0.3
VDD + 0.3
Digital pins to GND
–0.3
VIO + 0.3
Input current to any pin except supply pins
–10
10
Operating free-air, TA
–40
125
Junction, TJ
–40
150
Storage, Tstg
–60
150
V
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
VDD
Analog supply voltage
2.7
5.5
VIO
IO supply voltage
1.7
5.5
0
VIO
Reference divider disabled
1.2
(VDD – 0.2)/2
Reference divider enabled
2.4
VDD – 0.2
Reference divider disabled
1.2
VDD/2
Reference divider enabled
2.4
VDD
–40
125
V
DIGITAL INPUTS
Digital input voltage
V
REFERENCE INPUT
VDD = 2.7 V to 3.3 V
VREFIN
VDD = 3.3 V to 5.5 V
V
TEMPERATURE
TA
6
Operating free-air temperature
Submit Documentation Feedback
°C
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
7.4 Thermal Information
DACx0504
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
33.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.5
°C/W
RθJB
Junction-to-board thermal resistance
7.3
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE (1)
Resolution
INL
DNL
TUE
DAC80504
16
DAC70504
14
DAC60504
12
DAC80504
±0.5
±1
DAC70504
±0.5
±1
DAC60504
±0.5
±1
DAC80504, specified 16-bit monotonic
±0.5
±1
DAC70504, specified 14-bit monotonic
±0.5
±1
DAC60504, specified 12-bit monotonic
±0.5
±1
Total unadjusted error
±0.05
±0.1
%FSR
Offset error
±0.75
±1.5
mV
0.5
1.5
mV
Full-scale error
±0.05
±0.1
%FSR
Gain error
±0.05
±0.1
%FSR
Integral nonlinearity
Differential nonlinearity
Zero-code error
DAC code = zero scale
LSB
LSB
Offset error drift
±1
Zero-code error drift
±2
µV/°C
Full-scale error drift
±2
ppm of FSR/°C
±1
ppm of FSR/°C
20
ppm of FSR
Gain error drift
Output voltage drift over time
(1)
Bits
TA = 25°C, DAC code = midscale, 1600 hours
µV/°C
Static performance specified with DAC outputs unloaded for all gain options, unless otherwise noted. End point fit between codes. 16bit: Code 256 to 65280, 14-bit: Code 128 to 16127, 12-bit: Code 16 to 4031.
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
7
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
Electrical Characteristics (continued)
all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT CHARACTERISTICS
Voltage range
Gain = 2 (BUFF-GAIN = 1, REF-DIV = 0)
0
Gain = 1 (BUFF-GAIN = 1, REF-DIV = 1)
0
VREF
Gain = ½ (BUFF-GAIN = 0, REF-DIV = 1)
0
½ × VREF
to GND or VDD (unloaded)
Output voltage headroom
Short circuit current (2)
Load regulation
Maximum capacitive load (3)
to GND or VDD (–5 mA ≤ IOUT ≤ 5 mA)
2 × VREF
V
0.004
0.15
V
to GND or VDD (–10 mA ≤ IOUT ≤ 10 mA)
0.3
to GND or VDD (–20 mA ≤ IOUT ≤ 20 mA)
0.5
DAC code = full scale, output shorted to GND
30
DAC code = zero scale, output shorted to VDD
35
mA
DAC code = midscale, -10 mA ≤ IOUT ≤ 10 mA
85
µV/mA
RLOAD = ∞
0
2
RLOAD = 2 kΩ
0
10
nF
DAC code = midscale
0.085
DC output impedance
Ω
DAC code at GND or VDD
15
DYNAMIC PERFORMANCE
Output voltage settling time
¼ to ¾ scale and ¾ to ¼ scale settling time to ±2
LSB, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2
Slew rate
VDD = 5.5 V, VREFIN = 2.5 V, gain = 2
1.8
V/µs
Power-up time
DACx-PWDWN 1 to 0 transition, DAC code = full
scale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 (4)
12
µs
Power-up glitch magnitude
DAC code = zero scale, VDD = 5.5 V, VREFIN = 2.5 V,
gain = 2. CLOAD = 50 pF
25
mV
Output noise
0.1 Hz to 10 Hz, DAC code = midscale, VDD = 5.5 V,
VREFIN = 2.5 V, gain = 2
14
µVPP
1 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =
2.5 V, gain = 2
78
10 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =
2.5 V, gain = 2
74
1 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =
2.5 V, gain = 1
55
10 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =
2.5 V, gain = 1
50
AC PSRR
DAC code = midscale, frequency = 60 Hz,
amplitude = 200 mVPP superimposed on VDD
85
dB
DC PSRR
DAC code = midscale, VDD = 5 V ± 10%
10
µV/V
Code change glitch impulse
1 LSB change around major carrier
4
nV-s
Channel-to-channel ac crosstalk
DAC code = midscale. Code 32 to full-scale swing on
adjacent channel
0.2
nV-s
5
Output noise density
nV/√Hz
Measured channel at midscale, adjacent channel at
full scale
5
Measured channel at midscale, all other channels at
full scale
10
DAC code = midscale. fSCLK = 1 MHz, SDO disabled
0.1
nV-s
Channel-to-channel dc crosstalk
Digital feedthrough
µs
µV
EXTERNAL REFERENCE INPUT
Reference input current
VREFIN = 2.5 V
Reference input impedance
Reference input capacitance
(2)
(3)
(4)
8
25
µA
100
kΩ
5
pF
Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified
maximum junction temperature may impair device reliability.
Specified by design and characterization. Not tested during production.
Time to exit DAC power-down mode. Measured from CS rising edge to 90% of DAC final value.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
Electrical Characteristics (continued)
all minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ
to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.495
2.5
2.505
2
5
UNIT
INTERNAL REFERENCE
VREFOUT
Reference output voltage
TA = 25°C
Reference output drift
Reference output impedance
Reference output noise
0.1 Hz to 10 Hz
Reference output noise density
10 kHz, REFLOAD = 10 nF
Reference load current
Reference load regulation
0.1
Ω
15
µVPP
130
nV/√Hz
±5
mA
Source and sink
100
µV/mA
20
µV/V
TA = 25°C, 1600 hours
4.8
ppm
First cycle
50
Additional cycle
18
Reference line regulation
Reference output drift over time
V
ppm/°C
Reference thermal hysteresis
ppm
DIGITAL INPUTS
VIH
High-level input voltage
VIL
Low-level input voltage
0.7 × VIO
V
0.3 × VIO
Input current
Input pin capacitance
V
±2
µA
2
pF
DIGITAL OUTPUTS
VOH
High-level output voltage
ILOAD = 0.2 mA
VOL
Low-level output voltage
ILOAD = –0.2 mA
VIO – 0.4
Output pin capacitance
V
0.4
4
V
pF
POWER SUPPLY REQUIREMENTS
Active mode, internal reference enabled, gain = 1,
DAC code = full scale, outputs unloaded, SPI static
2.8
3.6
Active mode, internal reference disabled, gain = 1,
DAC code = full scale, outputs unloaded, SPI static
2.3
3
Power-down
15
mA
IDD
VDD supply current
IIO
VIO supply current
2
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
µA
3
µA
Submit Documentation Feedback
9
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
7.6 Typical Characteristics
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
1
1
OUT0
OUT1
OUT2
OUT3
0.8
0.6
0.8
0.6
0.4
DNL (LSB)
INL (LSB)
0.4
0.2
0
-0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
OUT0
OUT1
OUT2
OUT3
-1
-1
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D001
Figure 1. Integral Linearity Error vs Digital Input Code
1
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.1
0
-1
-40
8192 16384 24576 32768 40960 49152 57344 65536
Code
D003
Figure 3. Total Unadjusted Error vs Digital Input Code
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
D004
Figure 4. Integral Linearity Error vs Temperature
0.1
1
DNL Max
DNL Min
0.08
Total Unadjusted Error (%FSR)
0.8
DNL Error Max-Min (LSB)
INL Max
INL Min
0.8
INL Error Max-Min (LSB)
OUT0
OUT1
OUT2
OUT3
0.08
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.8
-1
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
Submit Documentation Feedback
-0.1
-40
-25
-10
5
D005
Figure 5. Differential Linearity Error vs Temperature
10
8192 16384 24576 32768 40960 49152 57344 65536
Code
D002
Figure 2. Differential Linearity Error vs Digital Input Code
0.1
Total Unadjusted Error (%FSR)
0.2
20 35 50 65
Temperature (oC)
80
95
110 125
D006
Figure 6. Total Unadjusted Error vs Temperature
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
Typical Characteristics (continued)
1.5
1.5
1
1.25
Zero Code Error (mV)
Offset Error (mV)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
0.5
0
-0.5
-1
-1.5
-40
1
0.75
0.5
0.25
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
0
-40
110 125
0.08
0.08
0.06
0.06
0.04
0.02
0
-0.02
-0.04
80
95
-25
-10
5
D009
Figure 9. Gain Error vs Temperature
D008
20 35 50 65
Temperature (oC)
80
95
110 125
D010
Figure 10. Full Scale Error vs Temperature
1
INL Max
INL Min
0.8
DNL Max
DNL Min
0.8
0.6
DNL Error Max-Min (LSB)
INL Error Max-Min (LSB)
110 125
-0.04
-0.1
-40
110 125
1
0.4
0.2
0
-0.2
-0.4
-0.6
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1
2.7
95
-0.02
-0.08
20 35 50 65
Temperature (oC)
80
0
-0.08
5
20 35 50 65
Temperature (oC)
0.02
-0.06
-10
5
0.04
-0.06
-25
-10
Figure 8. Zero Code Error vs Temperature
0.1
Full Scale Error (%FSR)
Gain Error (%FSR)
Figure 7. Offset Error vs Temperature
0.1
-0.1
-40
-25
D007
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
5.5
-1
2.7
3.1
3.5
D011
Gain = 1
3.9
4.3
VDD (V)
4.7
5.1
5.5
D012
Gain = 1
Figure 11. Integral Linearity Error vs Supply Voltage
Figure 12. Differential Linearity Error vs Supply Voltage
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
11
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
0.1
1.5
1
0.06
0.04
Offset Error (mV)
Total Unadjusted Error (%FSR)
0.08
0.02
0
-0.02
-0.04
-0.06
0
-0.5
-1
REF-DIV = 1
REF-DIV = 0
-0.08
-0.1
2.7
0.5
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
REF-DIV = 1
REF-DIV = 0
-1.5
2.7
5.5
Gain = 1
3.5
3.9
4.3
VDD (V)
4.7
Figure 13. Total Unadjusted Error vs Supply Voltage
D014
Figure 14. Offset Error vs Supply Voltage
REF-DIV = 1
REF-DIV = 0
0.08
Gain Error (%FSR)
0.06
1
0.75
0.5
0.04
0.02
0
-0.02
-0.04
-0.06
0.25
REF-DIV = 1
REF-DIV = 0
-0.08
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
-0.1
2.7
5.5
3.9
4.3
VDD (V)
4.7
5.1
5.5
D016
Figure 16. Gain Error vs Supply Voltage
0.1
1
REF-DIV = 1
REF-DIV = 0
0.08
0.06
0.6
0.04
0.4
0.02
0
-0.02
-0.04
0.2
0
-0.2
-0.4
-0.06
-0.6
-0.08
-0.8
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
Gain = 1
INL Max
INL Min
0.8
INL Error Max-Min
Full Scale Error (%FSR)
3.5
Gain = 1
Figure 15. Zero Code Error vs Supply Voltage
5.5
-1
1.25
2
2.75
D017
3.5
VREFIN (V)
4.25
5
5.5
D018
Gain = 1
Figure 17. Full Scale Error vs Supply Voltage
12
3.1
D015
Gain = 1
-0.1
2.7
5.5
0.1
1.25
0
2.7
5.1
Gain = 1
1.5
Zero Code Error (mV)
3.1
D013
Submit Documentation Feedback
Figure 18. Integral Linearity Error vs Reference Voltage
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
0.1
1
DNL Max
DNL Min
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
1.25
2
2.75
3.5
VREFIN (V)
4.25
5
0.04
0.02
0
-0.02
-0.04
-0.06
-0.1
1.25
5.5
3.5
VREFIN (V)
4.25
5
5.5
D020
Figure 20. Total Unadjusted Error vs Reference Voltage
1.5
REFDIV = 0
REFDIV = 1
1
REFDIV = 0
REFDIV = 1
Zero Code Error (mV)
1.25
0.5
0
-0.5
-1
1
0.75
0.5
0.25
2
2.75
3.5
VREFIN (V)
4.25
5
0
1.25
5.5
2
2.75
D021
Gain = 1
3.5
VREFIN (V)
4.25
5
5.5
D022
Gain = 1
Figure 21. Offset Error vs Reference Voltage
Figure 22. Zero Code Error vs Reference Voltage
0.1
0.1
REFDIV = 0
REFDIV = 1
0.08
Full Scale Error (%FSR)
0.04
0.02
0
-0.02
-0.04
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.06
-0.08
-0.08
2
2.75
3.5
VREFIN (V)
4.25
5
Gain = 1
REFDIV = 0
REFDIV = 1
0.08
0.06
Gain Error (%FSR)
2.75
Gain = 1
1.5
-0.1
1.25
2
D019
Figure 19. Differential Linearity Error vs Reference Voltage
Offset Error (mV)
0.06
-0.08
Gain = 1
-1.5
1.25
REFDIV = 0
REFDIV = 1
0.08
Total Unadjusted Error (%FSR)
DNL Error Max-Min (LSB)
0.8
5.5
-0.1
1.25
2
2.75
D023
3.5
VREFIN (V)
4.25
5
5.5
D024
Gain = 1
Figure 23. Gain Error vs Reference Voltage
Figure 24. Full Scale Error vs Reference Voltage
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
13
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
Typical Characteristics (continued)
3
3
2.5
2.5
1.5
1.5
IDD, Gain = 2
IIO, Gain = 2
IDD, Gain = 1 1
IIO, Gain = 1
1
0.5
IDD (mA)
2
IIO (PA)
0.5
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D025
0
0
Gain = 1, external reference = 2.5 V
Gain = 1
Figure 25. Supply Current With External Reference vs
Digital Input Code
3
3.5
3
2.5
1
0.5
0
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
IDD (mA)
IDD, Gain = 2
IIO, Gain = 2 1
IDD, Gain = 1
IIO, Gain = 1
0.5
IIO (PA)
1.5
3
2.5
2
1.5
3.5
3
2.5
2
IDD (mA)
Figure 26. Supply Current With Internal Reference vs
Digital Input Code
2.5
2
2
1.5
IDD, Gain = 2 1.5
IIO, Gain = 2
IDD, Gain = 1 1
IIO, Gain = 1
1
0.5
0
110 125
0.5
0
-40
-25
-10
5
D027
Gain = 1, external reference = 2.5 V
20 35 50 65
Temperature (qC)
80
95
3
D028
Figure 28. Supply Current With Internal Reference vs
Temperature
3
6
3
5.5
2.5
2.5
2.75
5
2.5
4.5
2
1.5
IDD
IIO 1
1
IDD (mA)
1.5
2.25
4
IIO (PA)
IDD (mA)
2
2
3.5
1.75
3
1.5
2.5
1.25
IDD
IIO 1
2
1.5
0.5
0.5
0.75
1
0.5
0.5
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
0
5.5
3.1
3.5
3.9
4.3
VDD (V)
4.7
5.1
0
5.5
D030
Gain = 1
Figure 29. Supply Current With External Reference vs
Supply Voltage
Submit Documentation Feedback
0.25
0
2.7
D029
Gain = 1, external reference = 2.5 V
14
0
110 125
Gain = 1
Figure 27. Supply Current With External Reference vs
Temperature
0
2.7
IIO (PA)
0
3.25
3
2.75
2.5
2.25
2
1.75
IDD, Gain = 2 1.5
IIO, Gain = 2 1.25
IDD, Gain = 1 1
IIO, Gain = 1
0.75
0.5
0.25
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D026
IIO (PA)
IDD (mA)
2
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
IIO (PA)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
Figure 30. Supply Current With Internal Reference vs
Supply Voltage
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
2
IDD
IIO 1.8
1.6
20
17.5
1.4
17.5
15
1.2
15
12.5
1
10
0.8
7.5
5
2.5
0
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
IDD (PA)
20
IIO (PA)
IDD (PA)
25
0.4
0.35
0.3
12.5
0.25
10
0.2
0.6
7.5
0.15
0.4
5
0.2
2.5
0
110 125
95
0.5
IDD
IIO 0.45
22.5
0.1
0.05
0
2.7
3.1
3.9
4.3
VDD (V)
4.7
5.1
0
5.5
D032
Figure 32. Supply Current and Input Current vs Supply
Voltage
1
4
Code 0x0000
Code 0x4000
Code 0x8000
Code 0xC000
Code 0xFFFF
0.8
3
0.6
DAC Output (V)
0.4
'VOUT (V)
3.5
D031
Figure 31. Supply Current and Input Current vs Temperature
IIO (PA)
25
22.5
0.2
0
-0.2
-0.4
Sourcing 5.5V
Sourcing 2.7V
Sinking 5.5V
Sinking 2.7V
-0.6
-0.8
5
10
15
20
Load Current (mA)
25
1
0
-1
-1
0
2
-2
-60
30
-40
D033
Figure 33. Headroom/Footroom vs Load Current
-20
0
20
Load Current (mA)
40
60
D034
Figure 34. Source and Sink Capability With Gain = ½
7
4
6
0xFFFF
0xC000
2
0x8000
1
0x4000
0x0000
0
0xFFFF
5
DAC Output (V)
DAC Output (V)
3
0xC000
4
3
0x8000
2
0x4000
1
0x0000
0
-1
-1
-2
-60
-40
-20
0
20
Load Current (mA)
40
60
D035
Figure 35. Source and Sink Capability With Gain = 1
-2
-60
-40
-20
0
20
Load Current (mA)
40
60
D036
Figure 36. Source and Sink Capability With Gain = 2
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
15
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
Time (2 Psec/div)
Time (2 Psec/div)
D037
Gain = 1
D038
Gain = 1
Figure 37. Full-Scale Settling Time, Rising Edge
Figure 38. Full-Scale Settling Time, Falling Edge
VOUT (2.5 mV/div)
CS (5 V/div)
VOUT (2.5mV/div)
CS (5 V/div)
Time (0.5 Ps/div)
Time (0.5 Ps/div)
D039
Gain = 1
D040
Gain = 1
Figure 39. Glitch Impulse, Falling Edge, 1 LSB Step
Figure 40. Glitch Impulse, Rising Edge, 1 LSB Step
VDD (1.5 V/div)
VOUT (1 V/div)
VDD (1.5 V/div)
VOUT (10 mV/div)
Time (600Ps/div)
Time (600 Ps/div)
D042
D041
Gain = 1
Gain = 1
Figure 41. Power-On, Reset to Zero Scale
16
Submit Documentation Feedback
Figure 42. Power-On, Reset to Midscale
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
VDD (1.5 V/div)
VOUT (1 V/div)
VIO (1.5 V/div)
VOUT (1 V/div)
Time (600Ps/div)
Time (600Ps/div)
D044
D060
Gain = 1, DAC code at midscale
Gain = 1, DAC code at midscale
Figure 43. VDD Power-Down
Figure 44. VIO Power-Down
SCLK (5 V/div)
VOUT (1 mV/div)
VOUT (200 PV/div)
CS (5 V/div)
Time (2 Psec/div)
Time (5 Psec/div)
D045
D046
Gain = 1, measured DAC at midscale,
all other DACs switch from code 32 to full scale
Gain = 1, DAC code at midscale
Figure 45. Channel to Channel Crosstalk
Figure 46. Clock Feedthrough With SCLK = 1 MHz
0
300
Gain = 1
Gain = 2
-10
-20
250
-40
Noise (nV/—Hz)
AC PSRR (dB)
-30
-50
-60
-70
-80
200
150
100
-90
-100
50
-110
-120
1
10
100
1000
Frequency (Hz)
10000
100000
D047
Gain = 1, VDD = 5 V + 200 mVPP (Sinusoid), DAC code at fullscale
Figure 47. DAC Output AC PSRR vs Frequency
0
10 2030 50 100 200
5001000
Frequency (Hz)
10000
100000
D048
External reference = 2.5 V, DAC code at midscale
Figure 48. DAC Output Noise Density vs Frequency
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
17
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
Typical Characteristics (continued)
VNOISE (2 PV/div)
VNOISE (2 PV/div)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
D049
Gain = 1, external reference = 2.5 V, DAC code at midscale
D050
Gain = 1, DAC code at midscale
Figure 50. DAC Output Noise With Internal Reference
0.1 Hz to 10 Hz
2.505
2.505
2.5025
2.5025
Internal Reference (V)
Internal Reference (V)
Figure 49. DAC Output Noise With External Reference
0.1 Hz to 10 Hz
2.5
2.4975
2.495
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
2.5
2.4975
2.495
2.7
110 125
3.1
3.5
D051
3.9
4.3
VDD (V)
4.7
5.1
5.5
D053
Figure 52. Internal Reference Voltage vs Supply Voltage
Figure 51. Internal Reference Voltage vs Temperature
2.505
800
2.5025
600
Noise (nV/—Hz)
Internal Reference (V)
700
2.5
2.4975
500
400
300
200
100
2.495
0
200
400
600
800 1000
Hours
1200
1400
Figure 53. Internal Reference Voltage vs Time
18
Submit Documentation Feedback
1600
0
10 2030 50 100 200
D055
5001000
Frequency (Hz)
10000
100000
D056
Figure 54. Internal Reference Noise Density vs Frequency
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, gain = 2, DAC outputs unloaded (unless otherwise noted)
45
40
Number of Units
VNOISE (2 PV/div)
35
30
25
20
15
10
5
0
0
D057
1
2
3
Temperature Drift (ppm/qC)
4
5
D058
0.1 Hz to 10 Hz
Figure 55. Internal Reference Noise
Figure 56. Internal Reference Temperature Drift Histogram
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
19
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
8 Detailed Description
8.1 Overview
The DACx0504 is a pin-compatible family of low-power, four-channel, buffered voltage-output digital-to-analog
converters (DACs) with 16-, 14-, and 12-bit resolution. The DACx0504 include a 2.5-V internal reference and
user-selectable gain configuration. providing full-scale output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1), or 5
V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is specified monotonic, and provides high
linearity of ±1 LSB INL.
Communication to the DACx0504 is performed through a 4-wire serial interface that supports stand-alone and
daisy-chain operation. The optional frame-error checking provides added robustness to the DACx0504 serial
interface.
The DACx0504 incorporates a power-on-reset circuit and RSTSEL pin that powers up and maintains the DAC
outputs at either zero scale or midscale until a valid code is written to the device.
8.2 Functional Block Diagram
VIO
VDD
REFDIV
REF
GAIN
Internal
Reference
DACx0504
÷1 or ÷2
GAIN
×1 or ×2
SCLK
DAC
Buffer
SDO/ALARM
CS
Interface Logic
SDI
LDAC
DAC
Register
DAC
OUT0
BUF
Channel 0
Channel 1
OUT1
Channel 2
OUT2
Channel 3
OUT3
Power On Reset
Power Down Logic
Resistive Network
RSTSEL
GND
Copyright © 2017, Texas Instruments Incorporated
20
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC)
Each output channel in the DACx0504 consists of an R-2R ladder architecture followed by an output buffer
amplifier. Figure 57 shows a block diagram of the DAC architecture.
REF
2.5-V
Reference
REF Divider
(÷1 or ÷2)
Serial Interface
DAC Data Register
READ
DIV
GAIN
WRITE
DAC
Buffer
Register
DAC
Active
Register
R-2R
Gain
(×1 or ×2)
VOUT
DAC Output
(asynchronous mode)
LDAC Trigger
(synchronous mode)
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 57. DACx0504 DAC Block Diagram
8.3.1.1 DAC Transfer Function
The input data are written to the individual DAC data registers in straight binary format. After a power-on or a
reset event, all DAC registers are set to either zero code or midscale code, as determined by the RSTSEL pin.
The DAC transfer function is given by Equation 1.
CODE VREF
VOUT
u
u GAIN
DIV
2n
where
•
•
•
•
•
CODE = decimal equivalent of the binary code that is loaded to the DAC register. CODE ranges from 0 to 2n –
1.
VREF = DAC reference voltage. Either VREFOUT from the internal 2.5 V reference or VREFIN if using an external
one.
n = resolution in bits. Either 16 (DAC80504), 14 (DAC70504), or 12 (DAC60504).
DIV = 1 or 2 as set by the REFDIV pin after a reset event or by the REF-DIV bit in the GAIN register.
GAIN = 1 or 2 as set by the GAIN pin after a reset event or by the BUFF-GAIN bit for that DAC channel in the
GAIN register.
(1)
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
21
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
Feature Description (continued)
8.3.1.2 Output Amplifiers
The DACx0504 output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a
maximum output range of 0 V to VDD. Each buffer amplifier is capable of driving a load of 2 kΩ in parallel with
10 nF to GND.
The full-scale output voltage for each channel is determined by the reference voltage (VREF), the reference
divider setting (DIV), and the output buffer gain for that channel (GAIN), as shown in Table 1. After a power-up or
reset event the DIV and GAIN settings are set by the REFDIV and GAIN pins, respectively. During normal
operation the DIV and GAIN settings can be reconfigured through the REF-DIV and BUFF-GAIN bit (see
Equation 1). The GAIN setting for each output channel can be individually configured thus enabling independent
output voltage ranges for each DAC output.
Table 1. DAC Output Range Configuration
DIV SETTING
GAIN SETTING
÷2
×1
0 V to ½ × VREF
DAC OUTPUT RANGE
÷1
×1
Not recommended
÷2
×2
0 V to VREF
÷1
×2
0 V to 2 × VREF
8.3.1.3 DAC Register Structure
Data written to the DAC data registers is initially stored in the DAC buffer registers. Transfer of data from the
DAC buffer registers to the active DAC registers can be configured to happen immediately (asynchronous mode)
or initiated by an LDAC trigger (synchronous mode). Once the DAC active registers are updated, the DAC
outputs change to their new values. When the host reads from a DAC Data register, the value held in the DAC
buffer register is returned (not the value held in the DAC active register).
8.3.1.3.1 DAC Register Synchronous and Asynchronous Updates
The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In
asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register
and DAC output on CS rising edge. In synchronous mode, writing to the DAC data register does not
automatically update the DAC output. Instead the update occurs only after an LDAC trigger event. An LDAC
trigger is generated either through the LDAC bit in the TRIGGER register or by the LDAC pin. The synchronous
update mode enables simultaneous update of multiple DAC outputs. In both update modes a minimum wait time
of 1 µs is required between DAC output updates.
8.3.1.3.2 Broadcast DAC Register
The DAC broadcast register enables a simultaneous update of multiple DAC outputs with the same value with a
single register write. Each DAC channel can be configured to update or remain unaffected by a broadcast
command by setting the corresponding DAC-BRDCAST-EN bit in the SYNC register. A register write to the
BRDCAST-DATA register forces those DAC channels that have been configured for broadcast operation to
update their outputs. The DAC ouputs update to the broadcast value on CS rising edge independently of their
synchronous mode configuration.
22
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
8.3.2 Internal Reference
The DACx0504 includes a 2.5 V precision bandgap reference enabled by default. Operation from an external
reference is supported by disabling the internal reference in the CONFIG register. The internal reference is
externally available at the REF pin.
A minimum 150 nF capacitor is recommended between the reference output and GND for noise filtering.
8.3.2.1 Reference Divider
The reference voltage to the device, either from the internal reference or an external one can be divided by a
factor of two by tying the REFDIV pin high at power-up or by setting the REF-DIV bit in the GAIN register to 1
during normal operation. The reference voltage divider provides additional flexibility in setting the full-scale output
voltage for each DAC output and must be configured to make certain that there is sufficient headroom from VDD
to the DAC operating reference voltage (VREF/DIV). See the Recommended Operating Conditions table for more
information.
Improper configuration of the reference divider issues a reference alarm condition. In this case, the reference
buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm
condition thus enabling the DAC output to return to normal operation once the reference divider is configured
correctly. The reference alarm status can be read from the REF-ALM bit in the STATUS register. Additionally by
setting ALM-EN = 1 and ALM-SEL = 1 in the CONFIG register, the SDO/ALARM pin is configured as a reference
alarm pin.
8.3.2.2 Solder Heat Reflow
A known behavior of IC reference voltage circuits is the shift induced by the soldering process. Figure 58 shows
the effect of solder heat reflow for the DACx0504 internal reference.
70%
Presolder Heat Reflow
Postsolder Heat Reflow
Percentage of Units
60%
50%
40%
30%
20%
10%
0
2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010
VREFOUT (V)
D061
Figure 58. Solder Heat Reflow Reference Voltage Shift
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
23
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
8.3.3 Device Reset Options
8.3.3.1 Power-on-Reset (POR)
The DACx0504 includes a power-on reset function that controls the output voltage at power up. After the VDD
and VIO supplies have been established a POR event is issued. The POR causes all registers to initialize to their
default values and communication with the device is valid only after a 250 µs power-on-reset delay. The default
value for all DACs is either zero-code or midscale-code as determined by the RSTSEL pin. Each DAC channel
remains at the power-up voltage until a valid command is written to it.
The POR circuit requires specific supply levels to discharge the internal capacitors and to reset the device on
power up, as indicated in Figure 59 and Figure 60. In order to initiate a POR event, VDD or VIO must be below
their corresponding low thresholds for at least 100 µs. If VDD and VIO remain above their specified high threshold
a POR event will not occur. When the supplies drop below their high threshold but remain over the lower one
(shown as the undefined region), the device may or may not reset under all specified temperature and powersupply conditions.
VDD (V)
VIO (V)
5.50
5.50
No Power-On Reset
Specified Supply
Voltage Range
No Power-On Reset
Specified Supply
Voltage Range
2.70
2.20
Undefined
1.70
1.50
1.20
Undefined
0.70
Power-On Reset
Power-On Reset
0.00
0.00
Figure 59. Threshold Levels for VDD POR Circuit
Figure 60. Threshold Levels for VIO POR Circuit
8.3.3.2 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to SOFT-RESET in the TRIGGER
register. The software reset command is triggered on the CS rising edge of the instruction. A software reset
initiates a POR event.
24
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
8.4 Device Functional Modes
8.4.1 Stand-Alone Operation
A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a
continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is
24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the CS pin must stay
low for at least 24 or 32 SCLK falling edges. The access cycle ends when the CS pin is de-asserted high. If the
access cycle contains less than the minimum clock edges, the communication is ignored. If the access cycle
contains more than the minimum clock edges are present, only the last 24 or 32 bits are used by the device.
When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state.
In an error checking disabled access cycle (24-bits long) the first byte input to SDI is the instruction cycle which
identifies the request as a read or write command and the 4-bit address to be accessed. The following bits in the
cycle form the data cycle, as shown in Table 2.
Table 2. Serial Interface Access Cycle
BIT
FIELD
23
RW
22:20
Reserved
19:16
A[3:0]
15:0
DI[15:0]
DESCRIPTION
Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a
write operation. R/W = 1 sets a read operation.
Reserved bits. Must be filled with zeros.
Register address. Specifies the register to be accessed during the read or write operation.
Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with
address A[3:0]. If a read command, the data cycle bits are don’t care values.
A read operation is initiated by issuing a read command access cycle. After the read command, a second access
cycle must be issued to get the requested data, as shown in Table 3. Data are clocked out on SDO pin either on
the falling edge or rising edge of SCLK according to the FSDO bit in the CONFIG register.
Table 3. SDO Output Access Cycle
BIT
FIELD
23
RW
22:20
Reserved
19:16
A[3:0]
15:0
DO[15:0]
DESCRIPTION
Echo RW from previous access cycle.
Echo bits 22:20 from previous access cycle (all zeros).
Echo address from previous access cycle.
Readback data requested on previous access cycle.
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
25
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
8.4.2 Daisy-Chain Operation
For systems that contain more than one DACx0504 devices, the SDO pin can be used to daisy-chain them
together. Daisy-chain operation is useful in reducing the number of serial interface lines.
The first falling edge on the CS pin starts the operation cycle. If more than 24 SCLK pulses are applied while the
CS pin is kept low, the data ripples out of the shift register and is clocked out on the SDO pin either on the falling
edge or rising edge of SCLK according to the FSDO bit. By connecting the SDO output of the first device to the
SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system
requires 24 clock pulses. As a result the total number of clock cycles must be equal to 24 × N, where N is the
total number of DACx0504 devices in the daisy chain. When the serial transfer to all devices is complete the CS
signal is taken high. This action transfers the data from the serial peripheral interface (SPI) shift registers to the
internal registers of each device in the daisy chain and prevents any further data from being clocked into the
input shift register.
C
B
DACx0504
DACx0504
DACx0504
SDO
SDI
A
SDI
SDO
SDI
SCLK
SCLK
SCLK
CS
CS
CS
SDO
Copyright © 2017, Texas Instruments Incorporated
Figure 61. Daisy-Chain Layout
8.4.3 Frame Error Checking
If the DACx0504 is used in a noisy environment, error checking can be used to check the integrity of SPI data
communication between the device and the host processor. This feature can be enabled by setting the CRC-EN
bit in the CONFIG register.
The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111).
When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are
appended with an 8-bit CRC polynomial by the host processor before feeding it to the device, as shown in
Table 4. In all serial interface readback operations the CRC polynomial is output on the SDO pin as part of the
32-bit cycle.
Table 4. Error Checking Serial Interface Access Cycle
BIT
26
FIELD
31
RW
30
CRC-ERROR
29:28
Reserved
27:24
A[3:0]
23:8
DI[15:0]
7:0
CRC
DESCRIPTION
Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a
write operation. R/W = 1 sets a read operation.
Reserved bit. Set to zero.
Reserved bits. Must be filled with zeros.
Register address. Specifies the register to be accessed during the read or write operation.
Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with
address A[3:0]. If a read command, the data cycle bits are don’t care values.
8-bit CRC polynomial.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
The DACx0504 decodes the 32-bit access cycle to compute the CRC remainder on CS rising edges. If no error
exists, the CRC remainder is zero and data are accepted by the device.
A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a
second access cycle can be issued to determine the error checking result (CRC-ERROR bit) on the SDO pin, as
shown in Table 5. Additionally, by setting ALM-EN = 1 and ALM-SEL = 0 in the CONFIG register, the
SDO/ALARM pin is configured as a CRC alarm pin.
Table 5. Write Operation Error Checking Cycle
BIT
FIELD
31
RW
DESCRIPTION
30
CRC-ERROR
Returns a 1 when a CRC error is detected, 0 otherwise.
29:28
Reserved
Echo bits 29:28 from previous access cycle (all zeros).
27:24
A[3:0]
23:8
DO[15:0]
7:0
CRC
Echo RW from previous access cycle (RW = 0).
Echo address from previous access cycle.
Echo data from previous access cycle.
Calculated CRC value of bits 31:8.
A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The
error check result (CRC-ERROR bit) from the read command is output on the SDO pin, as shown in Table 6. As
in the case of a write operation failing the CRC check, the SDO/ALARM pin if configured as a CRC alarm pin can
be used to indicate a read command CRC failure.
Table 6. Read Operation Error Checking Cycle
BIT
FIELD
DESCRIPTION
31
RW
30
CRC-ERROR
Returns a 1 when a CRC error is detected, 0 otherwise.
29:28
Reserved
Echo bits 29:28 from previous access cycle (all zeros).
27:24
A[3:0]
23:8
DO[15:0]
7:0
CRC
Echo RW from previous access cycle (RW = 1).
Echo address from previous access cycle.
Readback data requested on previous access cycle.
Calculated CRC value of bits 31:8.
8.4.4 Power-Down Mode
The DACx0504 DAC output amplifiers and internal reference can be independently powered down through the
CONFIG register. At power-up all output channels and the device internal reference are active by default. A DAC
output channel in power-down mode is connected internally to GND through a 1-kΩ resistor.
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
27
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
8.5 Programming
The DACx0504 is controlled through a flexible four-wire serial interface that is compatible with SPI type
interfaces used on many microcontrollers and DSP controllers. The interface provides read and write access to
all DACx0504 registers and can also be configured to daisy-chain multiple devices for write operations. The
DACx0504 incorporates an optional error checking mode to validate SPI data communication integrity in noisy
environments. Table 7 shows the SPI timing requirements. Figure 62 and Figure 63 show the SPI write and read
timing diagrams, respectively. Figure 64 shows the digital logic timing diagram.
Table 7. Programming Timing Requirements (1)
VIO = 1.7 V to 2.7 V
MIN
NOM
VIO = 2.7 V to 5.5 V
MAX
MIN
NOM
MAX
UNIT
SERIAL INTERFACE – WRITE OPERATION
fSCLK
SCLK frequency
tSCLKHIGH
SCLK high time
9
50
9
50
MHz
ns
tSCLKLOW
SCLK low time
9
9
ns
tSDIS
SDI setup
5
5
ns
tSDIH
SDI hold
10
10
ns
tCSS
CS to SCLK falling edge setup
13
13
ns
tCSH
SCLK falling edge to CS rising edge
10
10
ns
tCSHIGH
CS high time
15
15
ns
tCSIGNORE
SCLK falling edge to CS ignore
7
7
ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 0
fSCLK
SCLK frequency
tSCLKHIGH
SCLK high time
35
12
25
18
MHz
ns
tSCLKLOW
SCLK low time
35
25
ns
tSDIS
SDI setup
5
5
ns
tSDIH
SDI hold
10
10
ns
tCSS
CS to SCLK falling edge setup
32
20
ns
tCSH
SCLK falling edge to CS rising edge
10
10
ns
tCSHIGH
CS high time
15
15
tSDODLY
SDO output delay from SCLK rising edge
3.5
33.5
3.5
23
ns
tSDODZ
SDO driven to tri-state
0
30
0
25
ns
tCSIGNORE
SCLK falling edge to CS ignore
7
ns
7
ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 1
fSCLK
SCLK frequency
tSCLKHIGH
SCLK high time
22
20
18
25
MHz
ns
tSCLKLOW
SCLK low time
22
18
ns
tSDIS
SDI setup
5
5
ns
tSDIH
SDI hold
10
10
ns
tCSS
CS to SCLK falling edge setup
32
20
ns
tCSH
SCLK falling edge to CS rising edge
10
10
ns
tCSHIGH
CS high time
15
15
tSDODLY
SDO output delay from SCLK falling edge
3.5
45
3.5
32
ns
tSDODZ
SDO driven to tri-state
0
30
0
25
ns
tCSIGNORE
SCLK falling edge to CS ignore
7
ns
7
ns
DIGITAL LOGIC
tRSTDLYPOR
POR reset delay
tDACWAIT
Sequential DAC output updates
1
1
µs
tLDACS
LDAC setup
0
0
ns
tLDACH
LDAC hold
5
5
ns
(1)
28
170
250
170
250
µs
All input signals are specified at tR = tF = 1 ns/V (10% to 90% of VIO), timed from a voltage level of (VIL + VIH) / 2, VDD = 2.7 V to 5.5 V,
VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted)
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
tCSHIGH
tCSS
tCSH
CS
tCSIGNORE
tSCLKLOW
SCLK
tSCLKHIGH
SDI
Bit 23
Bit 1
Bit 0
tSDIH
tSDIS
Figure 62. Serial Interface Write Timing Diagram
tCSHIGH
tCSS
tCSH
CS
tCSIGNORE
tSCLKLOW
SCLK
tSCLKHIGH
FIRST READ COMMAND
SDI
Bit 23
tSDIS
Bit 22
ANY COMMAND
Bit 0
Bit 23
Bit 1
Bit 0
Bit 23
Bit 1
Bit 0
tSDIH
SDO
FSDO = 0
tSDODZ
tSDODLY
DATA FROM FIRST READ COMMAND
SDO
FSDO = 1
Bit 23
Bit 1
Bit 0
X
tSDODZ
tSDODLY
DATA FROM FIRST READ COMMAND
Figure 63. Serial Interface Read Timing Diagram
tLDACS
tLDACH
CS
LDAC
Figure 64. Digital Logic Timing Diagram
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
29
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
8.6 Register Map
Table 8. Register Map
ADDRESS BITS
REGISTER
NOP
30
TYPE
W
DATA BITS
RESET
A3
A2
A1
A0
0000
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
DEVICE ID
R
—
0
0
0
1
SYNC
R/W
FF00
0
0
1
0
CONFIG
R/W
0000
0
0
1
1
GAIN
R/W
0000
0
1
0
0
TRIGGER
W
0000
0
1
0
1
BRDCAST
R/W
0000
0
1
1
0
STATUS
R/W
0000
0
1
1
1
DAC0
R/W
0000
1
0
0
0
DAC0-DATA[15:0]
DAC1
R/W
0000
1
0
0
1
DAC1-DATA[15:0]
DAC2
R/W
0000
1
0
1
0
DAC2-DATA[15:0]
DAC3
R/W
0000
1
0
1
1
DAC3-DATA[15:0]
All Others
—
—
—
—
—
—
RESERVED
Submit Documentation Feedback
D6
D5
D4
D3
D2
D1
D0
NOP
DEVICEID
RESERVED
RESERVED
ALM
SEL
DACx-BRDCAST-EN
ALM
EN
CRC
EN
F
SDO
D
SDO
RESERVED
VERSIONID
RESERVED
DACx-SYNC-EN
REF
PWD
WN
RESERVED
DACx-PWDWN
REF
DIVEN
RESERVED
BUFFx-GAIN
L
DAC
RESERVED
SOFT-RESET[3:0]
BRDCAST-DATA[15:0]
RESERVED
REF
ALM
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
8.6.1 NOP Register (address = 0x00) [reset = 0x0000]
Figure 65. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOP
W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. NOP Register Field Descriptions
Bit
Field
Type
Reset
Description
15:0
NOP
W
0x0000
No operation. Write 0000h for proper no-operation command
8.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]
Figure 66. DEVICE ID Register
15
14
13
12
11
10
9
8
DEVICEID
R
7
6
5
4
3
2
1
0
VERSIONID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. DEVICE ID Field Descriptions
Bit
Field
Type
Reset
Description
15:2
DEVICEID
R
----
Device ID:
D15 Reserved - 0
D14:12 Resolution - 000 (16-bit); 001 (14-bit); 010 (12-bit)
D11:4 Channels - 0100 (4 channels)
D7 Reset - Determined by RSTSEL pin. 0 (reset to zero); 1
(reset to midscale)
D6:2 Reserved - 00101
1:0
VERSIONID
R
11
Version ID. Subject to change
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
31
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
8.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]
Figure 67. SYNC Register
15
14
13
12
11
DAC3BRDCAST-EN
R/W
10
DAC2BRDCAST-EN
R/W
9
DAC1BRDCAST-EN
R/W
8
DAC0BRDCAST-EN
R/W
5
4
3
DAC3-SYNCEN
R/W
2
DAC2-SYNCEN
R/W
1
DAC1-SYNCEN
R/W
0
DAC0-SYNCEN
R/W
Reserved
—
7
6
Reserved
—
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. SYNC Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
—
1111
Reserved for factory use
11
DAC3-BRDCAST-EN
R/W
1
10
DAC2-BRDCAST-EN
R/W
1
9
DAC1-BRDCAST-EN
R/W
1
8
DAC0-BRDCAST-EN
R/W
1
When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
When cleared to 0 the corresponding DAC output remains
unaffected after a serial interface write to the BRDCAST
register.
15:12
7:4
32
Reserved
—
0000
Reserved for factory use
3
DAC3-SYNC-EN
R/W
0
2
DAC2-SYNC-EN
R/W
0
1
DAC1-SYNC-EN
R/W
0
When set to 1 the corresponding DAC output is set to update in
response to an LDAC trigger (synchronous mode).
When cleared to 0 the corresponding DAC output is set to
update immediately on a CS rising edge (asynchronous mode).
0
DAC0-SYNC-EN
R/W
0
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
8.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]
Figure 68. CONFIG Register
15
14
Reserved
—
7
13
ALM-SEL
R/W
12
ALM-EN
R/W
5
4
6
11
CRC-EN
R/W
10
FSDO
R/W
9
DSDO
R/W
8
REF-PWDWN
R/W
3
2
1
0
DAC3-PWDWN DAC2-PWDWN DAC1-PWDWN DAC0-PWDWN
R/W
R/W
R/W
R/W
Reserved
—
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
Reserved
—
00
Reserved for factory use
13
ALM-SEL
R/W
0
ALARM select.
0: ALARM pin is CRC-ERROR
1: ALARM pin is REF-ALARM
12
ALM-EN
R/W
0
Configure SDO/ALARM pin. When 1: SDO/ALARM pin is an
active-low, open-drain, alarm pin. An external 10 kΩ pullup
resistor to VIO is required. FSDO and DSDO bits are ignored.
When 0: SDO/ALARM pin is a serial interface, push-pull, SDO
pin
11
CRC-EN
R/W
0
CRC enable bit. Set to 1 to enable CRC. Set to 0 to disable
10
FSDO
R/W
0
Fast SDO bit (half-cycle speedup). When 0, SDO updates on an
SCLK rising edge. When 1, SDO updates a half-cycle earlier,
during an SCLK falling edge.
9
DSDO
R/W
0
Disable SDO bit. When 1, SDO is always tri-stated. When 0,
SDO is driven while CS is low, and tri-stated while CS is high
8
REF-PWDWN
R/W
0
When set to 1 disables the device internal reference
Reserved
—
0000
Reserved for factory use
3
DAC3-PWDWN
R/W
0
2
DAC2-PWDWN
R/W
0
When set to 1 the corresponding DAC is set in power-down
mode and its output is connected to GND through a 1 kΩ
internal resistor.
1
DAC1-PWDWN
R/W
0
0
DAC0-PWDWN
R/W
0
7:4
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
33
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
8.6.5 GAIN Register (address = 0x04) [reset = 0x---]
Figure 69. GAIN Register
15
14
7
6
13
12
Reserved
—
11
10
9
8
REFDIV-EN
R/W
5
4
3
BUFF3-GAIN
R/W
2
BUFF2-GAIN
R/W
1
BUFF1-GAIN
R/W
0
BUFF0-GAIN
R/W
Reserved
—
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. GAIN Register Field Descriptions
Bit
15:9
8
7:4
Field
Type
Reset
Description
Reserved
—
0
Reserved for factory use.
REFDIV-EN
R/W
0/1
When set to 1 the reference voltage is internally divided by a
factor of 2.
When cleared to 0 the reference voltage is unaffected.
Default value is determined by the REFDIV pin.
Reserved
—
0000
Reserved for factory use
3
BUFF3-GAIN
R/W
0/1
2
BUFF2-GAIN
R/W
0/1
1
BUFF1-GAIN
R/W
0/1
0
BUFF0-GAIN
R/W
0/1
When set to 1 the buffer amplifier for corresponding DAC has a
gain of 2.
When cleared to 0 the buffer amplifier for corresponding DAC
has a gain of 1.
Default value is determined by the GAIN pin.
8.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]
Figure 70. TRIGGER Register
15
14
13
12
11
10
Reserved
—
9
8
7
6
5
4
LDAC
W
3
2
1
SOFT-RESET[3:0]
W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. TRIGGER Register Field Descriptions
Bit
15:5
4
3:0
34
Field
Type
Reset
Description
Reserved
—
0
Reserved for factory use.
LDAC
W
0
Set this bit to 1 to synchronously load those DACs that have
been set in synchronous mode in the SYNC register.
SOFT-RESET[3:0]
W
0x0
When set to the reserved code 1010 resets the device to its
default state.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
8.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]
Figure 71. BRDCAST Register
15
14
13
12
11
10
9
8
7
6
BRDCAST-DATA[15:0]
R/W
5
4
3
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. BRDCAST Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
BRDCAST-DATA[15:0]
R/W
0x0000
Writing to the BRDCAST register forces those DAC channels
that have been set to broadcast in the SYNC register to update
their active data register with the BRDCAST-DATA value.
Data are MSB aligned in straight binary format and follows the
format below:
DAC80504: { DATA[15:0] }
DAC70504: { DATA[13:0], x, x }
DAC60504: { DATA[11:0], x, x, x, x }
x – Don’t care bits
8.6.8 STATUS Register (address = 0x7) [reset = 0x0000]
Figure 72. STATUS Register
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
—
0
REFALM
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. STATUS Register Field Descriptions
Field
Type
Reset
Description
15:1
Bit
Reserved
—
0
Reserved for factory use.
0
REF-ALM
R
0
Reference alarm bit. Reads 1 when the difference between
VREF/DIV and VDD is below the required minimum analog
threshold. Reads 0 otherwise.
8.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]
Figure 73. DACx Register
15
14
13
12
11
10
9
8
7
DACx-DATA[15:0]
R/W
6
5
4
3
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. DACx Register Field Descriptions
Bit
15:0
Field
Type
Reset
Description
DACx-DATA[15:0]
R/W
0x0000 or
0x8000
Stores the 16- or 14-bit data to be loaded to DACx in MSB
aligned straight binary format. The default value is determined
by the RSTSEL pin.
Data follows the format below:
DAC80504: { DATA[15:0] }
DAC70504: { DATA[13:0], x, x }
DAC60504: { DATA[11:0], x, x, x, x }
x – Don’t care bits
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
35
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The high linearity, small package size and wide temperature range make the DACx0504 suitable in applications
such as optical networking, wireless infrastructure, industrial automation and data acquisition systems. The
device incorporates a 2.5 V internal reference with an internal reference divider circuit that enables full-scale
DAC output voltages of 1.25 V, 2.5 V, or 5 V.
9.1.1 Interfacing to a Microcontroller
Figure 74 displays a typical serial interface that may be observed when connecting the DACx0504 SPI serial
interface to a (master) microcontroller type platform. The setup for the interface is as follows: the microcontroller
output SPI CLK drives the SCLK pin of the DACx0504, while the DACx0504 SDI pin is driven by the MOSI pin of
the microcontroller. The CS pin of the DACx0504 can be asserted from a general program input/output pin of the
microcontroller. When data are to be transmitted to the DACx0504, the CS pin is taken low. The data from the
microcontroller is then transmitted to the DACx0504, totaling 24 bits latched into the DACx0504 device through
the falling edge of SCLK. CS is then brought high after the completed write. The DACx0504 requires data with
the MSB as the first bit received.
Microcontroller
CS
DACx0504
CS
SCLK
SCLK
MOSI
SDI
MISO
SDO
Copyright © 2017, Texas Instruments Incorporated
Figure 74. Typical Serial Interface
36
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
Application Information (continued)
9.1.2 Programmable Current Source Circuit
The DACx0504 can be integrated into the circuit in Figure 75 to implement an improved Howland current pump
for precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two
features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 2.
R2 R3 / R1
CODE
u VREF u
IL
R3
(2)
2n
The value of R3 in Equation 2 can be reduced to increase the output current drive of U3. U3 can drive ±20 mV in
both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the circuit
compensation capacitor C1 in the circuit is not suggested as a result of the change in the output impedance ZO,
according to Equation 3.
R1' R3 R1 R2
ZO
R1 R2'
R3'
R1' R2 R3
(3)
As shown in Equation 3, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a
value of several pF is suggested.
R2'
15 k
VDD
REF
VDD
VREF
C1
10 pF
VDAC
R1'
150 k
DACx0504
R3'
50
U3
OPA277
GND
VOUT
R3
50
GND
R1
150 k
R2
15 k
IL
LOAD
Copyright © 2017, Texas Instruments Incorporated
Figure 75. Programmable Bidirectional Current Source Circuit
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
37
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
9.2 Typical Application
The DACx0504 is designed for single-supply operation; however, a bipolar output is also possible using the
circuit shown in Figure 76.
GND
DACx0504
15 V
VDAC
R2
REF
OPA192
VOUT
VREF
±15 V
R1
R3
VREF
Copyright © 2017, Texas Instruments Incorporated
Figure 76. Bipolar Operation Using the DACx0504
9.2.1 Design Requirements
The circuit shown in Figure 76 gives a bipolar output voltage at VOUT. When GAIN = 1, VOUT can be calculated
using Equation 4:
ª§
R3 · º
CODE · § R3 R3 · §
u
VOUT CODE Ǭ VREF u
1
V
¨
¸
¨
¸»
REF
¸
R1 ¹ »¼
2n ¹ © R2 R1 ¹ ©
«¬©
where
•
•
•
•
VOUT(CODE) = output voltage versus code
CODE = 0 to 2n – 1. This is the digital code loaded to the DAC
VREF = reference voltage applied to the DACx0504
n = resolution in bits
(4)
Table 18. Design Parameters
PARAMETER
VALUE
VOUT
±10 V
VREF
2.5 V
n
12
9.2.2 Detailed Design Procedure
The bipolar output span can be calculated through Equation 4 by defining a few parameters, the first being the
value for the reference voltage. Once a reference voltage is chosen, the gain resistors can be set accordingly by
determining the desired VOUT at code 0 and code 2n. For a VREF of 2.5 V and a desired output voltage range of
±10 V the calculation is as follows.
CODE = 0:
VOUT 0
§
R3 ·
¨ VREF u
¸
R1 ¹
©
§
R3 ·
¨ 2.5V u
¸
R1 ¹
©
(5)
Setting the equation to minimum output span, VOUT(0) = –10 V, will reduce the equation to: R3/R1 = 4:
CODE = 4096:
Setting the equation to maximum output scan, VOUT(4096) = 10 V, and R3/R1 = 4 will reduce the equation to:
R3/R2 = 3
It is important to note that the maximum code of a 12-bit DAC is 4095; code 4096 was used to simplify the
equation above. For practical use, the true output span will encompass a range of –10 V to (10 V – 1 LSB),
which in this case is –10 V to 9.995 V.
38
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
9.2.3 Application Curve
The ±10 V output span with a reference voltage of 2.5 V can be achieved by using values of 30 kΩ, 10 kΩ, and
7.5 kΩ for R3, R2, and R1, respectively. A curve to illustrate this output span is shown in Figure 77. For this
example, 1% tolerance resistors were used in evaluating bipolar operation.
10
Output Voltage (V)
5
0
-5
-10
0
512
1024
1536 2048 2560
DAC Code
3072
3584
4096
D001
Figure 77. Bipolar Operation
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
39
DAC80504, DAC70504, DAC60504
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
www.ti.com
10 Power Supply Recommendations
The DACx0504 operates within the specified VDD supply range of 2.7 V to 5.5 V, and VIO supply range of 1.7 V to
5.5 V. The DACx0504 does not require specific supply sequencing.
The VDD supply must be well-regulated and low-noise. Switching power supplies and dc-dc converters often have
high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar
high-frequency spikes. This noise can easily couple into the DAC output voltage through various paths between
the power connections and analog output. In order to further minimize noise from the power supply, include a 1μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption on the VDD pin, the short-circuit
current limit, and the load current for the device is listed in the Electrical Characteristics. The power supply must
meet the aforementioned current requirements.
11 Layout
11.1 Layout Guidelines
A precision analog component requires careful layout, the list below provides some insight into good layout
practices.
• Bypass all power supply pins to ground with a low-ESR ceramic bypass capacitor. The typical recommended
bypass capacitance is 0.1-µF to 0.22-µF ceramic with a X7R or NP0 dielectric.
• Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize
performance.
• Use a high-quality ceramic type NP0 or X7R for its optimal performance across temperature, and very low
dissipation factor.
• The digital and analog sections must have proper placement with respect to the digital pins and analog pins
of the DACx0504 device. The separation of analog and digital blocks minimizes coupling into neighboring
blocks, as well as interaction between analog and digital return currents.
11.2 Layout Example
ANALOG SIDE
GND POUR
BYPASS CAPACITOR
4
BYPASS CAPACITORS
3
2
1
16
5
6
15
7
14
8
13
9
10
11 12
GND POUR
DIGITAL SIDE
Figure 78. DACx0504 Layout Example
40
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following: DACx0504 Evaluation Module User's Guide
12.2 Related Links
Table 19 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to order now.
Table 19. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC80504
Click here
Click here
Click here
Click here
Click here
DAC70504
Click here
Click here
Click here
Click here
Click here
DAC60504
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
41
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC60504BRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
654B
DAC60504BRTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
654B
DAC70504RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
70504
DAC70504RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
70504
DAC80504RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
(80504, 854)
DAC80504RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
(80504, 854)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
