DAC7621EBG4

® DAC DAC7621 ® 762 1 For most current data sheet and other product information, visit www.burr-brown.com 12-Bit, Parallel Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● LOW POWER: 2.5mW ● FAST SETTLING: 7µs to 1 LSB The DAC7621 is a 12-bit digital-to-analog converter (DAC) with guaranteed 12-bit monotonicity performance over the industrial temperature range. It requires a single +5V supply and contains an input register, latch, 2.435V reference, DAC, and high speed rail-to-rail output amplifier. For a full-scale step, the output will settle to 1 LSB within 7µs. The device consumes 2.5mW (0.5mA at 5V). ● 1mV LSB WITH 4.095V FULL-SCALE RANGE ● COMPLETE WITH REFERENCE ● 12-BIT LINEARITY AND MONOTONICITY OVER INDUSTRIAL TEMP RANGE ● ASYNCHRONOUS RESET TO 0V The parallel interface is compatible with a wide variety of microcontrollers. The DAC7621 accepts a 12-bit parallel word, has a double-buffered input logic structure and provides data readback. In addition, two control pins provide a chip select (CS) function and asynchronous clear (CLR) input. The CLR input can be used to ensure that the DAC7621 output is 0V on power-up or as required by the application. APPLICATIONS ● PROCESS CONTROL ● DATA ACQUISITION SYSTEMS ● CLOSED-LOOP SERVO-CONTROL ● PC PERIPHERALS ● PORTABLE INSTRUMENTATION The DAC7621 is available in a 20-lead SSOP package and is fully specified over the industrial temperature range of –40°C to +85°C. VDD Ref 12-Bit DAC VOUT 12 CLR DAC Register LOADDAC 12 Input Register 12 CS I/O Buffer R/W DAC7621 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation SBAS107 PDS-1502B Printed in U.S.A. March, 1999 SPECIFICATIONS ELECTRICAL At TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted. DAC7621E PARAMETER CONDITIONS RESOLUTION MIN DAC7621EB TYP MAX Guaranteed Monotonic Code 000H Code FFFH ANALOG OUTPUT Output Current Load Regulation Capacitive Load Short-Circuit Current Short-Circuit Duration Code 800H RLOAD ≥ 402Ω, Code 800H No Oscillation –2 –1 –1 4.079 ±1/2 ±1/2 +1 4.095 ±5 ±7 1 500 ±20 Indefinite GND or VDD DIGITAL INPUT Data Format Data Coding Logic Family Logic Levels VIH VIL IIH IIL TYP +2 +1 +3 4.111 ±1/4 ±1/4 ✻ 4.095 ✻ ✻ ✻ ✻ ✻ ✻ 3 ✻ ✻ ✻ +4.75 TEMPERATURE RANGE Specified Performance –40 +5.0 0.5 2.5 0.001 LSB LSB LSB V mA LSB pF mA +5.25 1 5 0.004 ✻ +85 ✻ ✻ ✻ ✻ ✻ V V µA µA µs nV-s nV-s ✻ ✻ ✻ 7 5 2 VIH = 5V, VIL = 0V, No Load, at Code 000H VIH = 5V, VIL = 0V, No Load ∆VDD = ±5% ✻ ✻ 0.3 • VDD ±10 ±10 POWER SUPPLY VDD IDD Power Dissipation Power Supply Sensitivity +1 +1 ✻ 4.103 ✻ ✻ ✻ 0.7 • VDD To ±1 LSB of Final Value UNITS Bits –1 –1 ✻ 4.087 Parallel Straight Binary CMOS DYNAMIC PERFORMANCE Settling Time(2) (tS) DAC Glitch Digital Feedthrough MAX ✻ 12 ACCURACY Relative Accuracy(1) Differential Nonlinearity Zero-Scale Error Full Scale Voltage MIN ✻ ✻ ✻ ✻ V mA mW %/% ✻ °C ✻ Same specification as for DAC7621E. NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7621 2 PIN CONFIGURATION PIN DESCRIPTIONS Top View PIN SSOP LABEL 1 CLR 1 20 LOADDAC VDD 2 19 CS VOUT 3 18 R/W AGND 4 17 DB0 (LSB) DGND 5 DB11 (MSB) DB10 16 DB1 6 15 DB2 7 14 DB3 DAC7621E DB9 8 13 DB4 DB8 9 12 DB5 DB7 10 11 DB6 DESCRIPTION CLR Reset. Resets the DAC register to zero. Active LOW. Asynchronous input. 2 VDD Postive Power Supply 3 VOUT DAC Output Voltage 4 AGND Analog Ground 5 DGND Digital Ground 6 DB11 Data Bit 11, MSB 7 DB10 Data Bit 10 8 DB9 Data Bit 9 9 DB8 Data Bit 8 10 DB7 Data Bit 7 11 DB6 Data Bit 6 12 DB5 Data Bit 5 13 DB4 Data Bit 4 14 DB3 Data Bit 3 15 DB2 Data Bit 2 16 DB1 Data Bit 1 17 DB0 Data Bit 0, LSB 18 R/W Read and Write Control 19 CS 20 LOADDAC ABSOLUTE MAXIMUM RATINGS(1) Chip Select. Active LOW. Loads the internal DAC register. The DAC register is a transparent latch and is transparent when LOADDAC is LOW (regardless of the state of CS or CLK). ELECTROSTATIC DISCHARGE SENSITIVITY VDD to GND .......................................................................... –0.3V to 6V Digital Inputs to GND .............................................. –0.3V to VDD + 0.3V VOUT to GND ........................................................... –0.3V to VDD + 0.3V Power Dissipation ........................................................................ 325mW Thermal Resistance, θJA ........................................................... 150°C/W Maximum Junction Temperature .................................................. +150°C Operating Temperature Range ...................................... –40°C to +85°C Storage Temperature Range ....................................... –65°C to +150°C Lead Temperature (soldering, 10s) .............................................. +300°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT MINIMUM RELATIVE ACCURACY (LSB) DIFFERENTIAL NONLINEARITY (LSB) SPECIFICATION TEMPERATURE RANGE PACKAGE PACKAGE DRAWING NUMBER(1) DAC7621E ±2 ±1 –40°C to +85°C 20-Lead SSOP 334 " " " " " " DAC7621EB ±1 ±1 –40°C to +85°C 20-Lead SSOP 334 " " " " " " ORDERING NUMBER(2) TRANSPORT MEDIA DAC7621E DAC7621E/1K DAC7621EB DAC7621EB/1K Rails Tape and Reel Rails Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7621E/1K” will get a single 1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ® 3 DAC7621 TIMING DIAGRAMS tWCS CS tWS tWH R/W tRCS CS tLWD tRDH tRDS LOADDAC R/W tDH tDS tDZ Data Out Data In Data Valid tCSD Data Output Timing Digital Input Timing TIMING SPECIFICATIONS LOGIC TRUTH TABLE TA = –40°C to +85°C SYMBOL DESCRIPTION tRCS CS LOW for Read MIN TYP MAX UNITS 200 ns tRDS R/W HIGH to CS LOW 10 ns tRDH R/W HIGH after CS HIGH 0 ns tDZ CS HIGH to Data Bus in High Impedance 100 tCSD CS LOW to Data Bus Valid tWCS CS LOW for Write 50 100 ns 160 tWS R/W LOW to CS LOW 0 ns tWH R/W LOW after CS HIGH 5 ns tDS Data Valid to CS LOW 0 ns tDH Data Valid after CS HIGH 5 ns tLWD LOADDAC LOW 50 ns ® DAC7621 4 DAC REGISTER L Write Write Write H Write Hold Write Input Read Hold Read Input Hold Update Update Hold Hold Hold CS L L L L H L H X H L X H H X = Don’t Care. ns INPUT REGISTER R/W LOADDAC MODE TYPICAL PERFORMANCE CURVES At TA = +25°, and VDD = 5V, unless otherwise specified. PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT OUTPUT SWING vs LOAD 1k 4.5 4.0 100 Delta VOUT (mV) Output Voltage (V) 3.5 3.0 2.5 2.0 1.5 1.0 85°C (mV) 25°C 10 1 –40°C 0.1 Data = 000H 0.5 0.01 0.001 0 10 100 1k 10k 100k 0.01 0.1 1 10 100 Current (mA) Load Resistance (Ω) SUPPLY CURRENT vs LOGIC INPUT VOLTAGE BROADBAND NOISE 4.0 Supply Current (mA) Noise Voltage (1mV/div) 3.5 Code = FFFH BW = 2MHz 3.0 2.5 2.0 1.5 1.0 0.5 0 5 Time (2µs/div) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Logic Voltage (V) POWER SUPPLY REJECTION vs FREQUENCY MINIMUM SUPPLY VOLTAGE vs LOAD 70 5.0 Data = FFFH VDD = 5V ±200mV AC 60 4.8 VDD Minimum (V) 50 PSR (dB) ∆VFS = 1 LSB Data = FFFH 40 30 20 4.6 4.4 4.2 10 0 10 100 1k 10k 100k 4.0 0.010 1M Frequency (Hz) 0.100 1.000 10.000 Output Load Current (mA) ® 5 DAC7621 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°, and VDD = 5V, unless otherwise specified. SUPPLY CURRENT vs TEMPERATURE SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE 4.0 80 Positive Current Limit Supply Current (mA) 40 VLOGIC = 3.5V Data = FFFH No Load 3.5 Data = 800H Output tied to ISOURCE 20 0 –20 –40 Negative Current Limit –60 3.0 2.5 2.0 VDD = 5.0V VDD = 5.25V 1.5 1.0 0.5 VDD = 4.75V 0 –80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 –40 –30 –20 –10 5.0 0 10 20 30 40 50 60 70 Output Voltage (V) Temperature (°C) MID-SCALE GLITCH PERFORMANCE MID-SCALE GLITCH PERFORMANCE LOADDAC 80 90 VOUT (2mV/div) VOUT (2mV/div) LOADDAC VOUT VOUT 7FFH to 800H 800H to 7FFH Time (500ns/div) Time (500ns/div) LARGE-SIGNAL SETTLING TIME RISE TIME DETAIL CL = 110pF RL = No Load Output Voltage (1mV/div) LD 1V/div Output Current (mA) 60 VOUT VOUT LD Time (10µs/div) Time (20µs/div) ® DAC7621 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°, and VDD = 5V, unless otherwise specified. OUTPUT VOLTAGE NOISE vs FREQUENCY FALL TIME DETAIL 10.000 Noise (µV/√Hz) Output Voltage (1mV/div) Data = FFFH VOUT LD 1.000 0.100 0.010 10 Time (10µs/div) 100 1k 10k 100k Frequency (Hz) LONG-TERM DRIFT ACCELERATED BY BURN-IN TOTAL UNADJUSTED ERROR HISTOGRAM 60 144 Units 6 T.U.E = ΣINL = ZS + FS Sample Size = 300 Units TA = +25°C 50 4 Number of Units Output Voltage Change (mV) 8 2 0 min –2 avg –4 40 30 20 max 10 –6 –8 0 200 400 600 800 1000 0 –12 1200 –8 –4 0 4 8 12 Hours of Operation at +150°C FULL-SCALE VOLTAGE vs TEMPERATURE ZERO-SCALE VOLTAGE vs TEMPERATURE 4.115 3 4.105 2 Zero-Scale (mV) Full-Scale Output (V) No Load Sample Size = 300 Avg + 3σ 4.110 4.100 4.095 Avg 4.090 4.085 1 0 4.080 Avg – 3σ 4.075 –1 –50 –25 0 25 50 75 100 125 –50 Temperature (°C) –25 0 25 50 75 100 125 Temperature (°C) ® 7 DAC7621 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°, and VDD = 5V, unless otherwise specified. DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE (at +25°C) LINEARITY ERROR vs DIGITAL CODE (at +25°C) 2.0 Differential Linearity Error (LSBs) 2.0 Linearity Error (LSBs) 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 0 512 1024 1536 2048 2560 3072 3584 0.5 0 –0.5 –1.0 –1.5 0 4096 512 1024 1536 2048 2560 3072 3584 4096 Code Code LINEARITY ERROR vs DIGITAL CODE (at +85°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE (at +85°C) 1 Differential Linearity Error (LSBs) 1 Linearity Error (LSBs) 1.0 –2.0 –2.0 0.5 0 –0.5 0.5 0 –0.5 –1.0 –1.0 0 512 1024 1536 2048 2560 3072 3584 0 4096 512 1024 1536 2048 2560 3072 3584 4096 Code Code LINEARITY ERROR vs DIGITAL CODE (at –40°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE (at –40°C) 1 Differential Linearity Error (LSBs) 1 Linearity Error (LSBs) 1.5 0.5 0 –0.5 –1.0 0.5 0 –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 Code 1024 1536 2048 Code ® DAC7621 512 8 2560 3072 3584 4096 OPERATION The digital data into the DAC7621 is double-buffered. This means that new data can be entered into the DAC without disturbing the old data and the analog output of the converter. At some point after the data has been entered into the serial shift register, this data can be transferred into the DAC register. This transfer is accomplished with a HIGH to LOW transition of the LOADDAC pin. However, the LOADDAC pin makes the DAC register transparent. If new data becomes available on the bus register while LOADDAC is LOW, the DAC output voltage will change as the data changes. To prevent this, CS must be returned HIGH prior to changing data on the bus. The DAC7621 is a 12-bit digital-to-analog converter (DAC) complete with an input shift register, DAC register, lasertrimmed 12-bit DAC, on-board reference, and a rail-to-rail output amplifier. Figure 1 shows the basic operation of the DAC7621. INTERFACE Figure 1 shows the basic connection between a microcontroller and the DAC7621. The interface consists of a Read/Write (R/W), data, and a load DAC signal (LOADDAC). In addition, a chip select (CS) input is available to enable the DAC7621 when there are multiple devices. The data format is Straight Binary. An asynchronous clear input (CLR) is provided to simplify start-up or periodic resets. Table I shows the relationship between input code and output voltage. At any time, the contents of the DAC register can be set to 000H (analog output equals 0V) by taking the CLR input LOW. The DAC register will remain at this value until CLR is returned HIGH and LOADDAC is taken LOW to allow the contents of the input register to be transferred to the DAC register. If LOADDAC is LOW when CLR is taken LOW, the DAC register will be set to 000H and the analog output driven to 0V. When CLR is returned HIGH, the DAC register and the analog output will respond accordingly. DAC7621 Full-Scale Range = 4.095V Least Significant Bit = 1mV DIGITAL INPUT CODE STRAIGHT OFFSET BINARY ANALOG OUTPUT (V) FFFH 801H 800H 7FFH 000H +4.095 +2.049 +2.048 +2.047 0 DESCRIPTION DIGITAL-TO-ANALOG CONVERTER Full Scale Midscale + 1 LSB Midscale Midscale – 1 LSB Zero Scale The internal DAC section is a 12-bit voltage output device that swings between ground and the internal reference voltage. The DAC is realized by a laser-trimmed R-2R ladder network which is switched by N-channel MOSFETs. The DAC output is internally connected to the rail-to-rail output operational amplifier. TABLE I. Digital Input Code and Corresponding Ideal Analog Output. DAC7621E Clear +5V 10µF + 0.1µF 0V to +4.095V Data Bus 1 CLR 2 3 4 5 6 7 LOADDAC 20 Load DAC VDD CS 19 Chip Select VOUT R/W 18 Read/Write AGND DB0 17 DGND DB1 16 DB11 DB2 15 DB10 DB3 14 8 DB9 DB4 13 9 DB8 DB5 12 10 DB7 DB6 11 Data Bus FIGURE 1. Basic Operation of the DAC7621. ® 9 DAC7621 R-2R DAC 2R Output Amplifier R Buffer 2R R2 2.435V Bandgap Reference R 2R R1 R 2R 2R FIGURE 2. Simplified Schematic of Analog Portion. OUTPUT AMPLIFIER A precision, low-power amplifier buffers the output of the DAC section and provides additional gain to achieve a 0V to 4.095V range. The amplifier has low offset voltage, low noise, and a set gain of 1.682V/V (4.095/2.435). See Figure 2 for an equivalent circuit schematic of the analog portion of the DAC7621. POWER SUPPLY A BiCMOS process and careful design of the bipolar and CMOS sections of the DAC7621 result in a very low power device. Bipolar transistors are used where tight matching and low noise are needed to achieve analog accuracy, and CMOS transistors are used for logic, switching functions and for other low power stages. If power consumption is critical, it is important to keep the logic levels on the digital inputs (R/W, CLK, CS, LOADDAC, CLR) as close as possible to either VDD or ground. This will keep the CMOS inputs (see “Supply Current vs Logic Input Voltages” in the Typical Performance Curves) from shunting current between VDD and ground. The DAC7621 power supply should be bypassed as shown in Figure 1. The bypass capacitors should be placed as close to the device as possible, with the 0.1µF capacitor taking priority in this regard. The “Power Supply Rejection vs Frequency” graph in the Typical Performance Curves section shows the PSRR performance of the DAC7621. This should be taken into account when using switching power supplies or DC/DC converters. The output amplifier has a 7µs typical settling time to ±1 LSB of the final value. Note that there are differences in the settling time for negative-going signals versus positivegoing signals. The rail-to-rail output stage of the amplifier provides the full-scale range of 0V to 4.095V while operating on a supply voltage as low as 4.75V. In addition to its ability to drive resistive loads, the amplifier will remain stable while driving capacitive loads of up to 500pF. See Figure 3 for an equivalent circuit schematic of the amplifier’s output driver and the Typical Performance Curves section for more information regarding settling time, load driving capability, and output noise. In addition to offering guaranteed performance with VDD in the 4.75V to 5.25V range, the DAC7621 will operate with reduced performance down to 4.5V. Operation between 4.5V and 4.75V will result in longer settling time, reduced performance, and current sourcing capability. Consult the “VDD vs Load Current” graph in the Typical Performance Curves section for more information. VDD P-Channel VOUT N-Channel AGND FIGURE 3. Simplified Driver Section of Output Amplifier. ® DAC7621 10 APPLICATIONS signals and should cross them at right angles. A solid analog ground plane around the D/A package, as well as under it in the vicinity of the analog and power supply pins, will isolate the D/A from switching currents. It is recommended that DGND and AGND be connected directly to the ground planes under the package. POWER AND GROUNDING The DAC7621 can be used in a wide variety of situations— from low power, battery operated systems to large-scale industrial process control systems. In addition, some applications require better performance than others, or are particularly sensitive to one or two specific parameters. This diversity makes it difficult to define definite rules to follow concerning the power supply, bypassing, and grounding. The following discussion must be considered in relation to the desired performance and needs of the particular system. If several DAC7621s are used, or if sharing supplies with other components, connecting the AGND and DGND lines together at the power supplies once, rather than at each chip, may produce better results. The power applied to VDD should be well regulated and lownoise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between VDD and VOUT. A precision analog component requires careful layout, adequate bypassing, and a clean, well-regulated power supply. As the DAC7621 is a single-supply, +5V component, it will often be used in conjunction with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good performance. The DAC7621 has separate analog ground and digital ground pins. The current through DGND is mostly switching transients and are up to 4mA peak in amplitude. The current through AGND is typically 0.5mA. As with the GND connection, VDD should be connected to a +5V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 10µF and 0.1µF capacitors shown in Figure 4 are strongly recommended and should be installed as close to VDD and ground as possible. In some situations, additional bypassing may be required such as a 100µF electrolytic capacitor or even a “Pi” filter made up of inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high frequency noise (see Figure 4). For best performance, separate analog and digital ground planes with a single interconnection point to minimize ground loops. The analog pins are located adjacent to each other to help isolate analog from digital signals. Analog signals should be routed as far as possible from digital Digital Circuits +5V Power Supply +5V +5V GND DAC7621 GND 100µF + + VDD 10µF 0.1µF AGND Optional DGND Other Analog Components FIGURE 4. Suggested Power and Ground Connections for a DAC7621 Sharing a +5V Supply with a Digital System with a Single Ground Plane. ® 11 DAC7621 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) DAC7621E ACTIVE SSOP DB 20 70 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 DAC7621E Samples DAC7621E/1K ACTIVE SSOP DB 20 1000 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 DAC7621E Samples DAC7621EB ACTIVE SSOP DB 20 70 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 DAC7621E B Samples DAC7621EBG4 ACTIVE SSOP DB 20 70 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 DAC7621E B Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of