DAC7634
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
16-BIT, QUAD VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
•
•
•
•
•
DESCRIPTION
Low Power: 10 mW
Unipolar or Bipolar Operation
Settling Time: 10 µs to 0.003%
15-Bit Linearity and Monotonicity:
–40°C to 85°C
Programmable Reset to Mid-Scale
or Zero-Scale
Double-Buffered Data Inputs
The DAC7634 is a 16-bit, quad voltage output, digitalto-analog converter with specified 15-bit monotonic
performance over the specified temperature range. It
accepts 24-bit serial input data, has double-buffered
DAC input logic (allowing simultaneous update of all
DACs), and provides a serial data output for
daisy-chaining
multiple
DACs.
Programmable
asynchronous reset clears all registers to a mid-scale
code of 8000H or to a zero-scale of 0000H. The
DAC7634 can operate from a single 5-V supply or
from 5-V and –5 V supplies.
APPLICATIONS
•
•
•
•
•
Low power and small size per DAC make the
DAC7634 ideal for automatic test equipment,
DAC-per-pin programmers, data acquisition systems,
and closed-loop servo-control. The DAC7634 is
available in a 48-lead SSOP package and offers
specifications over the –40°C to 85°C temperature
range.
Process Control
Closed-Loop Servo-Control
Motor Control
Data Acquisition Systems
DAC-Per-Pin Programmers
VDD
VSS
VREF L
AB Sense
VCC
VREFL AB
VREFH AB
VREF H
AB Sense
DAC7634
SDI
Shift
Register
Input
Register A
DAC
Register A
DAC A
SDO
VOUTA
VOUTA Sense
Input
Register B
DAC
Register B
DAC B
VOUTB
VOUTB Sense
CS
Input
Register C
DAC
Register C
Input
Register D
DAC
Register D
DAC C
VOUTC
CLOCK
RST
RESTSEL
LDAC
Control
Logic
VOUTC Sense
DAC D
VOUTD
LOAD
VOUTD Sense
AGND
DGND
VREF L
CD Sense
VREFL CD VREFH CD
VREF H
CD Sense
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
VCC and VDD to VSS
–0.3 V to 11 V
VCC and VDD to GND
–0.3 V to 5.5 V
VREFL to VSS
–0.3 V to (VCC - VSS)
VCC to VREFH
–0.3 V to (VCC - VSS)
VREFH to VREFL
–0.3 V to (VCC - VSS)
Digital input voltage to GND
–0.3 V to VDD + 0.3 V
Digital output voltage to GND
–0.3 V to VDD + 0.3 V
TJ
Maximum junction temperature
TA
Operating temperature range
–40°C to 85°C
150°C
Tstg
Storage temperature range
–65°C to 125°C
Lead temperature (solder, 10s)
(1)
300°C
Stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
SPECIFICATIONS
At TA = TMIN to TMAX, VDD = VCC = 5 V, VSS = –5 V, VREFH = 2.5 V, and VREFL = –2.5 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
DAC7634E
MIN
DAC7634EB
TYP
MAX
Linearity error
±3
±4
Linearity match
±4
Differential linearity error
±2
MIN
TYP
MAX
±2
±3
UNIT
ACCURACY
Monotonicity, TMIN to TMAX
±2
±3
14
Bipolar zero error
Bipolar zero error drift
Full-scale error
Full-scale error drift
LSB
LSB
±1
±2
15
LSB
Bits
±1
±2
±1
±2
mV
5
10
5
10
ppm/°C
±1
±2
±1
±2
mV
5
10
5
10
ppm/°C
Bipolar zero matching
Channel-to-channel
matching
±1
±2
±1
±2
mV
Full-scale matching
Channel-to-channel
matching
±1
±2
±1
±2
mV
Power supply rejection ratio (PSRR)
At full scale
10
100
10
100
2
ppm/V
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
SPECIFICATIONS (continued)
At TA = TMIN to TMAX, VDD = VCC = 5 V, VSS = –5 V, VREFH = 2.5 V, and VREFL = –2.5 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
DAC7634E
MIN
TYP
DAC7634EB
MAX
MIN
TYP
MAX
VREFL
VREFH
VREFL
VREFH
– 1.25
1.25
1.25
1.25
UNIT
ANALOG INPUT
Voltage output
Output current
VREF = –2.5 V, RL = 10 kΩ,
VSS = –5 V
Maximum load capacitance
No oscillation
500
Short-circuit current
Short-circuit duration
GND or VCC or VSS
V
mA
500
pF
–10, 30
–10, +30
mA
Indefinite
Indefinite
REFERENCE INPUT
Ref high input voltage range
Ref low input voltage range
VREFL
+1.25
2.5
VREFL
+1.25
2.5
V
–2.5
VREFH
– 1.25
–2.5
VREFH
– 1.25
V
Ref high input current
500
500
µA
Ref low input current
–500
–500
µA
DYNAMIC PERFORMANCE
Settling time
To ±0.003%, 5-V output step
Channel-to-channel crosstalk
See Figure 5
0.5
8
2
2
nV-s
Output noise voltage
f = 10 kHz
60
60
nV/√Hz
DAC glitch
7FFFH to 8000H or
8000H to 7FFFH
40
40
nV-s
Digital feedthrough
10
8
10
0.5
µs
LSB
DIGITAL INPUT
VIH
0.7 × VDD
0.7 × VDD
V
VIL
0.3 × VDD
0.3 × VDD
V
IIH
±10
±10
µA
IIL
±10
±10
µA
DIGITAL OUTPUT
VOH
IOH = –0.8 mA
VOL
IOL = 1.6 mA
3.6
4.5
3.6
0.3
0.4
4.5
V
0.3
0.4
V
POWER SUPPLY
VDD
4.75
5.0
5.25
4.75
5.0
5.25
V
VCC
4.75
5.0
5.25
4.75
5.0
5.25
V
VSS
–5.25
–5.0
–4.75
–5.25
–5.0
–4.75
1.5
2
1.5
2
ICC
IDD
ISS
Power
50
–2.3
–1.5
15
–2.3
20
V
mA
50
µA
–1.5
mA
15
20
mW
3
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
SPECIFICATIONS
At TA = TMIN to TMAX, VDD = VCC = 5 V, VSS = 0 V, VREFH = 2.5 V, and VREFL = 0 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
DAC7634E
MIN
DAC7634EB
TYP
MAX
Linearity error (1)
±3
±4
Linearity match
±4
Differential linearity error
±2
MIN
TYP
MAX
±2
±3
UNIT
ACCURACY
Monotonicity, TMIN to TMAX
±2
±3
14
Zero-scale error
Zero-scale error drift
Full-scale error
Full-scale error drift
LSB
LSB
±1
±2
15
LSB
Bits
±1
±2
±1
±2
mV
5
10
5
10
ppm/°C
±1
±2
±1
±2
mV
5
10
5
10
ppm/°C
mV
Zero-scale matching
Channel-to-channel matching
±1
±2
±1
±2
Full-scale matching
Channel-to-channel matching
±1
±2
±1
±2
mV
Power supply rejection ratio (PSRR)
At full scale
10
100
10
100
ppm/V
ANALOG INPUT
Voltage output
Output current
VREFL = 0 V, VSS = 0 V,
RL = 10 kΩ
Maximum load capacitance
No oscillation
0
VREFH
0
VREFH
– 1.25
1.25
–1.25
1.25
Short-circuit current
Short-circuit duration
GND or VCC
V
mA
500
500
pF
±30
±30
mA
Indefinite
Indefinite
REFERENCE INPUT
Ref high input voltage range
Ref low input voltage range
VREFL
+1.25
2.5
VREFL
+1.25
2.5
V
0
VREFH
–1.25
0
VREFH
–1.25
V
Ref high input current
250
250
µA
Ref low input current
–250
–250
µA
DYNAMIC PERFORMANCE
Settling time
To ±0.003%, 2.5-V output step
Channel-to-channel crosstalk
See Figure 6
0.5
8
2
2
nV-s
Output noise voltage
f = 10 kHz
60
60
nV/√Hz
DAC glitch
7FFFH to 8000H or
8000H to 7FFFH
40
40
nV-s
Digital feedthrough
10
8
10
0.5
µs
LSB
DIGITAL INPUT
VIH
0.7 × VDD
0.7 × VDD
V
VIL
0.3 × VDD
0.3 × VDD
V
IIH
±10
±10
µA
IIL
±10
±10
µA
DIGITAL OUTPUT
VOH
IOH = –0.8 mA
VOL
IOL = 1.6 mA
3.6
4.5
3.6
0.3
0.4
4.5
V
0.3
0.4
V
POWER SUPPLY
VDD
4.75
5.0
5.25
4.75
5.0
5.25
V
VCC
4.75
5.0
5.25
4.75
5.0
5.25
V
VSS
0
0
0
0
0
0
V
1.5
2
1.5
2
mA
10
7.5
10
mW
ICC
(1)
4
IDD
50
Power
7.5
50
If VSS = 0 V specification applies at Code 0040H and above due to possible negative zero-scale error.
µA
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
1
NC
No connection
25
VCC
Analog +5-V power supply
2
NC
No connection
26
VCC
Analog +5-V power supply
3
SDI
Serial data input
27
AGND
Analog ground
4
DGND
Digital ground
28
AGND
Analog ground
5
CLK
Data clock input
29
VSS
Analog +5-V power supply or 0-V single supply
6
DGND
Digital ground
30
VSS
Analog +5-V power supply or 0-V single supply
7
LDAC
DAC register load control, rising edge triggered
31
VOUTD
DAC D output voltage
8
DGND
Digital ground
32
VOUTD Sense
DAC D's output amplifier inverting input. Used to close
feedback loop at load.
9
LOAD
DAC input register load control, active low
33
VREFL CD Sense
DAC C and D reference low sense input
10
DGND
Digital ground
34
VREFL CD
DAC C and D reference low input
11
CS
Chip select, active low
35
VREFH CD
DAC C and D reference high input
12
DGND
Digital ground
36
VREFH CD Sense
DAC C and D reference high sense input
13
SDO
Serial data output
37
VOUTC
DAC C output voltage
14
DGND
Digital ground
38
VOUTC Sense
DAC C's output amplifier inverting input. Used to close
the feedback loop at the load.
15
RSTSEL
Reset Select. Determines the action of RST. If
HIGH, a RST common sets the DAC registers to
mid-scale (8000H). If LOW, a RST command sets
the DAC registers to zero (0000H).
39
VOUTB
DAC B output voltage
16
DGND
Digital ground
40
VOUTB Sense
DAC B's output amplifier inverting input. Used to close
the feedback loop at the load.
17
RST
Reset, rising edge triggered. Depending on the
state of RSTSEL, the DAC registers are set to
either mid-scale or zero.
41
VREFH AB Sense
DAC A and B reference high sense input
18
DGND
Digital ground
42
VREFH AB
DAC A and B reference high input
19
NC
No connection
43
VREFL AB
DAC A and B reference low input
20
NC
No connection
44
VREFL AB Sense
DAC A and B reference low sense input
21
DGND
Digital ground
45
VSS
Analog –5-V power supply or 0-V single supply
22
DGND
Digital ground
46
AGND
Analog ground
23
VDD
Digital 5-V power supply
47
VOUTA
DAC A output voltage
24
VDD
Digital 5-V power supply
48
VOUTA Sense
DAC A's output amplifier inverting input. Used to close
the feedback loop at the load.
5
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
PIN CONFIGURATION
1
48
VOUTA Sense
2
47
VOUTA
3
46
AGND
4
45
VSS
CLK
5
44
VREFL AB Sense
DGND
6
43
VREFL AB
LDAC
7
42
VREFH AB
DGND
8
41
VREFH AB Sense
LOAD
9
40
VOUTB Sense
DGND
10
39
VOUTB
CS
11
38
VOUTC Sense
DGND
12
37
VOUTC
NC
NC
SDI
DGND
DAC7634
6
SDO
13
36
VREFH CD Sense
DGND
14
35
VREFH CD
RSTSEL
15
34
VREFL CD
DGND
16
33
VREFL CD Sense
RST
17
32
VOUTD Sense
DGND
18
31
VOUTD
NC
19
30
VSS
NC
20
29
VSS
DGND
21
28
AGND
DGND
22
27
AGND
VDD
23
26
VCC
VDD
24
25
VCC
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = 0 V
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 25°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 25°C)
4000H 6000H 8000H
A000H C000H
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
E000H FFFFH
Digital Input Code
Figure 1.
Figure 2.
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 25°C)
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, 25°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
DLE (LSB)
LE (LSB)
Digital Input Code
4000H 6000H 8000H
A000H C000H
Digital Input Code
Figure 3.
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
E000H FFFFH
Digital Input Code
Figure 4.
7
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = 0 V (continued)
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 85°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 85°C)
4000H 6000H 8000H
A000H C000H
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
E000H FFFFH
Figure 5.
Figure 6.
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 85°C)
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, 85°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
4000H 6000H 8000H
A000H C000H
Digital Input Code
Figure 7.
8
A000H C000H
Digital Input Code
DLE (LSB)
DLE (LSB)
LE (LSB)
Digital Input Code
4000H 6000H 8000H
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
Digital Input Code
Figure 8.
E000H FFFFH
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = 0 V (continued)
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
4000H 6000H 8000H
A000H C000H
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
E000H FFFFH
Figure 9.
Figure 10.
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
LINEARY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
Digital Input Code
A000H C000H
E000H FFFFH
Digital Input Code
Figure 11.
Figure 12.
ZERO-SCALE ERROR vs TEMPERATURE
FULL-SCALE ERROR vs TEMPERATURE
2
2
Code (0040 H)
Positive Full−Scale Error (mV)
1.5
Zero−Scale Error (mV)
A000H C000H
Digital Input Code
DLE (LSB)
DLE (LSB)
LE (LSB)
Digital Input Code
1
DAC C
0.5
DAC A
0
–0.5
DAC D
–1
DAC B
–1.5
–2
1.5
Code (FFFFH)
1
DAC C
DAC A
0.5
0
–0.5
DAC B
DAC D
–1
–1.5
–2
–40 –30 –20 –10
0
10
20 30
40
50 60
70
80
90
–40 –30 –20 –10
0
10
20 30
40
Temperature − (°C)
Temperature − (°C)
Figure 13.
Figure 14.
50 60
70
80
90
9
DAC7634
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SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = 0 V (continued)
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
VREFL CURRENT vs CODE
(ALL DACs SENT TO INDICATED CODE)
0.30
0.00
0.25
–0.05
VREF Current (mA)
VREF Current (mA)
VREFH CURRENT vs CODE
(ALL DACs SENT TO INDICATED CODE)
0.20
0.15
0.10
–0.10
–0.15
–0.20
–0.25
0.05
–0.30
0.00
0000H 2000H
4000H 6000H 8000H
A000H C000H
0000H 2000H
E000H FFFFH
A000H C000H
Figure 15.
Figure 16.
POWER SUPPLY CURRENT
vs TEMPERATURE
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
2
E000H FFFFH
2
No Load
Data = FFFFH(all DACs)
No Load
1.5
1.5
I CC (mA)
ICC (mA)
4000H 6000H 8000H
Digital Input Code
Digital Input Code
1
0.5
All DACs
1
One DAC
0.5
0
0
–40 –30 –20 –10
0
10
20 30
40
5060
70
80
90
0000H 2000H 4000H 6000H
Temperature 〈°C)
8000H A000H C000H E000H FFFF H
Digital Input Code
Figure 17.
Figure 18.
OUTPUT VOLTAGE vs SETTLING TIME
(0 V TO 2.5 V)
OUTPUT VOLTAGE vs SETTLING TIME
(2.5 V TO 2 mV)
+5V
LDAC
0
+5V
LDAC
0
Small−Signal Settling Time: 4LSB/div
Output Voltage
Output Voltage
Large−Signal Settling Time: 0.5V/div
Small−Signal Settling Time: 4LSB/div
Large−Signal Settling Time: 0.5V/div
Time (2 µs/div)
Figure 19.
10
Time (2 µs/div)
Figure 20.
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = 0 V (continued)
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
OUTPUT VOLTAGE
vs MIDSCALE GLITCH PERFORMANCE
+5V
LDAC
0
Output Voltage (50mV/div)
Output Voltage (50mV/div)
+5V
LDAC
0
7FFFH to 8000 H
8000H to 7FFFH
Time (1 µs/div)
Time (1 µs/div)
Figure 21.
Figure 22.
BROADBAND NOISE
OUTPUT NOISE VOLTAGE vs FREQUENCY
Noise (nV/ Hz)
Noise Voltage (50µV/div)
1000
100
H
10
10
Time (10µs/div)
100
1000
10000
100000
1000000
Frequency (Hz)
Figure 23.
Figure 24.
VOUT
vs
RLOAD
5
VOUT (V)
4
3
Source
2
1
Sink
0
0.001
0.01
0.1
1
10
100
1000
RLOAD (kΩ)
Figure 25.
11
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = –5 V
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 25°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 25°C)
4000H 6000H 8000H
A000H C000H
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
A000H C000H
Figure 27.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, 25°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
4000H 6000H 8000H
A000H C000H
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
Digital Input Code
Figure 28.
12
E000H FFFFH
Figure 26.
DLE (LSB)
LE (LSB)
DLE (LSB)
4000H 6000H 8000H
Digital Input Code
Digital Input Code
Figure 29.
E000H FFFFH
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = –5 V (continued)
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 85°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 85°C)
4000H 6000H 8000H
A000H C000H
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
A000H C000H
E000H FFFFH
Digital Input Code
Figure 30.
Figure 31.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, 85°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, 85°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
DLE (LSB)
LE (LSB)
Digital Input Code
4000H 6000H 8000H
4000H 6000H 8000H
A000H C000H
Digital Input Code
Figure 32.
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
E000H FFFFH
Digital Input Code
Figure 33.
13
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = –5 V (continued)
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, –40°C)
DLE (LSB)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, –40°C)
0000H 2000H
4000H 6000H 8000H
A000H C000H
E000H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
A000H C000H
E000H FFFFH
Figure 35.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, –40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, –40°C)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
Figure 36.
E000H FFFFH
LE (LSB)
Figure 34.
Digital Input Code
14
4000H 6000H 8000H
Digital Input Code
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
DLE (LSB)
LE (LSB)
Digital Input Code
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
Digital Input Code
Figure 37.
E000H FFFFH
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = –5 V (continued)
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
VREFl CURRENT vs CODE
(ALL DACs SENT TO INDICATED CODE)
+0.6
0.0
+0.5
–0.1
VREF Current (mA)
VREF Current (mA)
VREFH CURRENT vs CODE
(ALL DACs SENT TO INDICATED CODE)
+0.4
+0.3
+0.2
+0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
0000H 2000H
E000H FFFFH
4000H 6000H 8000H
E000H FFFFH
Figure 38.
Figure 39.
ZERO-SCALE ERROR vs TEMPERATURE
(Code 8000H)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFFH)
2
2
1.5
1.5
1
DAC A
0.5
DAC B
0
–0.5
DAC D
–1
DAC C
–1.5
–2
1
DAC B
DAC A
0.5
0
–0.5
DAC C
–1
DAC D
–1.5
–2
–40 –30 –20 –10
0
10
20 30
40
50 60
70
80
90
–40 –30 –20 –10
0
Temperature − (°C)
10
20 30
40
50 60
70
80
90
Temperature − (°C)
Figure 40.
Figure 41.
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 0000H)
POWER SUPPLY CURRENT
vs TEMPERATURE
3
2
1.5
2
Data = FFFFH (all DACs)
No Load
1
DAC B
ICC
1
0.5
DAC C
I Q (mA)
Negative Full−Scale Error (mV)
A000H C000H
Digital Input Code
Positive Full−Scale Error (mV)
Zero−Scale Error (mV)
Digital Input Code
0
–0.5
0
I SS
–1
DAC A
–1
DAC D
–2
–1.5
–2
–3
–40 –30 –20 –10
0
10
20 30
40
Temperature − (°C)
Figure 42.
50 60
70
80
90
–40 –30 –20 –10
0
10
20 30
40
50 60
70
80
90
Temperature − (°C)
Figure 43.
15
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
TYPICAL PERFORMANCE CURVES: VSS = –5 V (continued)
At TA = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.
VOUT vs RLOAD
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
2
No Load
Source
ICC (mA)
VOUT (V)
1.5
All DACs
One DAC
1
Sink
–2
0.5
–3
–4
–5
0.001
0
0.01
0.1
1
10
100
1000
0000H 2000H 4000H
RLOAD (kΩ)
8000H A000H C000H E000H FFFFH
Digital Input Code
Figure 44.
Figure 45.
OUTPUT VOLTAGE vs SETTLING TIME
(–2.5 V TO 2.5 V)
OUTPUT VOLTAGE vs SETTLING TIME
(2.5 V TO –2.5 V)
+5V
LDAC
0
+5V
LDAC
0
Small−Signal Settling Time: 2LSB/div
Output Voltage
Large−Signal Settling Time: 1V/div
Output Voltage
6000H
Small−Signal Settling Time:
2LSB/div
Large−Signal Settling Time: 1V/div
Time (2 µs/div)
Time (2 µs/div)
Figure 46.
Figure 47.
THEORY OF OPERATION
The DAC7634 is a quad voltage output, 16-bit
digital-to-analog converter (DAC). The architecture is
an R-2R ladder configuration with the three MSBs
segmented, followed by an operational amplifier that
serves as a buffer. Each DAC has its own R-2R
ladder network, segmented MSBs, and output
operational amplifier, as shown in Figure 48. The
minimum voltage output (zero-scale) and maximum
voltage output (full-scale) are set by the external
voltage references (VREFL and VREFH, respectively).
16
The digital input is a 24-bit serial word that contains a
2-bit address code for selecting one of four DACs, a
quick load bit, five unused bits, and the 16-bit DAC
code (MSB first). The converters can be powered
from either a single 5-V supply or a dual ±5-V supply.
The device offers a reset function which immediately
sets all DAC output voltages and DAC registers to
mid-scale code 8000H or to zero-scale, code 0000H.
See Figure 49 and Figure 50 for the basic operation
of the DAC7634.
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
RF
VOUT Sense
VOUT
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREFH
VREFH Sense
VREFL
VREFL Sense
Figure 48. DAC7634 Architecture
Serial Data In
Clock
Load DAC Registers
Load
Chips Select
Serial Data Out
Reset DAC Registers
1
NC
VOUTA Sense
48
2
NC
VOUTA
47
3
SDI
AGND
46
4
DGND
5
CLK
6
VSS
45
VREFL AB Sense
44
DGND
VREFL AB
43
7
LDAC
VREFH AB
42
8
DGND
VREFH AB Sense
41
9
LOAD
VOUTB Sense
40
10
DGND
VOUTB
39
11
CS
VOUTC Sense
38
12
DGND
13
SDO
14
15
16
DGND
17
RST
18
DGND
19
20
21
DAC7634
VOUTC
37
VREFH CD Sense
36
DGND
VREFH CD
35
RSTSEL
VREFL CD
34
VREFL CD Sense
33
VOUTD Sense
32
VOUTD
31
NC
VSS
30
NC
VSS
29
DGND
AGND
28
22
DGND
AGND
27
23
VDD
VCC
26
24
VDD
VCC
25
0V to +2.5V
+2.5000V
0V to +2.5V
0V to +2.5V
+2.5000V
0V to +2.5V
0.1∝F
1∝
+5V
NC = No Connection
Figure 49. Basic Single-Supply Operation of the DAC7634
17
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
Serial Data In
Clock
Load DAC Registers
Load
Chips Select
Serial Data Out
+5V
Reset DAC Registers
1 µF
+5V
0.1 µF
1
NC
VOUTA Sense
48
2
NC
VOUTA
47
3
SDI
AGND
46
4
DGND
5
CLK
6
–2.5V to +2.5V
–5V
VSS
45
VREFL AB Sense
44
DGND
VREFL AB
43
–2.5V
7
LDAC
VREFH AB
42
+2.5V
8
DGND
VREFH AB Sense
41
9
LOAD
VOUTB Sense
40
10
DGND
VOUTB
39
11
CS
VOUTC Sense
38
12
DGND
13
SDO
14
15
16
DGND
17
RST
18
DGND
19
NC
20
NC
21
DAC7634
VOUTC
37
VREFH CD Sense
36
DGND
VREFH CD
35
RSTSEL
VREFL CD
34
VREFL CD Sense
33
VOUTD Sense
32
VOUTD
31
VSS
30
VSS
29
DGND
AGND
28
22
DGND
AGND
27
23
VDD
VCC
26
24
VDD
VCC
25
–2.5V to +2.5V
–2.5V to +2.5V
+2.5V
–2.5V
–2.5V to +2.5V
–5V
0.1 µF
+
1 µF
0.1 µF
+
1 µF
+5V
NC = No Connection
Figure 50. Basic Dual-Supply Operation of the DAC7634
ANALOG OUTPUTS
When VSS = –5V (dual supply operation), the output
amplifier can swing to within 2.25 V of the supply
rails, specified over the –40°C to 85°C temperature
range. When VSS = 0 V (single-supply operation), and
with RLOAD also connected to ground, the output can
swing to ground. Care must also be taken when
measuring the zero-scale error when VSS = 0 V.
Because the output voltage cannot swing below
ground, the output voltage may not change for the
first few digital input codes (0000H, 0001H, 0002H,
etc.) if the output amplifier has a negative offset. At
the negative limit of –2 mV, the first specified output
starts at code 0040H.
Due to the high accuracy of these D/A converters,
system design problems such as grounding and
contact resistance become important. A 16-bit
18
converter with a 2.5 V full-scale range has a 1-LSB
value of 38 µV. With a load current of 1 mA, series
wiring and connector resistance of only 40 mΩ (RW2)
causes a voltage drop of 40 µV, as shown in
Figure 51. To understand what this means in terms of
a system layout, the resistivity of a typical 1-ounce
copper-clad printed-circuit board is 1.2 mΩ per
square. For a 1-mA load, a 10-mil wide printed-circuit
conductor 600 mil long results in a voltage drop of 30
µV.
The DAC7634 offers a force and sense output
configuration for the high open-loop gain output
amplifier. This feature allows the loop around the
output amplifier to be closed at the load (as shown in
Figure 51), thus ensuring an accurate output voltage.
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
RW1
VOUTA Sense
48
VOUTA
47
AGND
46
VSS
45
VREFL AB Sense
44
VREFL AB
43
VREFH AB
42
VREFH AB Sense
41
VOUTB Sense
40
VOUTB
39
DAC7634
RW2
VOUT
+V
+2.5V
RW1
RW2
VOUT
Figure 51. Analog Output Closed-Loop
Configuration(1/2 DAC7634)
(RW Represents Wiring Resistances)
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any
voltage between VSS + 2.5 V and VCC – 2.5 V,
provided that VREFH is at least 1.25 V greater than
VREFL. The minimum output of each DAC is equal to
VREFL plus a small offset voltage (essentially, the
offset of the output operational amp). The maximum
output is equal to VREFH plus a similar offset voltage.
Note that VSS (the negative power supply) must either
be connected to ground or must be in the range of
–4.75 V to –5.25 V. The voltage on VSS sets several
bias points within the converter. If VSS is not in one of
these two configurations, the bias values may be in
error and proper operation of the device is not
specified.
The current into the VREFH input and out of VREFL
depends on the DAC output voltages, and can vary
from a few microamps to approximately 0.5 mA. The
reference input appears as a varying load to the
reference. If the reference can sink or source the
required current, a reference buffer is not required.
The DAC7634 features a reference drive and sense
connection such that the internal errors caused by the
changing reference current and the circuit
impedances can be minimized. Figure 52 through
Figure 60 show different reference configurations,
and the effect on the linearity and differential linearity.
+V
VOUTA Sense
48
VOUTA
47
AGND
46
VSS
45
VREFL AB Sense
44
VREFL AB
43
VREFH AB
42
VREFH AB Sense
41
VOUTB Sense
40
VOUTB
39
DAC7634
OPA2234
VOUT
100Ω
2200pF
–2.5V
–5V
–V
1000pF
+V
100Ω
1000pF
+2.5V
2200pF
VOUT
–V
Figure 52. Dual Supply Configuration-Buffered References, Used for Dual Supply Performance
19
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
+V
VOUTA Sense
48
VOUTA
47
AGND
46
VSS
45
VREFL AB Sense
44
VREFL AB
43
VREFH AB
42
VREFH AB Sense
41
VOUTB Sense
40
VOUTB
39
DAC7634
OPA2350
VOUT
2kΩ
2200pF
100Ω
+0.050V
+V
98kΩ
1000pF
+2.5V
100Ω
1000pF
2200pF
VOUT
NOTE: V REFL has been chosen to be 50 mV to allow for current sinking voltage
drops across the 100-Ω resistor and the output stage of the buffer operational amplifier.
0000H 2000H
4000H 6000H 8000H
A000H C000H
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
Figure 53. Single-Supply Buffered Reference With a Reference Low of 50 mV (1/2 DAC7634)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
E000H FFFFH
4000H 6000H 8000H
A000H C000H
E000H FFFF H
Digital Input Code
Digital Input Code
Figure 54. Integral Linearity and Differential Linearity
Error Curves for Figure 53
Figure 55. Integral Linearity and Differential Linearity
Error Curves for Figure 56
+V
VOUTA Sense
48
VOUTA
47
AGND
46
VSS
45
VREFL AB Sense
44
VREFL AB
43
VREFH AB
42
VREFH AB Sense
41
VOUTB Sense
40
VOUTB
39
DAC7634
OPA2350
VOUT
100Ω
+V
2200pF
1000pF
+1.25V
+V
100Ω
1000pF
2200pF
+2.5V
VOUT
Figure 56. Single-Supply Buffered Reference With VREFL = 1.25 V and VREFH = 2.5 V (1/2 DAC7634)
20
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
VOUTA Sense
48
VOUTA
47
AGND
46
VSS
45
VREFL AB Sense
44
VREFL AB
43
VREFH AB
42
VREFH AB Sense
41
VOUTB Sense
40
VOUTB
39
DAC7634
VOUT
+V
+V
OPA2350
+2.5V
100Ω
1000pF
2200pF
VOUT
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
LE (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DLE (LSB)
Figure 57. Single-Supply Buffered VREFH (1/2 DAC7634)
0000H 2000H
4000H 6000H 8000H
A000H C000H
E000H FFFF H
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H
4000H 6000H 8000H
A000H C000H
E000H FFFF H
Digital Input Code
Digital Input Code
Figure 58. Linearity and Differential Linearity
Error Curves for Figure 57
Figure 59. Linearity and Differential Linearity
Error Curves for Figure 60
VOUTA Sense
48
VOUTA
47
AGND
46
VSS
45
VREFL AB Sense
44
VREFL AB
43
VREFH AB
42
VREFH AB Sense
41
VOUTB Sense
40
VOUTB
39
DAC7634
VOUT
+V
+2.5V
VOUT
Figure 60. Low Cost Single-Supply Configuration
21
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
DIGITAL INTERFACE
The DAC code, quick load control, and address are
provided via a 24-bit serial interface (see Figure 15).
The first two bits select the input register that is
updated when LOAD goes LOW. The third bit is a
Quick Load bit such that if HIGH, the code in the shift
register is loaded into ALL DAC's input register when
LOAD signal goes LOW. If the Quick Load bit is
LOW, the content of shift register is loaded only to
the DAC input register that is addressed. The Quick
Load bit is followed by five unused bits. The last
sixteen bits (MSB first) are the DAC code.
Table 1 shows the basic control logic for the
DAC7634. The interface consists of a signal data
clock (CLK) input, serial data (SDI), DAC input
register load control signal (LOAD), and DAC register
load control signal (LDAC). In addition, a chip select
(CS) input is available to enable serial communication
when there are multiple serial devices. An
asynchronous reset (RST) input, by the rising edge,
is provided to simplify start-up conditions, periodic
resets, or emergency resets to a known state,
depending on the status of the reset select (RSTSEL)
signal.
SERIAL DATA INPUT
B23
A1
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
A0
QUICK
LOAD
X
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 1. DAC7634 Logic Truth Table (1)
A0
CS
RST
RSTSEL
LDAC
LOAD
INPUT
REGISTER
DAC
REGISTER
MODE
DAC
L
L
L
H
X
X
L
Write
Hold
Write Input
A
L
H
L
H
X
X
L
Write
Hold
Write Input
B
H
L
L
H
X
X
L
Write
Hold
Write Input
C
H
H
L
H
X
X
L
Write
Hold
Write Input
D
X
X
H
H
X
↑
H
Hold
Write
Update
All
X
X
H
H
X
H
H
Hold
Hold
Hold
All
X
X
X
↑
L
X
X
Reset to Zero
Reset to Zero
Reset to Zero
All
X
X
X
↑
H
X
X
Reset to Midscale
Reset to Midscale
Reset to Midscale
All
A1
(1)
If the DAC7634 is the only device on the serial bus, the CS pin can be connected to DGND permanently, which enables the shift register
all the time. In this case, only the CLK operates the serial shift register and all other functions listed in Table 1 should be followed as
shown. The DAC updates on the rising edge of LDAC.
The internal DAC register is edge-triggered and not
level-triggered. When the LDAC signal is transitioned
from LOW to HIGH, the digital word currently in the
DAC input register is latched. The first set of registers
(the DAC input registers) are level-triggered via the
LOAD signal. This double-buffered architecture has
been designed so that new data can be entered for
each DAC without disturbing the analog outputs.
When the new data has been entered into the device,
all of the DAC outputs can be updated simultaneously
by the rising edge of LDAC. Additionally, it allows the
DAC input registers to be written to at any point, then
the DAC output voltages can be synchronously
changed via a trigger signal (LDAC).
Note that CS and CLK are combined with an OR
22
gate, which controls the serial-to-parallel shift
register. These two inputs are completely
interchangeable. In addition, care must be taken with
the state of CLK when CS rises at the end of a serial
transfer. If CLK is LOW when CS rises, the OR gate
provides a rising edge to the shift register, shifting the
internal data one additional bit. The result will be
incorrect data and possible selection of the wrong
input register(s). If both CS and CLK are used, CS
should rise only when CLK is HIGH. If not, then either
CS or CLK can be used to operate the shift register.
See Table 2 for more information.
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
SERIAL-DATA OUTPUT
Table 2. Serial Shift Register Truth Table
CLK (1)
LOAD
RST
SERIAL SHIFT REGISTER
H (2)
X (3)
H
H
No Change
L (4)
L
H
H
No Change
L
↑ (5)
H
H
Advanced One Bit
↑
L
H
H
Advanced One Bit
H (6)
X
L (7)
H
No Change
H
↑ (8)
No Change
CS
(1)
H (6)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
X
CS and CLK are interchangeable.
H = Logic HIGH
X = Don't Care
L = Logic LOW
Positive logic transition
A HIGH value is suggested in order to avoid a false clock from advancing the shift register and
changing the shift register.
If data is clocked into the serial register while LOAD is LOW, the selected DAC register changes as
the shift register bits flow through A1 and A0. This corrupts the data in each DAC register that has
been erroneously selected.
Rising edge of RST causes no change in the contents of the serial shift register.
The Serial-Data Output (SDO) is the internal shift
register's output. For DAC7634, the SDO is a driven
output and does not require an external pull-up. Any
number of DAC7634s can be daisy-chained by
connecting the SDO pin of one device to the SDI pin
of the following device in the chain, as shown in
Figure 61.
SOURCE
DIGITAL INPUT CODING
The DAC7634 offers a unique set of features that
allows a wide range of flexibility in designing
applications circuits such as programmable current
sources. The DAC7634 offers both a differential
reference input, as well as an open-loop configuration
around the output amplifier. The open-loop
configuration around the output amplifier allows a
transistor to be placed within the loop to implement a
digitally- programmable, unidirectional current source.
The availability of a differential reference allows
programmability for both the full-scale and zero-scale
currents. The output current is calculated as:
The DAC7634 input data is in straight binary format.
The output voltage is given by Equation 1.
I
DIGITAL TIMING
Figure 62 and Table 3 provide detailed timing for the
digital interface of the DAC7634.
Where N is the digital input code. This equation does
not include the effects of offset (zero-scale) or gain
(full-scale) errors.
V
OUT
V
REF
L
VREFH VREFL
OUT
V
V
HV
L
REF
REF
R
SENSE
REF
LR
SENSE
65,N536
(2)
N
65, 536
(1)
DIGITALLY-PROGRAMMABLE CURRENT
23
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
DAC7634
SCK
CLK
DIN
SDI
CS
CS
DAC7634
DAC7634
CLK
SDO
SDI
CLK
SDO
SDO
SDI
CS
To
Other
Serial
Devices
CS
Figure 61. Daisy-Chaining DAC7634
(LSB)
(MSB)
SDI
A1
A0
QUICK
LOAD
X
X
X
XX
D15
D1
D0
CLK
tcss
t CSH
tLD1
tLD2
CS
tLDDD
LOAD
tLDRW
LDAC
Figure 62. Serial Interface Timing
tDS
t DH
SDI
t CL
tCH
CLK
Figure 63. Data and Clock Timing
tLDDL
tLDDH
LDAC
tS
VOUT
tS
±1 LSB
ERROR BAND
tRSTL
±1 LSB
ERROR BAND
tRSTH
RESET
tRSSH
tRSSS
RESETSEL
Figure 64. Reset and Output Timing
24
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
Table 3. Timing Specifications (TA = –40°C to 85°C)
SYMBOL
DESCRIPTION
MIN
UNITS
tDS
Data Valid to CLK Rising
10
ns
tDH
Data Held Valid after CLK Rises
20
ns
tCH
CLK HIGH
25
ns
tCL
CLK LOW
25
ns
tCSS
CS LOW to CLK Rising
15
ns
tCSH
CLK HIGH to CS Rising
0
ns
tLD1
LOAD HIGH to CLK Rising
10
ns
tLD2
CLK Rising to LOAD LOW
30
ns
tLDRW
LOAD LOW Time
30
ns
tLDDL
LDAC LOW Time
100
ns
tLDDH
LDAC HIGH Time
150
ns
tLDDD
LDAC Rising from LOAD LOW
40
ns
tRSSS
RESETSEL Valid to RESET HIGH
0
ns
tRSSH
RESET HIGH to RESETSEL Not Valid
100
ns
tRSTL
RESET LOW Time
10
ns
tRSTH
RESET HIGH Time
10
ns
tS
Settling Time
10
µs
Figure 65 shows a DAC7634 in a 4-mA to 20-mA current output configuration. The output current can be
determined by Equation 3:
I
OUT
0.5 V
125
2.5 V 0.5 V
N
125
65, 536
(3)
At full-scale, the output current is 16 mA, plus the 4 mA, for the zero current. At zero scale, the output current is
the offset current of 4 mA (0.5 V/125 Ω).
25
DAC7634
www.ti.com
SBAS134B – JULY 2004 – REVISED DECEMBER 2005
I OUT
VPROGRAMMED
125Ω
VOUTA Sense
48
VOUTA
47
AGND
46
VSS
45
VREFL AB Sense
44
VREFL AB
43
VREFH AB
42
VREFH AB Sense
41
VOUTB Sense
40
VOUTB
39
DAC7634
+V
OPA2350
2200pF
100Ω
20kΩ
+V
80kΩ
1000pF
+2.5V
100Ω
1000pF
2200pF
IOUT
VPROGRAMMED
125Ω
GND
Figure 65. 4 mA to 20 mA Digitally Controlled Current Source (1/2 DAC7634)
26
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC7634E
ACTIVE
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7634E
B
DAC7634E/1K
ACTIVE
SSOP
DL
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7634E
B
DAC7634EB
ACTIVE
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7634E
B
DAC7634EBG4
ACTIVE
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7634E
B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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