DIT4192
DIT41
92
SBOS229B – DECEMBER 2001 – REVISED JUNE 2003
192kHz Digital Audio Transmitter
FEATURES
APPLICATIONS
● COMPLIANT WITH AES-3, IEC-60958, AND EIAJ
CP1201 INTERFACE STANDARDS
● SUPPORTS SAMPLING RATES UP TO 192kHz
● SUPPORTS MONO-MODE OPERATION
● ON-CHIP DIFFERENTIAL LINE DRIVER
● FLEXIBLE AUDIO SERIAL INTERFACE:
-Master or Slave Mode Operation
-Supports I2S, Left-Justified, and Right-Justified
Data Formats
● SOFTWARE MODE VIA SERIAL CONTROL
INTERFACE:
-Block Sized Buffer for Channel Status Data
-Auto Increment Mode for Block Sized Write and
Read Operations
● HARDWARE MODE ALLOWS OPERATION
WITHOUT A MICROCONTROLLER
● CRC CODE GENERATION FOR PROFESSIONAL
MODE
● MASTER CLOCK RATE: 128fS, 256fS, 384fS, or 512fS
● +5V CORE SUPPLY (VDD)
● +2.7V TO VDD LOGIC I/O SUPPLY (VIO)
● PACKAGE: TSSOP-28
●
●
●
●
●
●
●
●
●
DIGITAL MIXING CONSOLES
DIGITAL MICROPHONES
DIGITAL AUDIO WORKSTATIONS
BROADCAST STUDIO EQUIPMENT
EFFECTS PROCESSORS
SURROUND-SOUND DECODERS AND ENCODERS
A/V RECEIVERS
DVD, CD, DAT, AND MD PLAYERS
AUDIO TEST EQUIPMENT
DESCRIPTION
The DIT4192 is a digital audio transmitter designed for use
in both professional and consumer audio applications. Transmit data rates up to 192kHz are supported. The DIT4192
supports both software and hardware operation, which makes
it suitable for applications with or without a microcontroller. A
flexible serial audio interface is provided, supporting standard audio data formats and easy interfacing to audio DSP
serial ports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2001-2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
Power-Supply Voltage, VDD .............................................................. +6.5V
VIO ............................................................... +6.5V
Input Current ................................................................................... ±10mA
Digital Input Voltage .......................................................... –0.2V to +5.5V
Digital Output Voltage ............................................ –0.2V to (VDD + 0.2V)
Power Dissipation .......................................................................... 300mW
Operating Temperature Range ...................................... –40°C to + 85°C
Storage Temperature ..................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR re-flow, 10s) ........................................ +235°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied.
PACKAGE/ORDERING INFORMATION
PRODUCT
DIT4192
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
TSSOP-28
PW
–40°C to +85°C
DIT4192IPW
"
"
"
"
DIT4192IPW
DIT4192IPWR
Rails, 50
Tape and Reel, 2000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
2
DIT4192
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SBOS229B
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, VDD = +5V, and VIO = 3.3V unless otherwise noted.
DIT4192IPW
PARAMETER
DIGITAL CHARACTERISTICS
Applies to All Digital I/O Except TX+ and TX–
High-Level Input Voltage, VIH
Low-Level Input Voltage, VIL
High-Level Output Voltage, VOH
Low-Level Output Voltage, VOL
Input Leakage Current
OUTPUT DRIVER CHARACTERISTICS
Applies Only to TX+ and TX–
High-Level Output Voltage, VOH
Low-Level Output Voltage, VOL
SWITCHING CHARACTERISTICS
Master Clock and Reset
Master Clock (MCLK) Frequency
Master Clock (MCLK) Duty Cycle
Reset (RST) Active Low Pulse Width
Serial Control Port Timing
CCLK Frequency
Stereo Mode
Mono Mode
Serial Control Data Setup Time, tSDS
Serial Control Data Hold Time, tSDH
CS Falling to CCLK Rising, tCSCR
CCLK Falling to CS Rising, tCFCS
CCLK Falling to CDOUT Data Valid, tCFDO
CS Rising to CDOUT High Impedance, tCSZ
Audio Serial Interface Timing
SYNC Frequency (or Frame Rate)
SYNC Clock Period tSYNCP
SYNC High/Low Pulse Width, tSYNCHL
SCLK Frequency
SCLK Clock Period, tSCLKP
SCLK High/Low Pulse Width, tSCLKHL
SYNC Edge to SCLK Edge, tSYSK
Audio Data Setup Time, tADS
Audio Data Hold Time, tADH
C, U, and V Input Timing
C/U/V Data Setup Time, tCUVS
C/U/V Data Hold Time, tCUVH
CONDITIONS
MIN
IO = –4mA
IO = +4mA
0.7 • VIO
0
0.8 • VIO
0
IO = –30mA
IO = +30mA
Power Dissipation
PD, Quiescent
PD, Power-Down Mode
PD, Dynamic (at 192kHz operation)
UNITS
VIO
0.2 • VIO
1
0.1 • VIO
10
VDD – 0.4
0.4
VDD
0.7
V
V
25
60
MHz
%
ns
128 • fS
64 • fS
MHz
MHz
ns
ns
ns
ns
ns
ns
fS = Sampling Frequency
fS = Sampling Frequency
12
8
15
12
12
10
195.3050
40
18
15
15
15
kHz
µs
µs
MHz
ns
ns
ns
ns
ns
15
15
ns
ns
5.12
2.56
25
+4.5
+2.7
+5
+5.5
VDD
V
V
VDD = +5V
VDD = +5V
VDD = +5V
VIO = +3.3V
VIO = +3.3V
VIO = +3.3V
VIO = +5V
VIO = +5V
25
2
30
15
15
1.5
250
250
3
µA
µA
mA
µA
µA
mA
µA
µA
mA
VDD = +5V
VDD = +5V
VDD = +5V
100
100
175
µW
µW
mW
TEMPERATURE RANGE
Operating Range
Storage Range
–40
–55
DIT4192
SBOS229B
MAX
V
V
V
V
µA
40
500
POWER-SUPPLY
Operating Voltage
VDD
VIO
Supply Current
IDD, Quiescent
IDD, Power-Down Mode
IDD, Dynamic (at 192kHz operation)
IIO, Quiescent
IIO, Power-Down Mode
IIO, Dynamic (at 192kHz operation)
IIO, Power-Down Mode
IIO, Quiescent
IIO, Dynamic (at 192kHz operation)
VDD – 0.7
0
TYP
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+85
+125
°C
°C
3
PIN CONFIGURATION: Software Mode (MODE = 0)
Top View
TSSOP
NC
1
28 MODE
CDOUT
2
27 U
CCLK
3
26 NC
CDIN
4
CS
Top View
TSSOP
CSS
1
28 MODE
COPY/C
2
27 U
L
3
26 V
25 BLS
CLK1
4
25 BLS
5
24 NC
CLK0
5
24 BLSM
MCLK
6
23 NC
MCLK
6
23 EMPH
VIO
7
22 INT
VIO
7
DGND
8
21 NC
DGND
8
21 MONO
RXP
9
20 NC
FMT0
9
20 MDAT
NC
10
19 VDD
FMT1
10
19 VDD
SCLK
11
18 TX+
SCLK
11
18 TX+
SYNC
12
17 TX–
SYNC
12
17 TX–
SDATA
13
16 DGND
SDATA
13
16 DGND
NC
14
15 RST
M/S
14
15 RST
DIT4192
PIN DESCRIPTIONS: Software Mode
4
PIN CONFIGURATION: Hardware Mode (MODE = 1)
PIN
NAME
1
2
3
4
5
6
7
NC
CDOUT
CCLK
CDIN
CS
MCLK
VIO
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DGND
RXP
NC
SCLK
SYNC
SDATA
NC
RST
DGND
TX–
TX+
VDD
NC
NC
INT
23
24
25
26
27
28
NC
NC
BLS
NC
U
MODE
DIT4192
22 AUDIO
PIN DESCRIPTIONS: Hardware Mode
PIN DESCRIPTION
No Connection
Control Port Data Output, Tri-State
Control Port Data Clock Input
Control Port Serial Data Input
Control Port Chip Select Input, Active LOW
Master Clock Input
Digital I/O Power Supply, +2.7V to VDD
Nominal
Digital Ground
AES-3 Encoded Data Input
No Connection
Audio Serial Port Data Clock I/O
Audio Serial Port Frame SYNC Clock I/O
Audio Serial Port Data Input
No Connection
Reset Input, Active LOW
Digital Ground
Transmitter Line Driver Output
Transmitter Line Driver Output
Digital Core Power Supply, +5V Nominal
No Connection
No Connection
Open Drain Interrupt Output, Active LOW.
Requires 10kΩ pull-up resistor to VIO.
No Connection
No Connection
Block Start I/O
No Connection
User Data Input
Control Mode Input. Set MODE = 0 for
Software Mode operation.
PIN
NAME
1
2
CSS
COPY/C
3
4
5
6
7
L
CLK1
CLK0
MCLK
VIO
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DGND
FMT0
FMT1
SCLK
SYNC
SDATA
M/S
RST
DGND
TX–
TX+
VDD
MDAT
MONO
AUDIO
EMPH
BLSM
BLS
V
U
MODE
PIN DESCRIPTION
Channel Status Data Mode Input
Copy Protect Input or Channel Status Serial Data Input
Generation Status Input
Master Clock Rate Selection Input
Master Clock Rate Selection Input
Master Clock Input
Digital I/O Power Supply, +2.7V to VDD
Nominal
Digital Ground
Audio Data Format Control Input
Audio Data Format Control Input
Audio Serial Port Data Clock I/O
Audio Serial Port Frame SYNC Clock I/O
Audio Serial Port Data Input
Audio Serial Port Master/Slave Control Input
Reset Input, Active LOW
Digital Ground
Transmitter Line Driver Output
Transmitter Line Driver Output
Digital Core Power-Supply, +5V Nominal
Mono Mode Channel Data Selection Input
Mono Mode Enable Input, Active HIGH
Audio Data Valid Control Input, Active LOW
Pre-Emphasis Status Input, Active LOW
Block Start Mode Control Input
Block Start I/O
Validity Data Input
User Data Input
Control Mode Input. Set MODE = 1 for
Hardware Mode Operation.
DIT4192
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SBOS229B
GENERAL DESCRIPTION
The DIT4192 is a complete digital audio transmitter, suitable
for both professional and consumer audio applications. Sampling rates up to 192kHz are supported. The DIT4192 complies with the requirements for the AES-3, IEC-60958, and
EIAJ CP1201 interface standards.
Figures 1 and 2 show the block diagrams for the DIT4192
when used in Software and Hardware control modes. The
MODE input (pin 28) determines the control model used to
configure the DIT4192 internal functions. In Software mode,
a serial control port is used to write and read on-chip control
registers and status buffers. In Hardware mode, dedicated
control pins are provided for configuration and status inputs.
The DIT4192 includes an audio serial port, which is used to
interface to standard digital audio sources, such as
Analog-to-Digital (A/D) converters, Digital Signal Processors
(DSPs), and audio decoders. Support for Left-Justified, RightJustified, and I2S data formats is provided.
The AES-3 encoder creates a multiplexed bit stream, containing audio, status, and user data. See Figure 3 for the
multiplexed data format. The data is then Bi-Phase Mark
encoded and output to a differential line driver. The line driver
outputs are connected to the transmission medium, be it
cable or fiber optics. In the case of twisted-pair or coaxial
cable, a transformer is commonly used to couple the driver
outputs to the transmission line. This provides both isolation
and improved common-mode rejection. For optical transmission, the TX+ (pin 18) driver output is connected to an optical
transmitter module. See the Applications Information section
of this data sheet for details regarding output driver circuit
configurations.
RXP
U
SYNC
Audio
Serial
Port
SCLK
SDATA
Reset
Logic
RST
AES-3 Encoder
Serial Control Interface,
Control Registers,
and Channel Status
Data Buffers
Line
Driver
TX+
TX–
Clock
Generator
MCLK
Control Port
BLS
INT
FIGURE 1. Software Mode Block Diagram.
SYNC
SCLK
SDATA
M/S
FMT0
FMT1
Audio
Serial
Port
AES-3 Encoder
Line
Driver
TX+
TX–
MCLK
RST
Reset
Logic
CUV
Data Buffer
Clock
Generator
CLK0
CLK1
BLSM
BLS
MONO
MDAT
CSS
COPY/C
L
AUDIO
EMPH
U
V
FIGURE 2. Hardware Mode Block Diagram.
DIT4192
SBOS229B
www.ti.com
5
Start of Channel Status Block
Frame 191
X
Channel A
Frame 0
Channel B
Z
Channel A
Y
Frame 1
Channel B
X
Channel A
Y
Channel B
One Sub-Frame
Bits: 0
3 4
Preamble
7 8
Aux Data
27 28 29 30 31
LSB
Audio Data
MSB V U C P
Validity Data
User Data
Channel Status Data
Parity Bit
FIGURE 3. AES-3 Frame Format.
MASTER CLOCK
The DIT4192 requires a master clock for operation. This
clock must be supplied at the MCLK input (pin 6). The
maximum master clock frequency that may be supplied to
MCLK is 25MHz. Table I shows master clock rates for
common input sampling frequencies.
SAMPLING
MASTER CLOCK FREQUENCY (MHz)
FREQUENCY (kHz)
128 • fS
256 • fS
384 • fS
512 • fS
22.05
24
32
44.1
48
88.2
96
176.4
192
n/a
n/a
n/a
n/a
n/a
n/a
n/a
22.5792
24.576
5.6448
6.144
8.192
11.2896
12.288
22.5792
24.576
n/a
n/a
8.4672
9.216
12.288
16.9344
18.432
n/a
n/a
n/a
n/a
11.2896
12.288
16.384
22.5792
24.576
n/a
n/a
n/a
n/a
TABLE I. Master Clock Frequencies for Common Sampling
Rates.
For Software mode, the master clock frequency selection is
programmed using the CLK0 and CLK1 bits in Control
Register 02H. For Hardware mode, the CLK0 (pin 5) and
CLK1 (pin 4) inputs are used to select the master clock
frequency. Table II shows the available MCLK frequency
selections.
CONTROL BITS OR INPUT PINS
CLK1
0
0
1
1
CLK0
0
1
0
1
MASTER CLOCK (MCLK) SELECTION
128 • fS
256 • fS
384 • fS
512 • fS
TABLE II. Master Clock Rate Selection for Software and
Hardware Modes.
6
RESET AND POWER-DOWN
OPERATION
The DIT4192 includes a reset input, RST (pin 15), which is
used to force a reset sequence. When the DIT4192 is first
powered up, the user must assert RST low in order to start
the reset sequence. The RST input must be low for a
minimum of 500ns. The RST input is then forced high to
enable normal operation. For software mode, the reset sequence will force all internal registers to their default settings.
In addition, the reset sequence will force all channel status
bits to 0 in Software mode.
While the RST input is low, the transmitter outputs,
TX– (pin 17) and TX+ (pin 18), are forced to ground.
Upon setting RST high, the TX– and TX+ outputs will remain
low until the rising edge of the SYNC clock is detected at
pin 12. Once this occurs, the TX– and TX+ outputs will
become active and be driven by the output of the AES-3
encoder.
In Software mode, the DIT4192 also includes software reset
and power-down bits, located in control register 02H. The
software reset bit, RST, and the software power-down bit,
PDN, are both active high.
AUDIO SERIAL PORT
The audio serial port is a 3-wire interface used to connect the
DIT4192 to an audio source, such as an A/D converter or
DSP. The port supports sampling frequencies up to 192kHz.
The port signals include SDATA (pin 13), SYNC (pin 12), and
SCLK (pin 11). The SDATA pin is the serial data input for the
port. The SCLK pin may be either an input or output, and is
used to clock serial data into the port. The SYNC pin may be
either an input or output, and provides the frame synchroni-
DIT4192
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SBOS229B
SYNC AND SCLK FREQUENCIES
zation clock for the port. The SYNC pin is also used as a data
latch clock for the channel status, user, and validity data
inputs in Hardware mode, and the user data input in Software
mode.
The SYNC clock rate is the same as the sampling frequency,
or fS. This holds true for both Slave and Master modes. The
DIT4192 supports SYNC frequencies up to 192kHz.
The SCLK frequency in Slave mode must provide at least
one clock cycle for each data bit that is input at SDATA. The
maximum SCLK frequency is 128 • fS, or 24.576MHz for
fS = 192kHz. The SCLK frequency in Master mode is set by
the DIT4192 itself. For Software mode operation, the SCLK
rate may be programmed to either 64 • fS or 128 • fS, using
the SCLKR bit in Control Register 03HEX. In Hardware mode,
the SCLK frequency is fixed at 64 • fS for Master mode.
SLAVE OR MASTER MODE OPERATION
The audio serial port supports both Slave and Master mode
operation. In Slave mode, both SYNC and SCLK are configured as inputs. The audio source device must generate both
the SYNC and SCLK clocks in Slave mode. In Master mode,
both SYNC and SCLK are configured as outputs. The audio
serial port generates the SYNC and SCLK clocks in Master
mode, deriving both from the master clock (MCLK) input.
AUDIO DATA FORMATS
In Software mode, Master/Slave mode selection is performed using the M/S bit in Control Register 03H (defaults to
Slave mode). In Hardware mode, the M/S input (pin 14) is
used to select the audio serial port mode. This is shown in
Table III.
The DIT4192 supports standard audio data formats, including Philips I2S, Left-Justified, and Right-Justified data.
Software mode provides the most flexible format selection,
while Hardware mode supports a limited subset of the
Software mode formats. Linear PCM audio data at the
SDATA input is typically presented in Binary Two’s Complement, MSB first format. Encoded or non-audio data may be
provided as required by the encoding scheme in use. Figure
4 shows the common data formats used by the audio serial
port.
CONTROL BITS OR INPUT PIN
M/S
MASTER/SLAVE MODE SELECTION
0
Slave Mode, both SYNC and SCLK
are inputs.
1
Master Mode, both SYNC and SCLK
are outputs.
TABLE III. Master/Slave Mode Selection for Software or
Hardware Mode.
Left Channel
Right Channel
SYNC
(ISYNC = 0)
SYNC
(ISYNC = 1)
MSB
SDATA
SDATA
SDATA
MSB
LSB
MSB
LSB
MSB
MSB
LSB
Right Justified
Left Justified
0 SCLK Delay
LSB
MSB
LSB
LSB
Left Justified
1 SCLK Delay (I2S)
SCLK
(ISCLK = 0)
SCLK
(ISCLK = 1)
tSYNCHL
tSYNCHL
SYNC
tSYSK
SCLK
tSYSKHL
tSCLKHL
tSCLKP
SDATA
tADS
tADH
FIGURE 4. Audio Data Formats and Timing.
DIT4192
SBOS229B
www.ti.com
7
For Software mode, Control Register 03H is used to set the
audio data format selection. Data word length may be set to
16, 18, 20, or 24 bits using the WLEN0 and WLEN1 bits.
Several format parameters, including SCLK sampling edge,
data delay from the start of frame, and SYNC polarity may be
programmed using this register. Table IV shows examples of
register bit settings for three standard audio formats. SCLK
sampling edges and SYNC polarity may differ from one
system implementation to the next. Consult the audio source
device data sheet or technical reference for details regarding
the output data formatting.
For Hardware mode, the FMT0 (pin 9) and FMT1 (pin 10)
inputs are utilized to select one of four audio data formats.
Refer to Table V for the available format selections.
Hardware mode operation is similar to Software mode operation, with the exception that there are only a limited number
of data formats available for the audio serial port. For Leftand Right-Justified formats, BLS behaves as it would in
Software mode with ISYNC = 0. For the I2S data format, BLS
behaves as it would in Software mode with ISYNC = 1.
CHANNEL STATUS DATA INPUT
INPUT PINS
FMT1
0
0
1
1
falling edge of SYNC when the ISYNC bit is set to 1. If BLS
is high when it is sampled, then a block start condition is
indicated. When BLS is configured as an output and the
ISYNC bit is set to 0, BLS will go high at every 192nd falling
edge of SYNC for Stereo mode, or every 384th falling edge
of SYNC for Mono mode. BLS will then go low on the
following falling edge. If the ISYNC bit is set to 1, then BLS
transitions on the rising edge of SYNC.
FMT0
0
1
0
1
FORMAT SELECTIONS
24-Bit Left-Justified
24-Bit I2S
24-Bit Right-Justified
16-Bit Right-Justified
TABLE V. Audio Data Format Selection for Hardware Mode.
AES-3 ENCODER OPERATION
The AES-3 encoder performs the multiplexing of audio,
channel status, user, and validity data. It also performs BiPhase Mark encoding of the multiplexed data stream. This
section describes how channel status, user, and validity data
are input to the encoder function.
BLOCK START INPUT/OUTPUT
The block start is used to indicate the start of a channel status
data block, which starts with Frame 0 for the AES-3 data
stream. For the DIT4192, the block start signal BLS
(pin 25), may be either an input or output. In Software mode,
the direction of BLS is set using the BLSM bit in control register
01H (defaults to input). In Hardware mode, the direction of BLS
is set by the BLSM input (pin 24). If BLSM = 0, the BLS pin is
an input. If BLSM = 1, the BLS pin is an output.
For Software mode operation, the block start signal is synchronized to the audio serial port frame sync clock, SYNC
(pin 12). When BLS is configured as an input pin, it is
sampled on the rising edge of SYNC when the ISYNC bit in
control register 03H is set to 0. Otherwise, it is sampled on the
Channel status data input is determined by the control mode
in use. In Software mode, the channel status data buffer is
accessed through the serial control port. Buffer operations
are described in detail in the section of this data sheet
entitled Channel Status Buffer Operation (Software Mode
Only). In Hardware mode, channel status data input is
accomplished by one of two user-selectable methods.
THE CSS INPUT
In Hardware mode, the state of the CSS input (pin 1)
determines the function of dedicated channel status inputs.
When CSS = 0, the COPY (pin 2), L (pin 3), AUDIO (pin 22),
and EMPH (pin 23) inputs are used to set associated
channel status data bits. The COPY and L inputs are used to
set up copy protection for consumer operation, or indicate
that the transmitter is operating in professional mode, without
copy protection. The AUDIO input is utilized to indicate
whether the data being transmitted is PCM audio data, or
non-audio data. The EMPH input is used to indicate whether
the PCM audio data has been pre-emphasized using the
50/15µs standard. See Table VI for the available options for
these dedicated channel status inputs.
When CSS = 1, the channel status data is input in a serial
fashion at the C input (pin 2). Data is clocked on the rising
and falling edges of the SYNC input (pin 12). All channel
status data bits can be written in this mode, allowing greater
flexibility than the previous Hardware mode case with
CSS = 0. See Figure 5 for the C input timing diagram.
CONTROL REGISTER 03H BIT SETTINGS
AUDIO DATA
Bit Name
Function
Bit Name
FORMATS
JUS
Justification
0
0
1
Left-Justified
Left-Justified
Right-Justified
Philips I2S
Left-Justified
Right-Justified
Function
Bit Name
Function
Bit Name
Function
DELAY
SCLK Delay
ISCLK
Sampling Edge
ISYNC
Phase
1
0
0
1 SCLK Delay
0 SCLK Delay
0 SCLK Delay
0
0
0
Rising Edge
Rising Edge
Rising Edge
1
0
0
Inverted
Noninverted
Noninverted
TABLE IV. Audio Data Format Selection in Software Mode.
8
DIT4192
www.ti.com
SBOS229B
INPUT
FUNCTION
COPY
Copy Status
L
Generation Status
COPY
0
0
1
1
AUDIO
Status
Consumer Mode, PRO =
Consumer Mode, PRO =
Consumer Mode, PRO =
Professional Mode, PRO
0, COPY = 0, L = 0
0, COPY = 0, L = 1
0, COPY = 1, L = 0
= 1, No Copy Protection
Audio Data Status
AUDIO
EMPH
L
0
1
0
1
Status
0
Digital (or Linear PCM) Audio Data
1
Non-Audio or Encoded Audio Data
Pre-Emphasis Status
EMPH
Status
0
Pre-emphasis bits are set to indicate 50/15µs Pre-emphasis has been applied.
1
Pre-emphasis bits are set to indicate that no Pre-emphasis has been applied.
TABLE VI. Channel Status Data Input for Hardware Mode with CSS = 0.
Block Start
Frame 191 or 383
Frame 0
SYNC(1)
BLS
(Input)
BLS
(Output)
192nd or 384th
Falling Edge(1)
C, U, or V
Data
Ch B
Data
Ch A
Data
tCUVS
Ch B
Data
Ch A
Data
tCUVH
NOTE: (1) Assumes ISYNC = 0.
FIGURE 5. C, U, and V Data Timing.
USER AND VALIDITY DATA INPUT
The user data bits in the AES-3 data stream allow for a
convenient way to transfer user-defined or application specific data to another device containing an AES-3 receiver.
The U input (pin 27) is used in both Software and Hardware
mode to input the user data in a serial fashion. Figure 5
shows the U input timing diagram.
Validity data is used to indicate that a sample is error-free
audio data, or that the sample is defective and is not suitable
for further processing. In Software mode, the VAL bit in
control register 01H is utilized to write the validity data. In
Hardware mode, the V input (pin 26) is used to input the
validity data in serial fashion. Refer to Figure 5 for V input
timing for Hardware Mode.
When VAL or V = 0, this indicates that the audio data is valid
and suitable for further processing. When VAL or V = 1, then
the audio sample is defective and should not be used.
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9
CCLK is the data clock for the serial control interface. Data
is clocked in at CDIN on the rising edge of CCLK, while data
is clocked out at CDOUT on the falling edge of CCLK. Data
is clocked MSB first for both CDIN and CDOUT.
LINE DRIVER OUTPUTS
The DIT4192 includes a balanced line driver. The line driver
outputs are TX– (pin 17) and TX+ (pin 18). In Software mode,
the line driver input is taken from either the output of the onchip AES-3 encoder, or from an external AES-3 encoded
source input at RXP (pin 9). The input source is selected
using the BYPASS bit in control register 01H (defaults to the
on-chip AES-3 encoder). In Hardware mode, the line driver
source is always the on-chip AES-3 encoder.
WRITE OPERATION
Figure 6 illustrates the write operation for the control port.
You may write one register or buffer address at a time, or use
the auto-increment capability built into the control port to
perform block writes. The register or buffer data is preceded
by a 16-bit header, with the first byte being used to configure
control port operation and set the starting register or buffer
address. The second byte of the header is comprised of
“don’t care” bits, which can be set to either 0 or 1 without
affecting port operation.
The outputs of the line driver will follow the AES-3 encoded
data source in normal operation. During a hardware or
software reset, or when the device is in power-down mode,
the line driver outputs will be forced to ground. The outputs
can also be forced to ground at any time in Software mode
by setting the TXOFF bit to 1 in control register 01H.
The first byte of the header contains two control bits, R/W
and STEP, followed by a 6-bit address. For write operations,
R/W = 0. The STEP bit determines the address step size for
the auto-increment operation. When STEP = 0, the address
is incremented by 1. When STEP = 1, the address is
incremented by 2. Incrementing by 1 is useful when writing
multiple control registers in sequence, or when writing both
left and right channel status data in sequence. Incrementing
by 2 is useful when writing just one channel of status data in
sequence.
CONTROL PORT OPERATION
(SOFTWARE MODE ONLY)
For Software mode operation, the DIT4192 includes a serial
control port, which is used to write and read control registers
and the channel status data buffer. Port signals include CS
(pin 5), CDIN (pin 4), CDOUT (pin 2), and CCLK (pin 3).
CS is the active low chip select. This signal must be driven
low in order to write or read control registers and the channel
status data buffer.
The third byte contains the 8-bit data for the register or buffer
address pointed to by the first byte of the header. To write a
single address location, CS is brought high after the least
significant bit of the third byte is clocked into the port. For
auto increment mode, CS is kept low to write successive
register or buffer addresses.
CDIN is the serial data input, while CDOUT serves as the
serial data output. The CDOUT pin is a tri-state output, which
is set to a high-impedance state when not performing a Read
operation, or when CS = 1.
Set CS = 1 here to write one register or buffer location.
Keep CS = 0 to enable auto-increment mode.
CS
Header
Byte 0
CDIN
Register or Buffer Data
Byte 1
Byte 2
Byte 3
Byte N
CCLK
BYTE DEFINITION
MSB
BYTE 0:
R/W STEP A5
LSB
A4
A3
A2
A1
A0
Register or Buffer Address
Auto-Increment Address Step Size: 0 = Increment Address by 1
1 = Increment Address by 2
Read/Write Control: Set to 1 for Read Operation
Byte 1: All 8 bits are Don’t Care. Set 0 or 1.
Bytes 2 through N: 8-Bit Register or Buffer data.
FIGURE 6. Write Operation Format.
10
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SBOS229B
READ OPERATION
the auto-increment operation. When STEP = 0, the address
is incremented by 1. When STEP = 1, the address is
incremented by 2. Incrementing by 1 is useful when reading
multiple control registers in sequence, or when reading both
left and right channel status data in sequence. Incrementing
by 2 is useful for reading just one channel of status data in
sequence.
Figure 7 shows an illustration of the read operation for the
control port. You may read one register or buffer address at
a time, or use the auto-increment capability built into the
control port to perform block reads. A 16-bit header is first
written to the port, with the first byte being used to configure
control port operation and set the starting register or buffer
address. The second byte of the header is comprised of
“don’t care” bits, which can be set to either 0 or 1 without
affecting port operation.
The first output data byte occurs immediately after the 16-bit
header has been written. This byte contains the 8-bit data for
the register or buffer address pointed to by the first byte of
the header. To read a single address location, CS is brought
high after the least significant bit of the first data byte is
clocked out of the port. For auto-increment mode, CS is kept
low to read successive register or buffer addresses.
The first byte of the header contains two control bits, R/W
and STEP, followed by a 6-bit address. For read operations,
R/W = 1. The STEP bit determines the address step size for
Set CS = 1 here to read one register or buffer location.
Keep CS = 0 to enable auto-increment mode.
CS
Header
Byte 0
CDIN
Byte 1
Ignore Until Next High-to-Low Transition of CS
Register or Buffer Data
Byte 0
High Impedance
CDOUT
Byte 1
Byte N
CCLK
BYTE DEFINITION
MSB
BYTE 0:
LSB
R/W STEP A5
A4
A3
A2
A1
A0
Register or Buffer Address
Auto-Increment Address Step Size: 0 = Increment Address by 1
1 = Increment Address by 2
Read/Write Control: Set to 1 for Read Operation
Byte 1: All 8 bits are Don’t Care. Set 0 or 1.
Bytes 2 through N: 8-Bit Register or Buffer data.
FIGURE 7. Read Operation Format.
CS
tCSCR
tCFCS
tSDS
CCLK
tSDH
CDIN
CDOUT
tCFDO
tCSZ
FIGURE 8. Serial Port Timing.
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11
CONTROL REGISTER DEFINITIONS
(SOFTWARE MODE ONLY)
When MONO = 1 and MCSD = 0, the MDAT bit
is used to select the source for Audio data.
When MONO = 1 and MCSD = 1, the MDAT bit
is used to select the source for both Audio and
Channel Status data.
This section defines the control registers used to configure
the DIT4192, as well as the status register used to indicate
an interrupt source.
MCSD
Channel Status Data Selection (Defaults to 0)
Register 00H: Reserved for Factory Use
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
0
0
0
0
0
0
0
0
BLSM
When set to 0, Channel A data is used for the A
sub-frame, while Channel B data is used for the
B sub-frame.
When set to 1, use the same channel status data
for both A and B sub-frames. Channel status data
source is selected using the MDAT bit.
Block Start Mode (Defaults to 0)
When set to 0, BLS (pin 25) is configured as an
input pin.
TXOFF
Transmitter Output Disable (Defaults to 0)
When set to 0, the line driver outputs, TX–
(pin 17) and TX+ (pin 18) are enabled.
When set to 1, BLS (pin 25) is configured as an
output pin.
VAL
When set to 1, the line driver outputs are forced
to ground.
Audio Data Valid (Defaults to 0)
When set to 0, valid Linear PCM audio data is
indicated.
When set to 1, invalid audio data or non-PCM
data is indicated.
Register 02H: Power-Down and Clock Control Register
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
0
0
0
0
RST
CLK1
CLK0
PDN
Register 01H: Transmitter Control Register
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
TXOFF
MCSD
MDAT
MONO
BYPAS
MUTE
VAL
BLSM
PDN
Power-Down (Defaults to 1)
When set to 0, the DIT4192 operates normally.
When set to 1, the DIT4192 is powered down,
with the line driver outputs forced to ground.
MUTE
Transmitter Mute (Defaults to 0)
When set to 0, the mute function is disabled.
CLK[1:0]
MCLK Rate Selection
These bits are used to select the master clock
frequency applied to the MCLK input (pin 6).
When set to 1, the mute function is enabled,
with Channel A and B audio data set to all 0’s.
BYPASS
CLK1
0
0
1
1
Transmitter Bypass—AES-3 Data Source for
the Output Driver (Defaults to 0)
When set to 0, AES-3 encoded data is taken
from the output of the on-chip encoder.
When set to 1, RXP (pin 9) is used as the
source for AES-3 encoded data.
MONO
When set to 1, the transmitter is set to Mono
mode.
When set to 0, the DIT4192 operates normally.
When set to 1, the DIT4192 is reset.
Register 03H: Audio Serial Port Control Register
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
ISYNC
ISCLK
DELAY
JUS
WLEN1
WLEN0
SCLKR
M/S
Data Selection Bit (Defaults to 0)
(0 = Left Channel, 1 = Right Channel)
When MONO = 0 and MCSD = 0, the MDAT bit
is ignored.
M/S
When MONO = 0 and MCSD = 1, the MDAT bit
is used to select the source for Channel Status
data.
12
MCLK Rate
128 • fS
256 • fS (default)
384 • fS
512 • fS
Software Reset (Defaults to 0)
Mono Mode Control (Defaults to 0)
When set to 0, the transmitter is set to Stereo
mode.
MDAT
RST
CLK0
0
1
0
1
Master/Slave Mode (Defaults to 0)
When set to 0, the audio serial port is set for
Slave operation.
When set to 1, the audio serial port is set for
Master operation.
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SBOS229B
SCLKR
Master Mode SCLK Frequency (Defaults to 0)
BTI
Buffer Transfer Interrupt Status—Active
High
When set to 0, the SCLK frequency is set to
64 • fS.
When User Access (UA) to Transmitter Access
(TA) buffer transfers are enabled, and the BTI
interrupt is unmasked, this bit will go HIGH
when a UA to TA buffer transfer has completed. This will also cause the INT output
(pin 22) to be driven Low, indicating that an
interrupt has occurred.
When set to 1, the SCLK frequency is set to
128 • fS.
WLEN[1:0]
Audio Data Word Length
These bits are used to set the audio data word
length for both Left and Right channels.
TSLIP
JUS
WLEN1
0
WLEN0
0
Length
24 Bits (default)
0
1
20 Bits
1
0
18 Bits
1
1
16 Bits
Transmitter Source Data Slip Interrupt Status—Active High
This bit will go HIGH when either a Data Slip or
Block Start condition is detected, and the TSLIP
interrupt is unmasked. This will also cause the
INT output (pin 22) to be driven LOW, indicating that an interrupt has occurred. The function
of this bit is selected using the BSSL bit in
control register 05H (defaults Data Slip).
Audio Data Justification (Defaults to 0)
When set to 0, the audio data is Left-Justified
The MBTI and MTSLIP bits are used to mask
the BTI and TSLIP interrupts. When masked,
these interrupt sources are disabled.
with respect to the SYNC edges.
When set to 1, the audio data is Right-Justified
with respect to the SYNC edges.
Register 05H: Interrupt Mask Register
DELAY
Audio Data Delay from the Start of Frame
(Defaults to 0)
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
0
0
0
0
0
BSSL
MTSLIP
MBTI
This applies primarily to I2S and DSP frame
formats, which use Left-Justified audio data.
When set to 0, audio data starts with the SCLK
period immediately following the SYNC edge
which starts the frame. This is referred to as a
zero SCLK delay.
When set to 1, the audio data starts with the
second SCLK period following the SYNC edge
which starts the frame. This is referred to as a
one SCLK delay. This is used primarily for the
I2S data format.
ISCLK
MBTI
BTI Interrupt Mask. Set to ‘0’ to mask BTI
(Defaults to 0).
MTSLIP
TSLIP Interrupt Mask. Set to ‘0’ to mask
TSLIP (Defaults to 0).
BSSL
TSLIP Interrupt Select (Defaults to 0)
When set to 0, the Data Slip condition is used
to trigger a TSLIP interrupt.
When set to 1, the Block Start condition is
used to trigger a TSLIP interrupt.
SCLK Sampling Edge (Defaults to 0)
When set to 0, audio serial data at SDATA
(pin 13) is sampled on rising edge of SCLK.
When set to 1, audio serial data at SDATA
(pin 13) is sampled on falling edge of SCLK.
ISYNC
Register 06H: Interrupt Mode Register
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
0
0
0
0
Bit 3
Bit 2
TSLIPM1 TSLIPM0
Bit 1
Bit 0 (LSB)
BTIM1
BTIM0
SYNC Polarity (Defaults to 0)
When set to 0, Left channel data occurs when
the SYNC clock is HIGH.
BTIM[1:0]
BTI Interrupt Mode
TSLIPM[1:0] TSLIP Interrupt Mode
When set to 1, Left channel data occurs when
the SYNC clock is LOW.
For both cases, Left channel data always precedes the Right channel data in the audio frame.
Register 04H: Interrupt Status Register
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
0
0
0
0
0
0
TSLIP
BTI
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These bits are used to select the active state
for interrupt operation.
BTIM1 or BTIM0 or
TSLIPM1
TSLIPM0
Interrupt Operation
0
0
Rising Edge Active (default)
0
1
Falling Edge Active
1
0
Level Active
1
1
Reserved
13
BTD
Buffer Transfer Disable (Defaults to 0)
When set to 0, User Access (UA) to Transmitter Access (TA) Buffer transfers are enabled.
When set to 1, User Access (UA) to Transmitter Access (TA) Buffer transfers are disabled.
Register 07H: Channel Status Buffer Control Register
bit 7 (MSB)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 (LSB)
0
0
0
0
0
0
0
BTD
CHANNEL STATUS DATA
BUFFER OPERATION
(SOFTWARE MODE ONLY)
The master clock input (MCLK) and the frame synchronization clock input (SYNC) must be active in order to update the
channel status buffer in Software mode. When the DIT4192
is initially powered up, the device defaults to power-down
mode. When the PDN bit in Register 2 is set to 0 to power
up the device, there must be a delay between the time that
PDN is set to 0 and the first access to the channel status
buffer. This delay allows the SYNC clock to synchronize the
AES3 encoder block with the audio serial port. It is recommended that Register 2 be the last control register written in
the initialization sequence, followed by a delay (10 milliseconds or longer) before attempting to access the channel
status buffer.
UPDATING THE CHANNEL DATA STATUS BUFFER
The DIT4192 contains two buffers for the channel status data.
These are referred to as the Transmitter Access (TA) buffer
and the User Access (UA) buffer. Each buffer is 48 bytes long,
containing 24 bytes each for channels A and B. The 24 bytes
per channel correspond to the channel status block defined in
the AES-3 and IEC-60958 specifications. Channel A and B
data are interleaved within the buffers, see Tables VII and VIII.
The AES-3 encoder internally accesses the TA buffer to
obtain the channel status data that is multiplexed into the
AES-3 data stream. The user accesses the UA buffer through
the control port in order to update the channel status data
when needed. The transfer of data from the UA buffer to the
TA buffer is managed internally by the DIT4192, but it may
be enabled or disabled by the user via a control register.
Updating the channel status data buffer involves disabling
and enabling the UA to TA buffer transfer using the BTD bit
in control register 07H. Figure 9 shows the proper flow for
updating the buffer.
The BTD bit is normally set to 0, which enables the UA to TA
buffer transfer. In order to update the channel status data, the
user must write to the UA buffer. To avoid UA to TA data
transfer while the UA buffer is being updated, the BTD bit is set
to 1, which disables UA to TA buffer transfers. While
BTD = 1, the user writes new channel status data to the UA
buffer via the control port. Once the UA buffer update is
complete, the BTD bit is reset to 0. A new UA to TA buffer
transfer will occur during one of the frames 184 through 191,
DISABLE UA TO TA BUFFER TRANSFER
Set BTD = 1
in Control Register 07H
UPDATE THE CS DATA
Write Channel Status Data
to the UA Buffer
ENABLE UA TO TA BUFFER TRANSFER
Set BTD = 0
in Control Register 07H
NO
NO
Is the
Buffer Transfer Interrupt (BTI)
Masked?
YES
Assume that the Buffer Transfer has
completed and that the Channel Status
data has been updated.
Is the
INT output LOW?
YES
Read Register 04H to verify that the
BTI bit is set to 1.
The Host has verified that the Buffer
Transfer is complete, which completes the
Channel Status Data update.
FIGURE 9. Flowchart for Updating the Channel Status Buffer.
14
DIT4192
www.ti.com
SBOS229B
ADDRESS
CS
BIT 0
(HEX)
Byte
MSB
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
08
A0
09
0A
BIT 7
PRO
AUDIO
EMPH
EMPH
EMPH
LOCK
fS
B0
PRO
AUDIO
EMPH
EMPH
EMPH
LOCK
fS
fS
A1
CH MODE
CH MODE
CH MODE
CH MODE
U BIT MGT
U BIT MGT
U BIT MGT
U BIT MGT
LSB
fS
0B
B1
CH MODE
CH MODE
CH MODE
CH MODE
U BIT MGT
U BIT MGT
U BIT MGT
U BIT MGT
0C
A2
AUX
AUX
AUX
WLEN
WLEN
WLEN
reserved
reserved
0D
B2
AUX
AUX
AUX
WLEN
WLEN
WLEN
reserved
reserved
0E
A3
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0F
B3
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
10
A4
REF
REF
reserved
reserved
reserved
reserved
reserved
reserved
11
B4
REF
REF
reserved
reserved
reserved
reserved
reserved
reserved
12
A5
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
13
B5
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
14
A6
Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel A
15
B6
Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel B
16
A7
Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel A
17
B7
Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel B
18
A8
Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel A
19
B8
Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel B
1A
A9
Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel A
1B
B9
Alphanumeric Channel Origin Data (7-Bit ASCII0) for Channel B
1C
A10
Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel A
1D
B10
Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel B
1E
A11
Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel A
1F
B11
Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel B
20
A12
Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel A
21
B12
Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel B
22
A13
Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel A
23
B13
Alphanumeric Channel Destination Data (7-Bit ASCII) for Channel B
24
A14
Local Sample Address Code (32-Bit Binary) for Channel A
25
B14
Local Sample Address Code (32-Bit Binary) for Channel B
26
A15
Local Sample Address Code (32-Bit Binary) for Channel A
27
B15
Local Sample Address Code (32-Bit Binary) for Channel B
28
A16
Local Sample Address Code (32-Bit Binary) for Channel A
29
B16
Local Sample Address Code (32-Bit Binary) for Channel B
2A
A17
Local Sample Address Code (32-Bit Binary) for Channel A
2B
B17
Local Sample Address Code (32-Bit Binary) for Channel B
2C
A18
Time of Day Code (32-Bit Binary) for Channel A
2D
B18
Time of Day Code (32-Bit Binary) for Channel B
2E
A19
Time of Day Code (32-Bit Binary) for Channel A
2F
B19
Time of Day Code (32-Bit Binary) for Channel B
30
A20
Time of Day Code (32-Bit Binary) for Channel A
31
B20
Time of Day Code (32-Bit Binary) for Channel B
32
A21
Time of Day Code (32-Bit Binary) for Channel A
33
B21
Time of Day Code (32-Bit Binary) for Channel B
34
A22
reserved
reserved
reserved
reserved
Rel Flags
Rel Flags
Rel Flags
Rel Flags
35
B22
reserved
reserved
reserved
reserved
Rel Flags
Rel Flags
Rel Flags
Rel Flags
36
A23
CRC Check Character for Channel A
37
B23
CRC Check Character for Channel B
TABLE VII. Channel Status Buffer Map for Professional Mode (PRO = 1).
DIT4192
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15
ADDRESS
CS
BIT 0
(HEX)
Byte
MSB
8
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
A12
B12
A13
B13
A14
B14
A15
B15
A16
B16
A17
B17
A18
B18
A19
B19
A20
B20
A21
B21
A22
B22
A23
B23
PRO = 0
PRO = 0
CAT CODE
CAT CODE
SOURCE
SOURCE
fS
fS
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
AUDIO
AUDIO
CAT CODE
CAT CODE
SOURCE
SOURCE
fS
fS
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
COPY
COPY
CAT CODE
CAT CODE
SOURCE
SOURCE
fS
fS
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EMPH
EMPH
CAT CODE
CAT CODE
SOURCE
SOURCE
fS
fS
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EMPH
EMPH
CAT CODE
CAT CODE
CH NUM
CH NUM
CLK ACC
CLK ACC
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
EMPH
EMPH
CAT CODE
CAT CODE
CH NUM
CH NUM
CLK ACC
CLK ACC
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
MODE
MODE
CAT CODE
CAT CODE
CH NUM
CH NUM
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
MODE
MODE
L
L
CH NUM
CH NUM
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
LSB
TABLE VIII. Channel Status Buffer for Consumer Mode (PRO = 0).
whichever is the first frame to occur after the BTD bit is reset
to 0. Once the UA to TA buffer transfer is completed, the buffer
transfer interrupt (BTI) will occur, as long as it is unmasked.
INTERRUPT SOURCES
(SOFTWARE MODE ONLY)
The transmitter will ignore any attempt to access the UA
buffer during a UA to TA buffer transfer. In addition, the BTD
bit may be set to 1 to stop a UA to TA buffer transfer that
maybe in progress, if so desired.
The DIT4192 can be programmed to generate interrupts for
up to three predefined conditions. The interrupt output, INT
(pin 22), is set low when a valid interrupt occurs. The interrupt
status register, 04H, is then read to determine the source of
the interrupt. Status register bits and the INT output pin
remain active until the status register is read. Once read,
status bits are cleared and the INT pin is pulled high by an
external pull-up resistor to VIO.
CHANNEL STATUS BUFFER MAP
The channel status buffer is organized in accordance with
the AES-3 and IEC-60958 standards. See Table VII for the
memory map for the UA channel status data buffer for
Professional mode. Table VIII shows the memory map for the
UA channel status data buffer for Consumer mode.
16
Interrupts may be masked using control register 05H. When
masked, the interrupt mechanism associated with a particular status bit is disabled.
DIT4192
www.ti.com
SBOS229B
CHANNEL STATUS BUFFER TRANSFER INTERRUPT
This interrupt occurs when a channel status buffer transfer
has been completed. The buffer transfer process was described in detail in the previous section of this data sheet.
This interrupt may be used by the host to trigger an event to
occur after a channel status buffer update. The BTI bit in
status register 04H is used to indicate the occurrence of the
buffer transfer. The BTI bit, like all other status bits, is active
high and remains set until the status register is read.
A block start condition occurs when a block start signal is
generated either internally by the DIT4192, or when an
external block start is received at the BLS input (pin 25).
APPLICATIONS INFORMATION
This section provides practical information pertinent for designing the DIT4192 into a target application. Circuit schematics are provided as needed.
DATA SLIP AND BLOCK START INTERRUPTS
TYPICAL APPLICATION DIAGRAMS
Unlike the BTI interrupt, which has only one function, the
TSLIP interrupt can be set to one of two modes. This is
accomplished using the BSSL bit in control register 05H.
When BSSL = 0, the TSLIP interrupt is set to indicate a data
slip condition. When BSSL = 1, the TSLIP interrupt is set to
indicate a block start condition. The TSLIP bit, like all other
status bits, is active high and remains set until the status
register is read.
Figures 10 and 11 illustrate the typical application schematics for the DIT4192 when used in Software and Hardware
modes. Figure 10 shows a typical Software mode application, where a microprocessor or DSP interface is used to
communicate with the DIT4192 via the serial control port.
See Figure 11 for a typical Hardware mode configuration,
where the control pins are either hardwired or driven by
digital logic in a stand-alone application.
A data slip condition may occur in cases where the master
clock, MCLK (pin 6), is asynchronous to the audio data
source. When BSSL = 0, the TSLIP bit will be set to 1 every
time a data sample is dropped or repeated.
The recommended component values for power-supply bypass capacitors are shown in Figures 10 and 11. These
capacitors should be located as close to the DIT4192 powersupply pins as physically possible.
From AES-3
Encoded Data
Source
(Optional)
9
11
Digital Audio
Source
(A/D Converter,
DSP)
12
13
DIT4192
RXP
SCLK
TX+
18
Output
Circuit
SYNC
SDATA
TX–
Cable or
Fiber Optics
17
(See Figs. 12-14)
5
3
4
2
µP or DSP
22
25
27
15
6
28
Audio Master
Clock
CS
CCLK
CDIN
CDOUT
INT
+2.7V to VDD
BLS
C1
U
VIO
RST
DGND
MCLK
VDD
MODE
DGND
7
8
19
+5V C2
C1 = C2 = 0.1µF to 1µF
16
10kΩ
VIO
FIGURE 10. Typical Circuit Configuration, Software Mode.
DIT4192
SBOS229B
www.ti.com
17
DIT4192
Digital Audio
Source
(A/D Converter,
DSP)
11
12
13
14
9
10
1
2
27
26
3
22
23
24
21
20
Hardwired
Control
or
Dedicated
Logic
or
Host
Controlled
15
25
6
5
4
28
Audio Master
Clock Generator
SCLK
SYNC
SDATA
TX+
18
Cable or
Fiber Optics
Output
Circuit
M/S
FMT0
FMT1
CSS
COPY/C
U
V
L
AUDIO
EMPH
BLSM
MONO
MDAT
TX–
17
(See Figs. 12-14)
+2.7V to VDD
C1
VIO
RST
BLS
DGND
VDD
MCLK
CLK0
CLK1
MODE
DGND
7
8
19
+5V C2
C1 = C2 = 0.1µF to 1µF
16
VIO
FIGURE 11. Typical Circuit Configuration, Hardware Mode.
The line driver outputs may be connected to cable or fiber
optic transmission media in the target application. Figures 12
and 13 show typical connections for driving either balanced
twisted-pair or unbalanced coaxial cable. Either of these
connections will support rates up to 192kHz.
TX+
18
T1(1)
1:1
110
1
XLR
5
Figure 14 illustrates the connection to an optical transmitter
module, used primarily in consumer applications, such as CD
or DVD players. The optical transmitter data rate is limited to
6Mb/s, so it will not support 192kHz data rates. The optical
interface is typically reserved for lower rate transmission,
such as 44.1kHz or 48kHz.
TX+
2
18
4
Toshiba
TOTX173
Optical
Transmitter
1
DIT4192
TX–
17
0.1µF
3
8
4
DIT4192
TX–
17
NC
3
NOTE: (1) Scientific Conversion SC937-02 or equivalent.
18
0.1µF
300
1
T1(1)
2:1
TOSLINK
APF Interconnect
+5V
FIGURE 14. Recommended Transmitter Output Circuit for
TOSLINK Optical Transmission Over All Plastic
Fiber (APF).
RCA or BNC
5
DUAL-WIRE OPERATION USING MONO MODE
DIT4192
TX–
17
4
8
NOTE: (1) Scientific Conversion SC982-04 or equivalent.
FIGURE 13. Recommended Transmitter Output Circuit for
Unbalanced, 75Ω Coaxial Cable Transmission.
18
1
8.2kΩ
FIGURE 12. Recommended Transmitter Output Circuit for
Balanced, 110Ω Twisted-Pair Transmission.
TX+
2
In order to support stereo 192kHz transmission for legacy
systems, which utilize AES-3 receivers that operate up to a
maximum of 96kHz, it is necessary to use two DIT4192
transmitters in what is referred to as a Dual-Wire configuration. Each transmitter carries data for only one channel in this
configuration.
DIT4192
www.ti.com
SBOS229B
Dual-Wire operation requires that each DIT4192 operates in
Mono mode, which is supported in both Software and Hardware control modes. In Mono mode, the DIT4192 transmits
two consecutive samples of a single channel for both the
Channel A and Channel B sub-frames, effectively doubling
the sampling rate. The audio serial port channel used for
sampling audio and channel status data is selectable in both
Software and Hardware control modes.
as the source channel for audio and channel status data.
Refer to the register definition for details regarding the setting
of these bits.
In Hardware mode, the MONO (pin 21) and MDAT (pin 20)
inputs are used to enable mono mode, as well as selecting
the source channel for audio and channel status data.
Table IX shows the available options for MONO and MDAT
selection. Figure 15 illustrates a simple Hardware mode
configuration for implementing Dual-Channel operation using
two DIT4192 transmitters.
In Software mode, the MONO, MDAT, and MCSD bits in
control register 01H are used to select mono mode, as well
INPUT
FUNCTION
MONO
Stereo/Mono Mode Selection
MONO
0
1
MDAT
Status
Stereo Mode
Mono Mode
Mono Mode Audio and Channel Status Data Selection
MDAT
Status
0
Source is Left Channel for Audio data, and Channel A for CS data.
1
Source is Right Channel for Audio data, and Channel B for CS data.
TABLE IX. Mono Mode Configuration Settings for Hardware Mode Operation.
VIO
11
12
13
14
ADC
DATA
LRCK
BCK
13
12
11
Master Clock
Generator
To All Devices 14
SCLK
21
20
MONO
MDAT
TX+
SYNC
DIT4192
SDATA
TX–
18
17
Output
Circuit
Right
Channel
Output
(See Figs. 12-14)
M/S
SDATA
TX+
SYNC
DIT4192
SCLK
M/S
TX–
MONO
MDAT
21
20
18
17
Output
Circuit
Left
Channel
Output
(See Figs. 12-14)
VIO
NOTE: To simplify the drawing, not all pins are shown here.
FIGURE 15. Hardware Mode Example for Dual-Channel Transmitter Operation.
DIT4192
SBOS229B
www.ti.com
19
PACKAGE DRAWING
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
20
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
DIT4192
www.ti.com
SBOS229B
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DIT4192IPW
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
DIT4192I
DIT4192IPWR
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
DIT4192I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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