DLP3010
DLPS099B – FEBRUARY 2018 – REVISED MAY 2022
DLP3010 0.3 720p DMD
1 Features
3 Description
•
The DLP3010 digital micromirror device (DMD) is
a digitally controlled micro-opto-electromechanical
system (MOEMS) spatial light modulator (SLM).
When coupled to an appropriate optical system,
the DLP3010 DMD displays a very crisp and high
quality image or video. DLP3010 is part of the
chipset comprising of the DLP3010 DMD, DLPC3433
or DLPC3438 display controller and DLPA200x/
DLPA3000 PMIC/LED driver. The compact physical
size of the DLP3010 coupled with the controller and
the PMIC/LED driver provides a complete system
solution that enables small form factor, low-power,
and high-resolution HD displays.
•
•
0.3-Inch (7.93-mm) Diagonal Micromirror Array
– 1280 × 720 Array of Aluminum MicrometerSized Mirrors, in an Orthogonal Layout
– 5.4-µm Micromirror Pitch
– ±17° Micromirror Tilt (Relative to Flat Surface)
– Side Illumination for Optimal Efficiency and
Optical Engine Size
– Polarization Independent Aluminum Micromirror
Surface
8-Bit SubLVDS Input Data Bus
Dedicated DLPC3433 or DLPC3438 Display
Controller and DLPA200x/DLPA3000 PMIC/LED
Driver for Reliable Operation
Device Information
2 Applications
•
•
•
•
•
•
Battery Powered Mobile Accessory HD Projector
Battery Powered Smart HD Projector
Digital Signage
Interactive Surface Projection
Low-Latency Gaming Display
Interactive Display
PART NUMBER
PACKAGE(1)
DLP3010
FQK (57)
(1)
BODY SIZE (NOM)
18.20-mm × 7.00-mm
For all available packages, see the orderable addendum at
the end of the data sheet.
DLP® DLP3010 0.3 720p Chipset
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP3010
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DLPS099B – FEBRUARY 2018 – REVISED MAY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 Storage Conditions..................................................... 7
6.3 ESD Ratings............................................................... 7
6.4 Recommended Operating Conditions.........................7
6.5 Thermal Information..................................................10
6.6 Electrical Characteristics...........................................10
6.7 Timing Requirements................................................ 11
6.8 Switching Characteristics..........................................16
6.9 System Mounting Interface Loads............................ 16
6.10 Micromirror Array Physical Characteristics............. 17
6.11 Micromirror Array Optical Characteristics............... 18
6.12 Window Characteristics.......................................... 19
6.13 Chipset Component Usage Specification............... 19
7 Detailed Description......................................................21
7.1 Overview................................................................... 21
7.2 Functional Block Diagram......................................... 21
7.3 Feature Description...................................................22
7.4 Device Functional Modes..........................................22
7.5 Optical Interface and System Image Quality
Considerations............................................................ 22
7.6 Micromirror Array Temperature Calculation.............. 23
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24
8 Application and Implementation.................................. 28
8.1 Application Information............................................. 28
8.2 Typical Application.................................................... 28
9 Power Supply Recommendations................................31
9.1 Power Supply Power-Up Procedure......................... 31
9.2 Power Supply Power-Down Procedure.....................31
9.3 Power Supply Sequencing Requirements................ 32
10 Layout...........................................................................34
10.1 Layout Guidelines................................................... 34
10.2 Layout Example...................................................... 34
11 Device and Documentation Support..........................35
11.1 Device Support........................................................35
11.2 Related Links.......................................................... 35
11.3 Receiving Notification of Documentation Updates.. 35
11.4 Support Resources................................................. 36
11.5 Trademarks............................................................. 36
11.6 Electrostatic Discharge Caution.............................. 36
11.7 Glossary.................................................................. 36
12 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2021) to Revision B (May 2022)
Page
• Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6
• Updated Micromirror Array Optical Characteristics ......................................................................................... 18
• Added Third-Party Products Disclaimer ...........................................................................................................35
Changes from Revision * (February 2018) to Revision A (October 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated |TDELTA| MAX from 30°C to 15°C..........................................................................................................7
2
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5 Pin Configuration and Functions
Figure 5-1. FQK Package. 57-Pin LGA. BOTTOM VIEW.
Table 5-1. Pin Functions – Connector Pins
PIN(1)
NAME
NO.
TYPE
SIGNAL
DATA RATE
PACKAGE NET
LENGTH(2) (mm)
DESCRIPTION
DATA INPUTS
D_N(0)
C9
I
SubLVDS
Double
Data, Negative
10.54
D_P(0)
B9
I
SubLVDS
Double
Data, Positive
10.54
D_N(1)
D10
I
SubLVDS
Double
Data, Negative
13.14
D_P(1)
D11
I
SubLVDS
Double
Data, Positive
13.14
D_N(2)
C11
I
SubLVDS
Double
Data, Negative
14.24
D_P(2)
B11
I
SubLVDS
Double
Data, Positive
14.24
D_N(3)
D12
I
SubLVDS
Double
Data, Negative
14.35
D_P(3)
D13
I
SubLVDS
Double
Data, Positive
14.35
D_N(4)
D4
I
SubLVDS
Double
Data, Negative
5.89
D_P(4)
D5
I
SubLVDS
Double
Data, Positive
5.89
D_N(5)
C5
I
SubLVDS
Double
Data, Negative
5.45
D_P(5)
B5
I
SubLVDS
Double
Data, Positive
5.45
D_N(6)
D6
I
SubLVDS
Double
Data, Negative
8.59
D_P(6)
D7
I
SubLVDS
Double
Data, Positive
8.59
D_N(7)
C7
I
SubLVDS
Double
Data, Negative
7.69
D_P(7)
B7
I
SubLVDS
Double
Data, Positive
7.69
DCLK_N
D8
I
SubLVDS
Double
Clock, Negative
8.10
DCLK_P
D9
I
SubLVDS
Double
Clock, Positive
8.10
LS_WDATA
C12
I
LPSDR(1)
Single
Write data for low-speed interface.
7.16
LS_CLK
C13
I
LPSDR
Single
Clock for low-speed interface.
7.89
CONTROL INPUTS
DMD_DEN_ARSTZ
C14
I
LPSDR
LS_RDATA
C15
O
LPSDR
VBIAS(3)
C1
Power
VBIAS(3)
C18
Power
Asynchronous reset DMD signal. A low
signal places the DMD in reset. A high
signal releases the DMD from reset
and places it in active mode.
Single
Read data for low-speed interface.
POWER
Supply voltage for positive bias level at
micromirrors.
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Table 5-1. Pin Functions – Connector Pins (continued)
PIN(1)
NAME
TYPE
VOFFSET(3)
D1
Power
VOFFSET(3)
D17
Power
VRESET
B1
Power
VRESET
B18
Power
VDD
B6
Power
VDD
B10
Power
VDD
B19
Power
VDD(3)
C6
Power
VDD
C10
Power
VDD
C19
Power
VDD
D2
Power
VDD
D18
Power
VDD
D19
Power
VDDI
B2
Power
VDDI
C2
Power
VDDI
C3
Power
VDDI
D3
Power
VSS
B3
Ground
VSS
B4
Ground
VSS
B8
Ground
VSS
B12
Ground
VSS
B13
Ground
VSS
B14
Ground
VSS
B15
Ground
VSS
B16
Ground
VSS
B17
Ground
VSS
C4
Ground
VSS
C8
Ground
VSS
C16
Ground
VSS
C17
Ground
VSS
D14
Ground
VSS
D15
Ground
VSS
D16
Ground
(1)
(2)
(3)
4
NO.
SIGNAL
DATA RATE
DESCRIPTION
PACKAGE NET
LENGTH(2) (mm)
Supply voltage for HVCMOS core
logic. Supply voltage for stepped
high level at micromirror address
electrodes.
Supply voltage for offset level at
micromirrors.
Supply voltage for negative reset level
at micromirrors.
Supply voltage for LVCMOS core logic.
Supply voltage for LPSDR inputs.
Supply voltage for normal high level at
micromirror address electrodes.
Supply voltage for SubLVDS receivers.
Common return.
Ground for all power.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
Net trace lengths inside the package:
Relative dielectric constant for the FQK ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.
Propagation delay = 0.265 ns/in = 265 ps/in = 10.43 ps/mm.
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
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Table 5-2. Pin Functions – Test Pads
NUMBER
SYSTEM BOARD
A13
Do not connect
A14
Do not connect
A15
Do not connect
A16
Do not connect
A17
Do not connect
A18
Do not connect
E13
Do not connect
E14
Do not connect
E15
Do not connect
E16
Do not connect
E17
Do not connect
E18
Do not connect
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
–0.5
2.3
VDDI
Supply voltage for SubLVDS receivers(2)
–0.5
2.3
VOFFSET
Supply voltage for HVCMOS and micromirror
electrode(2) (3)
–0.5
11
Supply voltage for micromirror electrode(2)
–0.5
19
Supply voltage for micromirror electrode(2)
–15
0.5
|VDDI–VDD|
Supply voltage delta (absolute
value)(4)
0.3
|VBIAS–VOFFSET|
Supply voltage delta (absolute value)(5)
11
|VBIAS–VRESET|
Clock
frequency
VDD + 0.5
Input voltage for other inputs SubLVDS(2) (7)
–0.5
VDDI + 0.5
|VID|
SubLVDS input differential voltage (absolute value)(7)
IID
ƒclock
ƒclock
|TDELTA|
(3)
(4)
(5)
(6)
(7)
(8)
(9)
6
UNIT
V
34
–0.5
Environmental TDP
(2)
Supply voltage delta (absolute
value)(6)
Input voltage for other inputs LPSDR(2)
TARRAY and TWINDOW
(1)
MAX
Supply voltage for LVCMOS core
Supply voltage for LPSDR low-speed interface
VRESET
Input pins
MIN
VDD
Supply voltage VBIAS
Input voltage
logic(2)
V
810
mV
SubLVDS input differential current
10
mA
Clock frequency for low-speed interface LS_CLK
130
Clock frequency for high-speed interface DCLK
560
Temperature – operational(8)
Temperature –
non-operational(8)
–20
90
–40
90
Dew point temperature – operating and non-operating
(non-condensing)
81
Absolute temperature delta between any point on the
window edge and the ceramic test point TP1(9)
30
MHz
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current
draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current
draw.
This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential
inputs must not exceed the specified limit or damage may result to the internal termination resistors.
The highest temperature of the active array (as calculated by the Section 7.6) or of any point along the window edge as defined
in Figure 7-1. The locations of thermal test points TP2 and TP3 in Figure 7-1 are intended to measure the highest window edge
temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be
used.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
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6.2 Storage Conditions
applicable for the DMD as a component or non-operational in a system
TDMD
DMD storage temperature
TDP-AVG
Average dew point temperature, (non-condensing)(1)
(non-condensing)(2)
TDP-ELR
Elevated dew point temperature range,
CTELR
Cumulative time in elevated dew point temperature range
(1)
(2)
MIN
MAX
UNIT
–40
85
°C
24
°C
28
36
°C
6
Months
The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
6.3 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE RANGE(4)
VDD
Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface
1.65
1.8
1.95
V
VDDI
Supply voltage for SubLVDS receivers
1.65
1.8
1.95
V
VOFFSET
Supply voltage for HVCMOS and micromirror electrode(5)
9.5
10
10.5
V
VBIAS
Supply voltage for mirror electrode
VRESET
Supply voltage for micromirror electrode
17.5
18
18.5
V
–14.5
–14
–13.5
V
|VDDI–VDD|
Supply voltage delta (absolute
value)(6)
0.3
V
|VBIAS–VOFFSET|
Supply voltage delta (absolute value)(7)
10.5
V
value)(8)
33
V
|VBIAS–VRESET|
Supply voltage delta (absolute
CLOCK FREQUENCY
ƒclock
Clock frequency for low-speed interface LS_CLK(9)
108
120
MHz
ƒclock
Clock frequency for high-speed interface DCLK(10)
300
540
MHz
44%
56%
Duty cycle distortion DCLK
SUBLVDS INTERFACE(10)
|VID|
SubLVDS input differential voltage (absolute value), see Figure
6-8 and Figure 6-9
150
250
VCM
Common mode voltage, see Figure 6-8 Figure 6-8 and Figure 6-9
700
900
VSUBLVDS
SubLVDS voltage, see Figure 6-8 and Figure 6-9
575
ZLINE
Line differential impedance (PWB/trace)
90
100
110
Ω
ZIN
Internal differential termination resistance, see Figure 6-10
80
100
120
Ω
100-Ω differential PCB trace
350
mV
1100
mV
1225
mV
6.35
152.4
0
40 to 70
–20
–10
–10
0
70
75
mm
ENVIRONMENTAL
Array temperature – long-term operational(11) (13) (14) (15)
Array temperature – short-term operational, 25 hr
(16)
TARRAY
maximum(13)
Array temperature – short-term operational, 500 hr maximum(13)
(16)
Array temperature – short-term operational, 500 hr maximum(13)
(16)
°C
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6.4 Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
MAX
UNIT
|TDELTA|
15
°C
TWINDOW
Window temperature – operational(11) (18)
90
°C
24
°C
36
°C
(non-condensing)(20)
TDP-AVG
Average dew point temperature
TDP-ELR
Elevated dew point temperature range (non-condensing)(19)
CTELR
Cumulative time in elevated dew point temperature range
ILLUV
Illumination wavelengths < 420 nm(11)
ILLVIS
Illumination wavelengths between 420 nm and 700 nm
ILLIR
Illumination wavelengths > 700 nm
10
mW/cm2
ILLθ
Illumination marginal ray angle(12)
55
deg
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
8
NOM
Absolute temperature delta between any point on the window
edge and the ceramic test point TP1(17)
28
6
Months
0.68
mW/cm2
Thermally limited
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.
Section 6.4 are applicable after the DMD is installed in the final product.
The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by
the Section 6.4. No level of performance is implied when operating the device above or below the Section 6.4 limits.
All voltage values are with respect to the ground pins (VSS).
VOFFSET supply transients must fall within specified maximum voltages.
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit.
LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
Refer to the SubLVDS timing requirements in Section 6.7.
Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination will reduce device lifetime.
The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily
been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not
been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)
will contribute to thermal limitations described in this document, and may negatively affect lifetime.
The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Figure 7-1 and the package thermal resistance using Section 7.6.
Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the
DMD experiences in the end application. Refer to Section 7.7 for a definition of micromirror landed duty cycle.
Long-term is defined as the usable life of the device
Short-term is the total cumulative time over the useful life of the device.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure
7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
Window temperature is the highest temperature on the window edge shown in Figure 7-1. The locations of thermal test points TP2 and
TP3 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on
the window edge to be at a higher temperature, that point should be used.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
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Max Recommended Array Temperature –
Operational (°C)
DLPS099B – FEBRUARY 2018 – REVISED MAY 2022
80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
100/0
95/5
90/10
85/15
80/20
75/25
70/30
65/35
Micromirror Landed Duty Cycle
60/40
55/45
D001
Figure 6-1. Maximum Recommended Array Temperature – Derating Curve
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6.5 Thermal Information
DLP3010
THERMAL
METRIC(1)
UNIT
FQK (LGA)
57 PINS
Active area to test point 1 (TP1)(1)
Thermal resistance
(1)
5.4
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on
the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed
by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy
falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the
device.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)(1)
TEST CONDITIONS(3)
PARAMETER
MIN
TYP
MAX
UNIT
CURRENT
IDD
Supply current: VDD(4) (6)
IDDI
Supply current: VDDI(4) (6)
IOFFSET
Supply current: VOFFSET(5) (7)
IBIAS
Supply current: VBIAS(5) (7)
IRESET
Supply current: VRESET(7)
VDD = 1.95 V
60.5
VDD = 1.8 V
54
VDDI = 1.95 V
16.5
VDD = 1.8 V
11.3
VOFFSET = 10.5 V
2.2
VOFFSET = 10 V
1.5
VBIAS = 18.5 V
0.6
VBIAS = 18 V
0.3
VRESET = –14.5 V
2.4
VRESET = –14 V
1.7
mA
mA
mA
mA
mA
POWER(2)
VDD = 1.95 V
PDD
Supply power dissipation: VDD(4) (6)
PDDI
Supply power dissipation: VDDI(4) (6)
POFFSET
Supply power dissipation: VOFFSET(5) (7)
PBIAS
Supply power dissipation: VBIAS(5) (7)
PRESET
Supply power dissipation: VRESET(7)
PTOTAL
Supply power dissipation: Total
LPSDR
VIH(DC)
VDD = 1.8 V
VDDI = 1.95 V
20
VOFFSET = 10.5 V
23
VOFFSET = 10 V
15
VBIAS = 18.5 V
11
VBIAS = 18 V
6
VRESET = –14.5 V
35
VRESET = –14 V
24
162.2
voltage(10)
DC input low
AC input high voltage(10)
voltage(10)
VIL(AC)
AC input low
∆VT
Hysteresis ( VT+ – VT– )
See Figure 6-10
IIL
Low–level input current
VDD = 1.95 V; VI = 0 V
IIH
High–level input current
VDD = 1.95 V; VI = 1.95 V
10
32
VDD = 1.8 V
DC input high voltage(10)
VIH(AC)
VOH
97.2
219
mW
mW
mW
mW
mW
mW
INPUT(8)
VIL(DC)
LPSDR
118
0.7 × VDD
VDD + 0.3
V
–0.3
0.3 × VDD
V
0.8 × VDD
VDD + 0.3
V
–0.3
0.2 × VDD
V
0.1 × VDD
0.4 × VDD
V
–100
nA
100
nA
OUTPUT(9)
DC output high voltage
IOH = –2 mA
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0.8 × VDD
V
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6.6 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)(1)
TEST CONDITIONS(3)
PARAMETER
VOL
DC output low voltage
MIN
TYP
MAX
UNIT
IOL = 2 mA
0.2 × VDD
V
Input capacitance LPSDR
ƒ = 1 MHz
10
Input capacitance SubLVDS
ƒ = 1 MHz
10
COUT
Output capacitance
ƒ = 1 MHz
10
pF
CRESET
Reset group capacitance
ƒ = 1 MHz; (720 × 160)
micromirrors
220
pF
CAPACITANCE
CIN
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
200
pF
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
Supply power dissipation based on non–compressed commands and data.
Supply power dissipation based on 3 global resets in 200 µs.
LPSDR specifications are for pins LS_CLK and LS_WDATA.
LPSDR specification is for pin LS_RDATA.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
6.7 Timing Requirements
Device electrical characteristics are over Section 6.4 unless otherwise noted.
MIN
NOM
MAX
UNIT
1
3
V/ns
(70% to 20%) × VDD, see Figure 6-3
1
3
V/ns
(20% to 80%) × VDD, see Figure 6-3
0.25
(80% to 20%) × VDD, see Figure 6-3
0.25
LPSDR
tr
Rise slew rate(1)
rate(1)
tƒ
Fall slew
tr
Rise slew rate(2)
rate(2)
(30% to 80%) × VDD, see Figure 6-3
V/ns
tƒ
Fall slew
tc
Cycle time LS_CLK,
See Figure 6-2
7.7
tW(H)
Pulse duration LS_CLK high 50% to 50% reference points, see Figure 6-2
3.1
ns
tW(L)
Pulse duration LS_CLK low 50% to 50% reference points, see Figure 6-2
3.1
ns
tsu
Setup time
LS_WDATA valid before LS_CLK ↑, see Figure
6-2
1.5
ns
th
Hold time
LS_WDATA valid after LS_CLK ↑, see Figure
6-2
1.5
ns
tWINDOW
Window time(1) (4)
Setup time + hold time, see Figure 6-2
3
ns
Window time derating(1) (4)
For each 0.25-V/ns reduction in slew rate below
1 V/ns, see Figure 6-5
tr
Rise slew rate
20% to 80% reference points, see Figure 6-4
tƒ
Fall slew rate
80% to 20% reference points, see Figure 6-4
tc
Cycle time DCLK,
See Figure 6-6
tW(H)
Pulse duration DCLK high
50% to 50% reference points, see Figure 6-6
0.79
ns
tW(L)
Pulse duration DCLK low
50% to 50% reference points, see Figure 6-6
0.79
ns
tsu
Setup time
D(0:3) valid before
DCLK ↑ or DCLK ↓, see Figure 6-6
th
Hold time
D(0:3) valid after
DCLK ↑ or DCLK ↓, see Figure 6-6
tWINDOW
Window time
Setup time + hold time, see Figure 6-6 and
Figure 6-7
tDERATING
V/ns
8.3
ns
0.35
ns
SubLVDS
0.7
1
V/ns
0.7
1
V/ns
1.79
1.85
ns
0.3
ns
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6.7 Timing Requirements (continued)
Device electrical characteristics are over Section 6.4 unless otherwise noted.
MIN
tLVDSENABLE+REFGEN
(1)
(2)
(3)
(4)
NOM
Power-up receiver(3)
MAX
UNIT
2000
ns
Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.
Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3.
Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 ns to 3.7 ns.
tc
tw(H)
LS_CLK
50%
tw(L)
50%
50%
th
tsu
LS_ WDATA
50%
50%
twindow
Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B,
Low Power Double Data Rate (LPDDR) JESD209B.
Figure 6-2. LPSDR Switching Parameters
LS_CLK, LS_WDATA
DMD_DEN_ARSTZ
1.0 * VDD
1.0 * VDD
0.8 * VDD
0.7 * VDD
VIH(AC)
VIH(DC)
0.3 * VDD
0.2 * VDD
VIL(DC)
VIL(AC)
0.8 * VDD
0.2 * VDD
0.0 * VDD
0.0 * VDD
tr
tf
tr
tf
Figure 6-3. LPSDR Input Rise and Fall Slew Rate
12
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VDCLK_P , VDCLK_N
VD_P(0:7) , VD_N(0:7)
1.0 * VID
0.8 * VID
VCM
0.2 * VID
0.0 * VID
tr
tf
Figure 6-4. SubLVDS Input Rise and Fall Slew Rate
VIH MIN
LS_CLK Midpoint
VIL MAX
tSU
tH
VIH MIN
LS_WDATA Midpoint
VIL MAX
tWINDOW
VIH MIN
Midpoint
LS_CLK
VIL MAX
tDERATING
tSU
tH
VIH MIN
Midpoint
LS_WDATA
VIL MAX
tWINDOW
Figure 6-5. Window Time Derating Concept
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tc
tw(L)
DCLK _ P
DCLK _ N
tw(H)
50%
50%
50%
th
tsu
D_P (0:7)
D_N(0:7)
50%
50%
twindow
Figure 6-6. SubLVDS Switching Parameters
High Speed Training Scan Window
tc
DCLK _ P
DCLK _ N
¼ tc
¼ tc
D_P (0:7)
D_N(0:7)
Note: Refer to Section 7.3.3 for details.
Figure 6-7. High-Speed Training Scan Window
(VIP + V IN) / 2
DCLK _P , D_P(0:7)
SubLVDS
Receiver
VID
DCLK _N , D_N(0:7)
VCM
VIP
VIN
Figure 6-8. SubLVDS Voltage Parameters
14
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1.225V
V SubLVDS max = V CM max + | 1/2 * V ID max |
VCM
VID
VSubLVDS min = VCM min – | 1/2 * VID max |
0.575V
Figure 6-9. SubLVDS Waveform Parameters
DCLK _P , D_P(0:7)
ESD
Internal
Termination
SubLVDS
Receiver
DCLK _N , D_N(0:7)
ESD
Figure 6-10. SubLVDS Equivalent Input Circuit
Not to Scale
VIH
VT+
Δ VT
VT-
VIL
LS_CLK
LS_WDATA
Figure 6-11. LPSDR Input Hysteresis
LS_CLK
LS_WDATA
Stop Start
tPD
LS_RDATA
Acknowledge
Figure 6-12. LPSDR Read Out
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Data Sheet Timing Reference Point
Device Pin
Output Under Test
Tester Channel
CL
See Section 7.3.4 for more information.
Figure 6-13. Test Load Circuit for Output Propagation Measurement
6.8 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)(1).
PARAMETER
tPD
TEST CONDITIONS
Output propagation, clock to Q, rising edge
of LS_CLK input to LS_RDATA output, see
Figure 6-12
TYP
MAX
11.1
CL = 10 pF
11.3
CL = 85 pF
15
Slew rate, LS_RDATA
0.5
Output duty cycle distortion, LS_RDATA
(1)
MIN
CL = 5 pF
UNIT
ns
V/ns
40%
60%
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
6.9 System Mounting Interface Loads
PARAMETER
Maximum system mounting
interface load to be applied to the:
MIN
Electrical interface area, see Figure 6-14
MAX
125
Clamping and thermal interface area, see Figure 6-14
Electrical Interface Area
125 N Maximum
NOM
67
UNIT
N
Clamping and Thermal Interface Area # 1
33.5 N Maximum
Clamping and Thermal Interface Area # 2
33.5 N Maximum
Figure 6-14. System Interface Loads
16
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6.10 Micromirror Array Physical Characteristics
PARAMETER
ε
(1)
VALUE
UNIT
Number of active columns
See Figure 6-15
1280
micromirrors
Number of active rows
See Figure 6-15
720
micromirrors
Micromirror (pixel) pitch
See Figure 6-16
5.4
µm
Micromirror active array width
Micromirror pitch × number of active columns; see Figure 6-15
6.912
mm
Micromirror active array height
Micromirror pitch × number of active rows; see Figure 6-15
3.888
mm
Micromirror active border
Pond of micromirror (POM)(1)
20
micromirrors/side
The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
Not To Scale
Width
Mirror
Mirror
Mirror
Mirror
719
718
717
716
Height
Illumination
DMD Active Mirror Array
1280 Mirrors * 720 Mirrors
3
2
1
0
Mirror
Mirror
Mirror
Mirror
Mirror
Mirror
Mirror
Mirror
1276
1277
1278
1279
0
1
2
3
Mirror
Mirror
Mirror
Mirror
Figure 6-15. Micromirror Array Physical Characteristics
ε
ε
ε
ε
Figure 6-16. Mirror (Pixel) Pitch
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6.11 Micromirror Array Optical Characteristics
PARAMETER
Micromirror tilt angle
TEST CONDITIONS
DMD landed
Micromirror tilt angle tolerance(2) (3) (4) (5)
Micromirror tilt direction (6) (7)
180
270
Typical performance
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
18
degree
degree
3
10
Gray 10 Screen (12)
0
Bright pixel(s) in the POM (13) Gray 10 Screen (12)
1
Dark pixel(s) in the active
area (14)
White Screen
4
Adjacent pixel(s) (15)
Any Screen
0
Unstable pixel(s) in active
area (16)
Any Screen
0
(11)
(1)
(2)
(3)
(4)
1
UNIT
degree
1.4
Landed OFF state
Typical performance
MAX
17
Landed ON state
Micromirror switching time(9)
Image
performance(10)
NOM
–1.4
Micromirror crossover time(8)
Bright pixel(s) in active area
MIN
state(1)
µs
micromirrors
Measured relative to the plane formed by the overall micromirror array.
Additional variation exists between the micromirror array and the package datums.
Represents the landed tilt angle variation relative to the nominal landed tilt angle.
Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations, or system contrast variations.
When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state
direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See Figure 6-17.
Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is
aligned with the +X Cartesian axis.
The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
The minimum time between successive transitions of a micromirror.
Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear
Test set brightness and contrast shall be set to nominal
The diagonal size of the projected image shall be a minimum of 20 inches
The projections screen shall be 1X gain
The projected image shall be inspected from a 38 inch minimum viewing distance
The image shall be in focus during all image quality tests
Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels
Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
POM definition: Rectangular border of off-state mirrors surrounding the active area
Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels
Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster
Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable
pixel appears to be flickering asynchronously with the image
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(1279, 719)
Incident
Illumination
Light Path
Tilted Axis of
Pixel Rotation
On-State
Landed Edge
Off-State
Landed Edge
(0,0)
Off-State
Light Path
Figure 6-17. Landed Pixel Orientation and Tilt
6.12 Window Characteristics
PARAMETER(3)
MIN
Window material designation
Window refractive index
NOM
MAX
at wavelength 546.1 nm
1.5119
Window aperture(1)
See (1)
Illumination overfill(2)
See (2)
Window transmittance, single-pass
through both surfaces and glass
Minimum within the wavelength range
420 nm to 680 nm. Applies to all angles
0° to 30° AOI.
97%
Window transmittance, single-pass
through both surfaces and glass
Average over the wavelength range 420
nm to 680 nm. Applies to all angles 30°
to 45° AOI.
97%
(1)
(2)
(3)
UNIT
Corning Eagle XG
See the package mechanical characteristics for details regarding the size and location of the window aperture.
The active area of the DLP3010 device is surrounded by an aperture on the inside of the DMD window surface that masks structures
of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating
the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The
illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux
level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light
on the outside of the active array may cause system performance degradation.
See Optical Interface and System Image Quality Considerations for more information.
6.13 Chipset Component Usage Specification
Note
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
The DLP3010 is a component of one or more DLP® chipsets. Reliable function and operation of the DLP3010
requires that it be used in conjunction with the other components of the applicable DLP chipset, including
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those components that contain or implement TI DMD control technology. TI DMD control technology is the TI
technology and devices for operating or controlling a DLP DMD.
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7 Detailed Description
7.1 Overview
The DLP3010 is a 0.3-in diagonal spatial light modulator of aluminum micromirrors. Pixel array size is 1280
columns by 720 rows in a square grid pixel arrangement. The electrical interface is sub low voltage differential
signaling (SubLVDS) data.
DLP3010 is part of the chipset comprising of the DLP3010 DMD, DLPC3433 or DLPC3438 display controller and
DLPA200x/DLPA3000 PMIC/LED driver. To ensure reliable operation, DLP3010 DMD must always be used with
DLPC3433 or DLPC3438 display controller and DLPA200x/DLPA3000 PMIC/LED driver.
7.2 Functional Block Diagram
A.
Details omitted for clarity.
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7.3 Feature Description
7.3.1 Power Interface
The power management IC, DLPA200x/DLPA3000, contains 3 regulated DC supplies for the DMD reset circuitry:
VBIAS, VRESET and VOFFSET, as well as the two regulated DC supplies for the DLPC3433 or DLPC3438
controller.
7.3.2 Low-Speed Interface
The low-speed interface handles instructions that configure the DMD and control reset operation. LS_CLK is the
low-speed clock, and LS_WDATA is the low-speed data input.
7.3.3 High-Speed Interface
The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high-speed
DDR transfer and compression techniques to save power and time. The high-speed interface is composed of
differential SubLVDS receivers for inputs, with a dedicated clock.
7.3.4 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 6-13 shows an equivalent test load circuit for the
output under test. Timing reference loads are not intended as a precise representation of any particular system
environment or depiction of the actual load presented by a production test. System designers should use IBIS
or other simulation tools to correlate the timing reference load to a system environment. The load capacitance
value stated is only for characterization and measurement of AC timing signals. This load capacitance value
does not indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC3433 or DLPC3438 controller. See the DLPC3430 or
DLPC3435 controller data sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device micromirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from
the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from
any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger
than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts
in the display border and/or active area could occur.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display’s border and/or active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
22
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7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system
should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately
10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill
light may have to be further reduced below the suggested 10% level in order to be acceptable.
7.6 Micromirror Array Temperature Calculation
TP3
Illumination
Direction
TP2
Off-state Light
Window Edge
(4 surfaces)
TP2
TP3
TP1
TP1
Figure 7-1. DMD Thermal Test Points
Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat
load. The relationship between micromirror array temperature and the reference ceramic temperature is provided
by the following equations:
•
•
•
•
•
•
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC)
(1)
QARRAY = QELECTRICAL + QILLUMINATION
(2)
QILLUMINATION = (CL2W × SL)
(3)
TARRAY = Computed DMD array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 7-1
RARRAY–TO–CERAMIC = DMD package thermal resistance from array to outside ceramic (°C/W) specified in
Thermal Information
QARRAY = Total DMD power; electrical plus absorbed (calculated) (W)
QELECTRICAL = Nominal DMD electrical power dissipation (W)
CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below
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•
SL = Measured ANSI screen lumens (lm)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.1 W.
Absorbed optical power from the illumination source is variable and depends on the operating state of the
micromirrors and the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with
total projection efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral
efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and
16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00266
W/lm.
Sample Calculation for typical projection application:
1. TCERAMIC = 55°C, assumed system measurement; see Recommended Operating Conditions for specification
limits.
2. SL = 300 lm
3. QELECTRICAL = 0.100 W
4. CL2W = 0.00266 W/lm
5. QARRAY = 0.100 + (0.00266 × 300) = 0.898 W
6. TARRAY = 55°C + (0.898 W × 5.4°C/W) = 59.84°C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the
time (and in the OFF state 0% of the time), whereas 0/100 would indicate that the pixel is in the OFF state 100%
of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the
landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example,
a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect the DMD’s usable life, and this interaction
can be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD’s usable life. This
is quantified in the de-rating curve shown in Figure 6-1. The importance of this curve is that:
•
•
•
24
All points along this curve represent the same usable life.
All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
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In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at
for a given long-term average landed duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the pixel
will experience a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the grayscale value, as shown in Table 7-1.
Table 7-1. Grayscale
Value and Landed Duty
Cycle
Grayscale
Value
Landed Duty
Cycle
0%
0/100
10%
10/90
20%
20/80
30%
30/70
40%
40/60
50%
50/50
60%
60/40
70%
70/30
80%
80/20
90%
90/10
100%
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given
primary must be displayed in order to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%
×
Blue_Scale_Value)
(4)
where
Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_% represent the percentage of the frame time that red, green,
and blue are displayed (respectively) to achieve the desired white point.
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue
color intensities would be as shown in Table 7-2.
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Table 7-2. Example Landed Duty Cycle for Full-Color
Pixels
Red Cycle
Percentage
Green Cycle
Percentage
Blue Cycle
Percentage
50%
20%
30%
Red Scale
Value
Green Scale
Value
Blue Scale
Value
Landed Duty
Cycle
0%
0%
0%
0/100
100%
0%
0%
50/50
0%
100%
0%
20/80
0%
0%
100%
30/70
12%
0%
0%
6/94
0%
35%
0%
7/93
0%
0%
60%
18/82
100%
100%
0%
70/30
0%
100%
100%
50/50
100%
0%
100%
80/20
12%
35%
0%
13/87
0%
35%
60%
25/75
12%
0%
60%
24/76
100%
100%
100%
100/0
The last factor to account for in estimating the landed duty cycle is any applied image processing. Within
the DLP Controller DLPC3433/DLPC3438, the two functions which affect landed duty cycle are Gamma and
IntelliBright™.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC3430/DLPC3435 controller, gamma is applied to the incoming image data on a pixel-by-pixel basis.
A typical gamma factor is 2.2, which transforms the incoming data as shown in Figure 7-2.
100
90
Output Level (%)
80
Gamma = 2.2
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Input Level (%)
70
80
90
100
D002
Figure 7-2. Example of Gamma = 2.2
From Figure 7-2, if the grayscale value of a given input pixel is 40% (before gamma is applied), then grayscale
value will be 13% after gamma is applied. Therefore, since gamma has a direct impact on displayed grayscale
level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.
The IntelliBright algorithms content adaptive illumination control (CAIC) and local area brightness boost (LABB)
also apply transform functions on the grayscale level of each pixel.
26
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But while amount of gamma applied to every pixel (of every frame) is constant (the exponent, Gamma, is
constant), CAIC and LABB are both adaptive functions that can apply a different amounts of either boost or
compression to every pixel of every frame.
Consideration must also be given to any image processing which occurs before the DLPC3433 or DLPC3438
controller.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
CAUTION
The DLP3010 DMD has mandatory software requirements. Refer to Software Requirements for TI
DLP® Pico™ TRP Digital Micromirror Devices application report for additional information.
The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC3433/
DLPC3438 controller. The new high tilt pixel in the side illuminated DMD increases brightness performance and
enables a smaller system electronics footprint for thickness constrained applications. Applications of interest
include projection embedded in display devices like smartphones, tablets, cameras, and camcorders. Other
applications include wearable (near-eye) displays, battery powered mobile accessory, interactive display, lowlatency gaming display, and digital signage.
DMD power-up and power-down sequencing is strictly controlled by the DLPA200x/DLPA3000. Refer to
Power Supply Recommendations for power-up and power-down specifications. To ensure reliable operation,
DLP3010 DMD must always be used with DLPC3433 or DLPC3438 display controller and DLPA200x/DLPA3000
PMIC/LED driver.
8.2 Typical Application
A common application when using the DLPC3433/DLPC3438 is for creating a pico-projector that can be used
as an accessory to a smartphone, tablet or a laptop. The DLPC3433/DLPC3438 in the pico-projector receives
images from a multimedia front end within the product as shown in the following figure.
28
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BAT
±
Charger
+
DC_IN
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...
2.3 V-5.5 V
Projector Module Electronics
DC Supplies
1.8 V
On/Off
Other
Supplies
1.8V
L3
1.8 V
HDMI
VGA
1.1 V
1.1 V
Reg
SYSPWR
VDD
VSPI
HDMI
Receiver
PROJ_ON
Triple
ADC
Keystone
Sensor
PROJ_ON
GPIO_8
(Normal Park)
SPI_0
SPI_1
Front-End
Chip
FLASH,
SDRAM
- OSD
- AutoLock
- Scaler
- uController
Keypad
SD Card
Reader, etc.
(optional)
1.8 V
PAD2005
4
FLASH
4
RESETZ
INTZ
PARKZ
HOST_IRQ
BIAS, RST, OFS
3
LED_SEL(2)
DPP3433/8
VLED
Curr
entS
L1
ense
L2
RED
GREEN
BLUE
WPC
LABB
CMP_PWM
Parallel I/F
28
Illuminatio
nOptics
CMP_OUT
Thermistor
I2C
1.8 V
1.1 V
VIO
VCC_INTF
VCC_FLSH
VCORE
Sub-LVDS DATA
CTRL
18
DLP3010A
WVGA
720p
DDR DMD
Spare R/
W GPIO
Included in DLP® Chip Set
Non-DLP components
Copyright © 2017, Texas Instruments Incorporated
Figure 8-1. Typical Application Diagram
8.2.1 Design Requirements
A pico-projector is created by using a DLP chip set comprised of DLP3010 DMD, a DLPC3433/DLPC3438
controller and a DLPA200x/DLPA3000 PMIC/LED driver. The DLPC3433/DLPC3438 controller does the digital
image processing, the DLPA200x/DLPA3000 provides the needed analog functions for the projector, and
DLP3010 DMD is the display device for producing the projected image.
In addition to the three DLP chips in the chip set, other chips may be needed. At a minimum a Flash part is
needed to store the software and firmware to control the DLPC3433/DLPC3438 controller.
The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often
contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the pico-projector.
For connecting the DLPC3433/DLPC3438 controller to the multimedia front end for receiving images, parallel
interface is used. When the parallel interface is used, I2C should be connected to the multimedia front end for
sending commands to the DLPC3433/DLPC3438 controller and configuring the DLPC3433/DLPC3438 controller
for different features.
8.2.2 Detailed Design Procedure
For connecting together the DLPC3433/DLPC3438 controller, the DLPA200x/DLPA3000, and the DLP3010
DMD, see the reference design schematic. When a circuit board layout is created from this schematic a very
small circuit board is possible. An example small board layout is included in the reference design data base.
Layout guidelines should be followed to achieve a reliable projector.
The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical
OEM who specializes in designing optics for DLP projectors.
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8.2.3 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased,
the brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is as shown in Figure 8-2. For the LED currents shown, it’s assumed
that the same current amplitude is applied to the red, green, and blue LEDs.
1
0.9
0.8
Luminance
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
500
1000
1500
Current (mA)
2000
2500
3000
D001
Figure 8-2. Luminance vs Current
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and
VRESET. DMD power-up and power-down sequencing is strictly controlled by the DLPA200x devices.
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to the prescribed power-up and power-down procedures may affect
device reliability.
VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during powerup and power-down operations. Failure to meet any of the below requirements will result in a
significant reduction in the DMD’s reliability and lifetime. Refer to Figure 9-2. VSS must also be
connected.
9.1 Power Supply Power-Up Procedure
•
•
•
•
During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET
voltages are applied to the DMD.
During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in Recommended Operating Conditions. Refer to Table 9-1 and the Layout Example for
power-up delay requirements.
During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled
at operating voltage.
During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow
the requirements listed previously and in Figure 9-1.
9.2 Power Supply Power-Down Procedure
•
•
•
•
•
Power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be
supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement
that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended
Operating Conditions (refer to Note 2 for Figure 9-1).
During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in
Recommended Operating Conditions.
During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed previously and in Figure 9-1.
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9.3 Power Supply Sequencing Requirements
DLP Display Controller and
PMIC control start of DMD
operation
DRAWING NOT TO SCALE.
DETAILS OMITTED FOR CLARITY.
DLP Display Controller and PMIC
disable VBIAS, VOFFSET and
VRESET
Mirror Park
Sequence
Note 4
Power Off
VDD / VDDI
VDD / VDDI
VDD / VDDI VSS
VSS
VOFFSET
VOFFSET
9'' ” 92))6(7 < 6 V
VOFFSET
VBIAS < 4 V
VSS
Note 2
Note 3
Note 1
Note 2
VSS
ûV < Specification Limit
9'' ” 9%,$6 < 6 V
ûV < Specification Limit
VBIAS
ûV < Specification Limit
VBIAS
VBIAS
VOFFSET < 4 V
VSS
VSS
VRESET < 0.5 V
VSS
VSS
VRESET > - 4 V
VRESET
VRESET
VRESET
VDD
VDD
DMD_DEN_ARSTZ VSS
INITIALIZATION
LS_CLK
LS_WDATA
VSS
VDD
VDD
VSS
VSS
VID
VID
D_P(0:7), D_N(0:7)
DCLK_P, DCLK_N
VSS
VSS
A.
B.
Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Section 6.4. OEMs may find that
the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET
during power-down. Refer to Table 9-1 and Figure 9-2 for power-up delay requirements.
C.
D.
To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Section 6.4.
When system power is interrupted, the DLPA200x initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after
the Micromirror Park Sequence.
Drawing is not to scale and details are omitted for clarity.
E.
Figure 9-1. Power Supply Sequencing Requirements (Power Up and Power Down)
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Table 9-1. Power-Up Sequence Delay Requirement
PARAMETER
MIN
MAX
2
UNIT
tDELAY
Delay requirement from VOFFSET power up to VBIAS power up
ms
VOFFSET
Supply voltage level during power–up sequence delay (see Figure 9-2)
6
V
VBIAS
Supply voltage level during power–up sequence delay (see Figure 9-2)
6
V
12 V
VOFFSET
8V
VDD ≤ VOFFSET < 6 V
4V
VSS
tDELAY
0V
VBIAS
20 V
16 V
12 V
8V
VDD ≤ VBIAS < 6 V
4V
VSS
A.
0V
Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
Figure 9-2. Power-Up Sequence Delay Requirement
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10 Layout
10.1 Layout Guidelines
There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board
connector to a flex cable. Flex cable provides the interface of data and CTRL signals between the DLPC343x
controller and the DLP3010 DMD. For detailed layout guidelines refer to the layout design files. Some layout
guideline for the flex cable interface with DMD are:
•
•
•
•
•
•
Match lengths for the LS_WDATA and LS_CLK signals.
Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 10-1.
Minimum of two 100-nF decoupling capacitor close to VBIAS. Capacitor C6 and C7 in Figure 10-1.
Minimum of two 100-nF decoupling capacitor close to VRST. Capacitor C9 and C8 in Figure 10-1.
Minimum of two 220-nF decoupling capacitor close to VOFS. Capacitor C5 and C4 in Figure 10-1.
Minimum of four 100-nF decoupling capacitor close to Vcci and Vcc. Capacitor C1, C2, C3 and C10 in Figure
10-1.
10.2 Layout Example
Figure 10-1. Power Supply Connections
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Device Nomenclature
DLP3010A FQK
Package Type
Device Descriptor
Figure 11-1. Part Number Description
11.1.3 Device Markings
The device marking includes the legible character string GHJJJJK DLP3010AFQK. GHJJJJK is the lot trace
code. DLP3010AFQK is the device part number.
Lot Trace Code
GHJJJJK
DLP3010AFQK
Part Marking
Figure 11-2. DMD Marking
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DLP3010A
Click here
Click here
Click here
Click here
Click here
DLPC3433
Click here
Click here
Click here
Click here
Click here
DLPC3438
Click here
Click here
Click here
Click here
Click here
DLPA2005
Click here
Click here
Click here
Click here
Click here
DLPA3000
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
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11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
IntelliBright™, Pico™, and TI E2E™ are trademarks of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
DLP3010AFQK
ACTIVE
CLGA
FQK
57
120
RoHS & Green
NI/AU
N / A for Pkg Type
0 to 70
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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