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DRV3220-Q1
SLVSDM3 – FEBRUARY 2017
DRV3220-Q1 Three-Phase Automotive Gate Driver With Enhanced Protection,
Diagnostics, and Monitoring
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
•
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•
AEC-Q100 Qualified for Automotive Applications:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Three-Phase Bridge Driver for Motor Control
Suitable for 12-V and 24-V Applications
Integrated Boost Converter, Gate Drive to 4.75 V
Drives 6 Separate N-Channel Power MOSFETs
Strong 1-A Gate Drive for High-Current FETs
Programmable Dead Time
PWM Frequency up to 20 kHz
Supports 100% Duty Cycle Operation
Short-Circuit Protection
– VDS-Monitoring (Adjustable Detection Level)
Overvoltage and Undervoltage Protection
Overtemperature Warning and Shut Down
Sophisticated Failure Detection and Handling
Through SPI
System Supervision
– Q&A Watchdog
– I/O Supply Monitoring
– ADREF Monitoring
Programmable Internal Fault Diagnostics
Sleep Mode Function
Thermally-Enhanced 48-Pin HTQFP PowerPAD™
IC Package (7-mm × 7-mm Body)
•
Automotive Motor-Control Applications
– Electrical Power Steering (EPS, EHPS)
– Electrical Brake and Brake Assist
– Transmission
– Pumps
Industrial Motor-Control Applications
3 Description
The DRV3220-Q1 bridge driver is dedicated to
automotive three-phase brushless DC motor control
applications. The device provides six dedicated
drivers for standard-level N-channel MOSFET
transistors. A boost converter with an integrated FET
provides the overdrive voltage, allowing full control on
the power stages even for low battery voltage down
to 4.75 V. The strong driver strength is suitable for
high-current applications and programmable to limit
peak output current.
The device incorporates robust FET protection and
system monitoring functions like a Q&A watchdog
and voltage monitors for I/O supplies and ADC
reference voltages. Integrated internal diagnostic
functions can be accessed and programmed through
an SPI interface.
Device Information(1)
PART NUMBER
DRV3220-Q1
PACKAGE
HTQFP (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
3.3 V, 5 V
12 V, 24 V
PWM
(3× or 6× pins)
/
Controller
SPI
//
DRV3220-Q1
Driver
40
Protection
W
Diagnostics
FETs
M
S/D
Paths
ADC
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV3220-Q1
SLVSDM3 – FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
7.4 Register Maps ......................................................... 17
1
1
1
2
3
5
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 20
8.3 System Example ..................................................... 20
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 22
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Serial Peripheral Interface Timing Requirements ... 11
Typical Characteristics ............................................ 12
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Programming........................................................... 14
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
February 2017
*
Initial release.
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Product Folder Links: DRV3220-Q1
DRV3220-Q1
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SLVSDM3 – FEBRUARY 2017
5 Pin Configuration and Functions
ILS1
ILS2
ILS3
IHS1
IHS2
IHS3
NU
NU
NU
NU
NU
NU
48
47
46
45
44
43
42
41
40
39
38
37
PHP PowerPAD™ Package
48-Pin HTQFP
Top View
GLS3
1
36
NU
SLS3
2
35
NU
GHS3
3
34
NU
SHS3
4
33
ADREF
VSH
5
32
VCC5
SHS2
6
31
NU
GHS2
7
30
GNDA
SLS2
8
29
VCC3
GLS2
9
28
SDI
TEST
10
27
SDO
GLS1
11
26
SCLK
SLS1
12
25
VDDIO
Thermal
24
Not to scale
EN
23
GNDLS_B
22
NCS
21
SW
20
BOOST
19
RVSET
18
DRVOFF
17
ERR
16
GNDA
15
VS
14
SHS1
GHS1
13
Pad
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
1
GLS3
PWR
Gate low-side 3, connected to gate of external power MOSFET.
2
SLS3
PWR
Source low-side 3, connected to external power MOSFET for gate discharge and VDS monitoring.
3
GHS3
PWR
Gate high-side 3, connected to gate of external power MOSFET.
4
SHS3
PWR
Source high-side 3, connected to external power MOSFET for gate discharge and VDS monitoring.
5
VSH
HVI_A
Sense high-side, sensing VS connection of the external power MOSFETs for VDS monitoring.
6
SHS2
PWR
Source high-side 2, connected to external power MOSFET gate discharge and VDS monitoring.
7
GHS2
PWR
Gate high-side 2, connected to gate of external power MOSFET.
8
SLS2
PWR
Source low-side 2, connected to external power MOSFET for gate discharge and VDS monitoring.
9
GLS2
PWR
Gate low-side 2, connected to gate of external power MOSFET.
10
TEST
HVI_A
Test mode input, during normal application connected to ground.
(1)
Description of pin type: GND = Ground; HVI_A = High-voltage input analog; HVI_D = High-voltage input digital; LVI_A = Low-voltage
input analog; LVO_A = Low-voltage output analog; LVO_D = Low-voltage output digital; NC = No connect; PWR = Power output; Supply
= Supply input
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Pin Functions (continued)
PIN
TYPE (1)
DESCRIPTION
NO.
NAME
11
GLS1
PWR
Gate low-side 1, connected to gate of external power MOSFET.
12
SLS1
PWR
Source low-side 1, connected to external power MOSFET for gate discharge and VDS monitoring.
13
GHS1
PWR
Gate high-side 1, connected to gate of external power MOS transistor.
14
SHS1
PWR
Source high-side 1, connected to external power MOS transistor for gate discharge and VDS.
15
VS
Supply
16
GNDA
GND
17
ERR
LVO_D
Error (low active), Error pin to indicate detected error.
18
DRVOFF
HVI_D
Driver OFF (high active), secondary bridge driver disable.
19
RVSET
HVI_A
VDDIO / ADREF OV/UV configuration resister.
20
BOOST
Supply
Boost output voltage, used as supply for the gate drivers.
21
SW
PWR
22
NCS
HVI_D
23
GNDLS_B
GND
Power-supply voltage (externally protected against reverse battery connection).
Analog ground.
Boost converter switching node connected to external coil and external diode.
SPI chip select.
Boost GND to set current limit. Boost switching current goes through this pin through external resistor to
ground.
24
EN
HVI_D
Enable (high active) of the device.
25
VDDIO
Supply
I/O supply voltage, defines the interface voltage of digital I/O, for example, SPI.
26
SCLK
HVI_D
SPI clock.
27
SDO
LVO_D
SPI data output.
28
SDI
HVI_D
SPI data input.
29
VCC3
LVO_A
VCC3 regulator, for internal use only. TI recommends an external decoupling capacitor of 0.1 µF.
External load < 100 µA.
30
GNDA
GND
31
NU
—
32
VCC5
LVO_A
VCC5 regulator, for internal use only. Recommended external decoupling capacitor 1 µF. External load
< 100 µA.
33
ADREF
LVI_A
ADC reference of MCU. Connect to VDDIO
34
NU
—
Not used. Leave this pin open.
35
NU
—
Not used. Leave this pin open.
36
NU
—
Not used. Leave this pin open.
37
NU
—
Not used. Connect this pin to ground.
38
NU
—
Not used. Connect this pin to ground.
39
NU
—
Not used. Connect this pin to ground.
40
NU
—
Not used. Connect this pin to ground.
41
NU
—
Not used. Connect this pin to ground.
42
NU
—
Not used. Connect this pin to ground.
43
IHS3
HVI_D
High-side input 3, digital input to drive the HS3.
44
IHS2
HVI_D
Input HS 2, digital input to drive the HS2.
45
IHS1
HVI_D
Input HS 1, digital input to drive the HS1.
46
ILS3
HVI_D
Low-side input 3, digital input to drive the LS3.
47
ILS2
HVI_D
Input LS 2, digital input to drive the LS2.
48
ILS1
HVI_D
Input LS 1, digital input to drive the LS1.
4
Analog ground.
Not used. Leave this pin open.
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SLVSDM3 – FEBRUARY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
POS
2.1
VS, VSH
2.1a
VS
2.1c
DC voltage
2.1b
VSH
2.1d
MIN
MAX
UNIT
–0.3
60
V
Negative voltages with minimum serial resistor 5 Ω,
TA = 25°C
–5
V
Negative voltages with minimum serial resistor 5 Ω,
TA = 105°C
–2.5
V
Negative voltages with minimum serial resistor 10 Ω,
TA = 25°C
–5
V
Negative voltages with minimum serial resistor 10 Ω,
TA = 105°C
–2.5
V
2.2A
Gate high-side voltage
GHSx
–9
70
V
2.2B
Source high-side voltage
SHSx
–9
70
V
2.3
Gate-source high-side voltage
difference
GHSxSHSx
–0.3
15
V
2.4
Gate low-side voltage
GLSx
–9
20
V
2.5
Source low-side voltage
SLSx
–9
7
V
2.6
Gate-source low-side voltage
difference
GLSxSLSx
–0.3
15
V
2.7
Boost converter
BOOST, SW
–0.3
70
V
VDDIO
–0.3
60
V
ADREF
–0.3
60
V
RVSET
–0.3
60
V
2.9
2.9a
Analog input voltage
2.11
Externally driven, internal limited, see position 5.4 in
Electrical Characteristics
Externally driven, internal limited, see position 5.5 in
Electrical Characteristics
2.10
Digital input voltage
ILSx,IHSx, EN, DRVOFF, SCLK, NCS, SDI
–0.3
60
V
2.13
Difference between GNDA and
GNDLS_B
GNDA, GNDLS_B
–0.3
0.3
V
2.20
Maximum slew rate of SHSx pins, SRSHS
–250
250
V/µs
2.21
Analog and digital output
voltages
ERR, SDO, RO
–0.3
6
V
2.22
Unused pins (connect to GND)
TEST
–0.3
0.3
V
VCC5
–0.3
6
V
VCC3
–0.3
3.6
V
–10
10
mA
80
mA
2.24
2.25
Internal supply voltage
2.21
A
Forced input and output current
ERR, SDO, RO
2.24
A
Short-to-ground current, IVCC5 (3)
Internal current limit
2.26
Short-to-ground current, IVCC3
Limited by VCC5
2.27
Driver FET total gate charge (per VS = 12 V, ƒPWM = 20 kHz, 6 FETs ON/OFF per PWM cycle
FET), Qgmax
VS = 24 V, ƒPWM = 20 kHz, 6 FETs ON/OFF per PWM cycle
2.28
(1)
(2)
(3)
(4)
80
mA
200 (4)
nC
(4)
nC
100
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal, unless specified otherwise.
IVCC5 is not specifying VCC5 output current capability for external load. The allowed external load on VCC5 is specified at position 3.18
in Recommended Operating Conditions.
The maximum value also depends on PCB thermal design, modulation scheme, and motor operation time.
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Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted)(1)(2)
POS
MIN
MAX
UNIT
2.14
Operating virtual junction temperature, TJ
–40
150
°C
2.15
Storage temperature, Tstg
–55
165
°C
6.2 ESD Ratings
POS
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
2.17
2.18
V(ESD)
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
2.19
(1)
All pins
±2000
Pins 4, 6, and 14
±4000
All pins
±500
Corner pins (1, 12, 13, 24, 25, 36, 37,
and 48)
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
POS
MIN
3.1
VVS
Supply voltage, normal voltage
operation
Full device functionality. Operation at VS = 4.75 V
only when coming from higher VS. Minimum VS
for startup = 4.85 V
3.2
VVSLO
Supply voltage, logic operation
Logic functional (during battery cranking after
coming from full device functionality)
3.3
VVDDIO
Supply voltage for digital I/Os
3.14
VCC3
Internal supply voltage
VS > 4 V, external load current 6 V, external load current < 100 µA,
decoupling capacitor typical 1 µF
IVSn
VS quiescent current normal
operation (boost converter
enabled, drivers not switching)
3.6A
3.61A
3.6B
NOM
3.6C
IBOOSTn
BOOST pin quiescent current
normal operation (drivers not
switching)
IVSn
VS quiescent additional current
normal operation because of
RVSET thermal voltage output
enabled (boost converter
enabled, drivers not switching)
IBOOST,sw
BOOST pin additional load
current because of switching gate
drivers
3.6C1
3.61B
3.6D
3.61D
UNIT
4.75
40
V
4
40
V
2.97
5.5
V
3 (1)
3.3
V
5.15
5.45
V
Boost converter enabled, see and for SHSx/SLSx
connections. EN_GDBIAS = 1
22
mA
Boost converter enabled, see and for SHSx/SLSx
connections. EN_GDBIAS = 0
22.3
mA
4.75 V < VS < 20 V, TA = 25°C to 125°C
3.62B
MAX
9
4.75 V < VS < 20 V, TA = –40°C
10
20 < VS < 40 V, TA = 25°C to 125°C
9.5
20 < VS < 40 V, TA = –40°C
10.5
THERMAL_RVSET_EN = 1
0.6
Excluding FET gate charge current. 20-kHz all
gate drivers switching at the same time.
EN_GDBIAS = 1
4
Excluding FET gate charge current. 20-kHz all
gate drivers switching at the same time.
EN_GDBIAS = 0
5.4
mA
mA
mA
3.75
IVSq_1
VS quiescent current shutdown
(sleep mode) 1
VS = 14 V, no operation, TJ < 25°C, EN = Low,
total leakage current on all supply connected pins
20
µA
3.75a
IVSq_2
VS quiescent current shutdown
(sleep mode) 2
VS = 14 V, no operation, TJ < 85°C, EN = Low,
total leakage current on all supply connected pins
30
µA
3.15
IVCC3
VCC3 output current
Intended for MCU ADC input
0
100
µA
3.18
IVCC5
VCC5 output current
Intended for MCU ADC input
0
100
µA
3.16
CVCC3
VCC3 decoupling capacitance
0.075
0.1
0.2
µF
3.19
CVCC5
VCC5 decoupling capacitance
0.5
1
1.5
µF
3.4
D
Duty cycle of bridge drivers
0%
100%
3.5
ƒPWM
PWM switching frequency
0
22 (1)
(1)
6
kHz
Maximum PWM allowed also depends on maximum operating temperature, FET gate charge current, VS supply voltage, modulation
scheme, and PCB thermal design.
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SLVSDM3 – FEBRUARY 2017
Recommended Operating Conditions (continued)
POS
MIN
3.8
TJ
Junction temperature
3.9
TA
Operating ambient free-air
temperature
With proper thermal connection
MAX
UNIT
–40
NOM
150
°C
–40
125
°C
6.4 Thermal Information
DRV3220-Q1
THERMAL METRIC
(1)
PHP (HTQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
25.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
10.3
°C/W
RθJB
Junction-to-board thermal resistance
6
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
5.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating temperature TJ = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V (1), ƒPWM < 20
kHz (unless otherwise noted)
POS
PARAMETER
4.4
ADREF / VDDIO
4.4.3
IADREF
4.4.4
4.4.4a
4.4.5
4.4.5a
4.4.7
4.4.7a
4.4.8
4.4.8a
Vovadref
Vuvadref
Vovvddio
Vuvvddio
ADREF bias current
Overvoltage threshold, ADREF
Undervoltage threshold, ADREF
Overvoltage threshold, VDDIO
Undervoltage threshold, VDDIO
TEST CONDITIONS
MIN
TYP
MAX
UNIT
300
µA
3.696
3.795
3.894
V
5.6
5.75
5.9
V
2.706
2.805
2.904
V
4.1
4.25
4.4
V
3.696
3.795
3.894
V
5.6
5.75
5.9
V
2.706
2.805
2.904
V
VDDIO: 5-V setting by RVSET resistor
4.1
4.25
4.4
V
135
150
165
kΩ
ADREF = 3.3 V, pin to ground
ADREF: 3.3-V setting by RVSET resistor
ADREF: 5-V setting by RVSET resistor
ADREF: 3.3-V setting by RVSET resistor
ADREF: 5-V setting by RVSET resistor
VDDIO: 3.3-V setting by RVSET resistor
VDDIO: 5-V setting by RVSET resistor
VDDIO: 3.3-V setting by RVSET resistor
4.4.10
RRVSET33
VDDIO = 3.3 V; ADREF = 3.3-V mode;
STAT6 bit[3:0] = 4’b0001
4.4.11
RRVSET53
VDDIO = 5 V; ADREF = 3.3-V mode; STAT6
bit[3:0] = 4’b0100
46
51
56.5
kΩ
13.5
15
16.5
kΩ
5.1
5.65
kΩ
RVSET resistance
4.4.12
RRVSET35
VDDIO = 3.3 V; ADREF = 5-V mode; STAT6
bit[3:0] = 4’b1000
4.4.13
RRVSET55
VDDIO = 5 V; ADREF = 5-V mode; STAT6
bit[3:0] = 4’b0010
4.6
4.4.30
RRVSETopen
Open
650
4.4.31
RRVSETshort
4.4.32
VRVSETn40
4.4.33
VRVSET25
4.4.34
VRVSET125
RVSET resistor error detection
RVSET output voltage
Short
1.5
–40°C TJ, THERMAL_RVSET_EN = 1
1.67
1.745
1.82
25°C TJ, THERMAL_RVSET_EN = 1
1.445
1.535
1.625
125°C TJ, THERMAL_RVSET_EN = 1
1.085
1.195
1.305
kΩ
V
VCC3 / VCC5 REGULATORS
4.4.14
VCC3
VCC3 regulator output voltage
VS > 4 V
3
3.15
3.3
V
4.4.15
VCC3UV
VCC3 regulator undervoltage
threshold
VS > 4 V
2.7
2.85
3
V
4.4.16
VCC3OV
VCC3 regulator overvoltage
threshold (2)
VS > 4 V
3.3
3.45
3.6
V
(1)
(2)
Product life time depends on VS voltage, PCB thermal design, modulation scheme, and motor operation time. The product is designed
for 12-V and 24-V battery system.
ADREF / VDDIO overvoltage and undervoltage is set by RVSET.
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Electrical Characteristics (continued)
over operating temperature TJ = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V(1), ƒPWM < 20
kHz (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.15
5.3
5.45
V
4.6
5.45
V
VS > 4.75 V
4.3
4.6
V
VS > 4.75 V
5.45
5.75
V
0.2
V
220
330
kΩ
2
4
kΩ
4.4.17
VCC5_1
VCC5 regulator output voltage 1
VS > 6 V
4.4.18
VCC5_2
VCC5 regulator output voltage 2
6 V > VS > 4.75 V
4.4.19
VCC5UV
VCC5 regulator undervoltage
threshold
4.4.20
VCC5OV
VCC5 regulator overvoltage
threshold
5.
GATE DRIVER
5.1
VGS,low
Gate-source voltage low, highside/low-side driver
Active pulldown, Iload = –2 mA
5.2
RGSp
Passive gate-source resistance
Vgs ≤ 200 mV
5.3
RGSsa
Semi-active gate-source
resistance
In sleep mode, VGS > 2 V
5.3b
IGSL01
5.3c
IGSL00
5.3d
5.6
0
110
Gate driven low by gate driver,
CURR1, 3 = 01, SPI configurable
TYP × 0.65
0.65
TYP × 1.35
A
Gate driven low by gate driver (2),
CURR1, 3 = 00, SPI configurable
TYP × 0.1
0.15
TYP × 1.9
A
IGSL10
Gate driven low by gate driver,
CURR1, 3 = 11, SPI configurable
TYP × 0.65
1.1
TYP × 1.35
A
5.3f
IGSH01
Gate driven low by gate driver,
CURR0, 2 = 01, SPI configurable
TYP × 0.65
0.65
TYP × 1.35
A
5.3g
IGSH00
Gate driven low by gate driver (2),
CURR0, 2 = 00, SPI configurable
TYP × 0.1
0.15
TYP × 1.9
A
5.3h
IGSH11
Gate driven low by gate driver,
CURR0, 2 = 11, SPI configurable
TYP × 0.65
1.1
TYP × 1.35
A
5.3i
IGSHsd
High-side/low-side driver
shutdown current
2
30
70
5.4
VGS,HS,high
High-side output voltage
Iload = –2 mA; 4.75 V < VS < 40 V
9
13.4
V
5.5
VGS,LS,high
Low-side output voltage
Iload = –2 mA
9
13.4
V
350
ns
Low-side driver pullup/pulldown
current
High-side driver pullup/pulldown
current
5.27
tDon
Propagation on delay time
After ILx/IHx rising edge, Cload = 10 nF,
CURR1, 3 = 10, VGS = 1 V
5.31
Adt
Accuracy of dead time
If not disabled in CFG1
5.32
IHSxlk_1
EN = L, SHSx = 1.5 V, TJ < 125°C
5.32a
IHSxlk_2
Source leak current, total
leakage current of source pins
(3)
100
200
–15%
mA
15%
–5
5
µA
EN = L, SHSx = 1.5 V, 125°C < TJ < 150°C
–40
40
µA
ILx/IHx falling edge to VGS,LS,high(VGS,HS,high) –
1 V Ciss = 10 nF, CURR1,3 = 10,
100
350
ns
5.29
tDoff
Propagation off delay time
5.30
tDoffdiff
Propagation off delay time
difference (3)
LSx to LSy and HSx to HSy Cload = 10 nF,
CURR1,3 = 10, VGS,LS,high(VGS,HS,high) – 1 V
50
ns
5.30a
tDon_Doff_diff
Difference between propagation
on delay time and propagation
off delay time (3)
For each gate driver in each channel:
Cload = 10 nF, CURR1, 3 = 10, VGS = 1 V
(rising), VGS,LS,high(VGS,HS,high) – 1 V (falling)
150
ns
5.30c
tENoff
Propagation off (EN) deglitch
time (3)
After falling edge on EN
6
12
µs
5.30d
tSD
Time until gate drivers initiate
shutdown (3)
After falling edge on EN
12
24
µs
5.30e
tSDDRV
Time until gate drivers initiate
shutdown (3)
After rising edge on DRVOFF
10
µs
(3)
8
2.5
200
Ensured by characterization.
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Electrical Characteristics (continued)
over operating temperature TJ = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V(1), ƒPWM < 20
kHz (unless otherwise noted)
POS
PARAMETER
6.
BOOST CONVERTER
6.1
VBOOST
Boost output voltage excluding
switching ripple and response
delay.
6.1b
VBOOSTOV
Boost output voltage overvoltage
with respect GND
6.2
IBOOST
Output current capability
6.3
ƒBOOST
Switching frequency
6.31
6.4
TEST CONDITIONS
BOOST – VS voltage
64
67.5
70
V
7
8
V
10
V
6
µs
200
mV
100
ns
840
1600
mA
0.25
1.5
Ω
2
Ω
VDDIO × 0.3
V
6.5
tBCSD
Filter time for undervoltage
detection
6.7
VGNDLS_B,off
Voltage at GNDLS_B pin at
which boost FET switches off
because of current limit
6.7a
tSW,off
Delay of the GNDLS_B current
limit comparator
6.8
ISW,fail
Internal second-level current limit GNDLS_B = 0 V
2.5
150
Specified by design
VS ≥ 6; ISW = VGNDLS_B,off / 0.33 Ω
VS < 6; ISW= VGNDLS_B,off / 0.33 Ω
7.1
INL
Input low threshold
All digital inputs NCS, DRVOFF, ILSx, IHSx,
SDI
7.1a
ENH
EN input high threshold
VS > 4 V
7.1b
ENL
EN input low threshold
VS > 4 V
INH
Input high threshold
All digital inputs NCS, DRVOFF, ILSx, IHSx,
SDI
Inhys
Input hysteresis
3
MHz
110
DIGITAL INPUTS
2.7
V
0.7
VDDIO × 0.7
V
V
All digital inputs EN, NCS, DRVOFF, ILSx,
IHSx, SDI, VDDIO = 5 V
0.3
0.4
V
All digital inputs EN, NCS, DRVOFF, ILSx,
IHSx, SDI, VDDIO = 3.3 V
0.2
0.3
V
140
200
Rpd,EN
Input pulldown resistor at EN pin
EN
7.4a
tdeg,ENon
Power-up time after EN pin high
from sleep mode to active mode
ERR = L → H
7.5
Rpullup
Input pullup resistance
NCS, DRVOFF
200
7.6
Rpulldown
Input pulldown resistance
ILSx, IHSx, SDI , SCLK Input voltage = 0.1 V
100
Input pulldown current
ILSx, IHSx, SDI, SCLK Input voltage =
VDDIO
7.6a
Rpulldown
8.
DIGITAL OUTPUTS
8.1
OH1
Output high voltage 1
All digital outputs: SDO, I = ±2 mA; VDDIO in
functional range (5)
8.2
OL1
Output low voltage 1
All digital outputs: SDO, I = ±2 mA; VDDIO in
functional range
8.1
OH2
Output high voltage 2
ERR I = –0.2 mA; VDDIO in functional range
8.2
OL2
Output low voltage 2
ERR I = +0.2 mA; VDDIO in functional range
9.
VDS, VGS, MONITORING
9.1
VSCTH
(4)
(5)
mA
5
7.
7.4
V
3
BOOST – GND voltage
7.3a
16.5
1.1
VBOOSTUV2
7.3
15
BOOST – VS > VBOOSTUV; VS < 6 V; ensured
by characterization (4)
6.4a
7.2
14
1.8
BOOST – VS voltage
6.9a
UNIT
BOOST – VS > VBOOSTUV; ensured by
characterization (4)
Undervoltage condition that
device may enter RESET state
Rdson resistance boost FET
MAX
40
Undervoltage shutdown level
Rdson_BSTfet
TYP
External load current including external
MOSFET gate charge current
BOOST – VS > VBOOSTUV
VBOOSTUV
6.9
MIN
VDS short-circuit threshold range If not disabled in CFG1
4
360
kΩ
5
ms
280
400
kΩ
140
200
kΩ
50
µA
VDDIO × 0.9
V
VDDIO × 0.1
VDDIO × 0.9
0.1
V
V
VDDIO × 0.1
V
2
V
During startup when BOOST – VS < VBOOSTUV , ƒBOOST is typically 1.25 MHz.
All digital outputs have a push-pull output stage between VDDIO and ground.
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Electrical Characteristics (continued)
over operating temperature TJ = –40°C to 150°C and recommended operating conditions, VS = 4.75 V to 40 V(1), ƒPWM < 20
kHz (unless otherwise noted)
POS
PARAMETER
TEST CONDITIONS
0.1-V to 0.5-V threshold setting
MIN
TYP
MAX
–50
50
–10%
10%
UNIT
mV
9.2
Avds
Accuracy of VDS monitoring
9.3
tVDS
Detection filter time
Only rising edge of VDS comparators are
filtered
9.4
Vgserr+_1
VGS error detection 1
STAT7, IHSx (ILSx) = H
9.5
Vgserr–
VGS error detection
STAT7, IHSx (ILSx) = L
9.6
tVGS
Detection filter time
CFG6[5:4]
1.0
µs
9.6a
tVGSm
Detection mask time
CFG6[2:0]
2.5
µs
10.
THERMAL SHUTDOWN
10.1
Tmsd0
Thermal recovery
Specified by characterization
130
153
178
°C
10.2
Tmsd1
Thermal warning
Specified by characterization
140
165
190
°C
10.3
Tmsd2
Thermal global reset
Specified by characterization
170
195
220
°C
10.4
Thmsd
Thermal shutdown×2 hysteresis
Specified by characterization
10.5
tTSD1
Thermal warning filter time
Specified by characterization
40
45
50
µs
10.6
tTSD2
Thermal shutdown×2 filter time
Specified by characterization
2.5
6
12
µs
12.
VS MONITORING
12.1
VVS,OVoff0
Programmable CFG5 mode1, 12-V/24-V
mode
29
38
V
12.1a
12.1b
12.1c
12.1d
12.1e
12.1f
12.2
Overvoltage shutdown level
range (6)
(6)
VVS,OVoff1
Overvoltage shutdown level
VVS, OVon1
Recovery level form overvoltage
shutdown (6)
(6)
VVS,OVoff2
Overvoltage shutdown level
VVS, OVon2
Recovery level form overvoltage
shutdown (6)
(6)
VVS,OVoff3
Overvoltage shutdown level
VVS, OVon3
Recovery level form overvoltage
shutdown (6)
VVS,UVoff
Undervoltage shutdown level
12.2a
VVS,UVon
Recovery level form
undervoltage shutdown (6)
12.3
tVS,SHD
Filter time for
overvoltage/undervoltage
shutdown
(6)
10
0.6-V to 2-V threshold setting
(6)
5
7
µs
8.5
2
40
V
V
°C
29-V threshold setting
27.5
29
30.5
V
29-V threshold setting
26.5
28
29.5
V
33-V threshold setting
32
33.5
35
V
33-V threshold setting
31
32.5
34
V
38-V threshold setting
36.5
38
39.5
V
38-V threshold setting
35.5
37
38.5
V
VS is falling from higher voltage than 4.75 V
4.5
4.75
V
Minimum VS for device startup
4.6
4.85
V
5
6
µs
Shutdown signifies predriver shutdown, not VCC3/VCC5 regulator shutdown.
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6.6 Serial Peripheral Interface Timing Requirements
POS
13
MIN
13.1
ƒSPI
SPI clock (SCLK) frequency
13.2
tSPI
SPI clock period (2)
UNIT
(1)
MHz
4
250
ns
90
ns
90
ns
tSPI / 2
ns
(2)
13.3
thigh
High time: SCLK logic high duration
13.4
tlow
Low time: SCLK logic low duration (2)
13.5
tsucs
Setup time NCS: time between falling edge of NCS and rising edge of SCLK (2)
(3)
13.6
td1
Delay time: time delay from falling edge of NCS to data valid at SDO
13.7
tsusi
Setup time at SDI: setup time of SDI before the rising edge of SCLK (2)
13.8
td2
Delay time: time delay from falling edge of SCLK to data valid at SDO (3)
60
ns
30
0
(2)
13.9
thcs
Hold time: time between the falling edge of SCLK and rising edge of NCS
13.10
thlcs
SPI transfer inactive time (time between two transfers) (2)
13.11
ttri
Tri-state delay time: time between rising edge of NCS and SDO in tri-state (2)
(1)
(2)
(3)
NOM MAX
ns
60
ns
45
ns
250
ns
30
ns
The maximum SPI clock tolerance is ±10%.
Ensured by characterization.
Ensured by characterization.
NCS
thcs
thlcs
tsucs
SCLK
tsucs
thigh
tlow
SDI
tsusi
tsusi
SDO
td1
td2
ttri
td1
Figure 1. SPI Timing Parameters
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6.7 Typical Characteristics
45
40
35
20
VS = 36 V
VS = 14 V
VS = 4.75 V
19.5
19
IVSn (mA)
30
IVSq_1 (µA)
VS = 36 V
VS = 14 V
VS = 4.75 V
25
20
18.5
18
15
17.5
10
17
5
0
-50
0
50
Temperature (°C)
100
150
0
D001
Figure 2. VS Quiescent Current Shutdown
12
16.5
-50
50
Temperature (°C)
100
150
D002
Figure 3. VS Quiescent Current Shutdown
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7 Detailed Description
7.1 Overview
The DRV3220-Q1 is designed to control 3-phase brushless DC motors in automotive applications using pulsewidth modulation. Three high-side and three low-side gate drivers can be switched individually with low
propagation delay. The input logic prevents simultaneous activation of the high-side and low-side driver of the
same channel. A configuration and status register can be accessed through a SPI communication interface.
7.2 Functional Block Diagram
22 µH
VS
SW
5
BOOST
Battery voltage
1 …F
Controller
GNDLS_B
330 m
ERR
VDDIO
RVSET
EN
NCS
SCLK
SDI
SDO
IHSx, ILSx
Safety and Diagnostic
- Overtemperature
- Overvoltage,
Undervoltage
- Watch dog
- Clock Monitoring
- Overtemperature
VDDIO Detection
ADREF - Short Circuit
- Shoot-through
Protection
- VDS/VGS Monitoring
- Dead Time Control
6x VDS Monitor
+
VSH
±
3 Phase Gate Driver
3 × PowerStage
GHSx(1)
Rgate
SHSx(1)
Level
shift
GLSx(1)
BLDC
Motor
Rgate
SLSx(1)
Control Logic
- Program Gate Current
- Program Gain
- Sleep Mode Control
Power Supply
DRVOFF
Bridge Driver
Reference and Bias
VCC5
Bandgap,
Bias, Oscillator
VCC3
Digital
Safety Relevant
GNDA
0.1 …F
ADREF(3)
1 …F
Copyright © 2017, Texas Instruments Incorporated
(1)
x = 1, 2, 3
(2)
y = 1, 2, 3
(3)
An external reference voltage (VCC5 or VCC3) cannot be used for ADREF voltage.
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7.3 Programming
7.3.1 SPI
The SPI slave interface is used for serial communication with the external SPI master (external MCU). The SPI
communication starts with the NCS falling edge and ends with NCS rising edge. The NCS high level keeps the
SPI slave interface in reset state, and the SDO output in tri-state.
7.3.1.1 Address Mode Transfer
The address mode transfer is an 8-bit protocol. Both SPI slave and SPI master transmit the MSB first.
1
2
3
4
5
6
7
8
SDI
R7
R6
R5
R4
R3
R2
R1
R0
X
SDO
D7
D6
D5
D4
D3
D2
D1
D0
X
NCS
SCLK
NOTE: SPI master (MCU) and SPI slave (DRV3220-Q1) sample received data on the falling SCLK edge and transmit on the
rising SCLK edge.
Figure 4. Single 8-Bit SPI Frame/Transfer
After the NCS falling edge, the first word of 7 bits are address bits followed by the RW bit. During first address
transfer, the device returns the STAT1 register on SDO.
Each complete 8-bit frame will be processed. If NCS goes high before a multiple of 8 bits is transferred, the bits
are ignored.
7.3.1.1.1 SPI Address Transfer Phase
Figure 5. SPI Address Transfer Phase Bits
Bit
Function
D7
ADDR6
D6
ADDR5
D5
ADDR4
D4
ADDR3
D3
ADDR2
D2
ADDR1
D1
ADDR0
D0
RW
ADDR [6:0] Register address
RW
Read and write access
RW = 0: Read access. The SPI master performs a read access to selected register. During
following SPI transfer, the device returns the requested register read value on SDO, and
device interprets SDI bits as a next address transfer.
RW = 1: Write access. The master performs a write access on the selected register. The
slave updates the register value during next SPI transfer (if followed immediately) and
returns the current register value on SDO.
7.3.1.2 SPI Data Transfer Phase
14
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Figure 6. SPI Data Transfer Phase Bits
Bit
Function
D7
DATA7
D6
DATA6
D5
DATA5
D4
DATA4
D3
ADDR3
D2
DATA2
D1
DATA1
D0
DATA0
DATA [7:0] Data value for write access (8-Bit).
The table shows data value encoding scheme during a write access It is possible to mix the
two access modes (write and read access) during one SPI communication sequence (NCS =
0). The SPI communication can be terminated after single 8-bit SPI transfer by asserting
NCS = 1. Device returns STAT1 register (for the very first SPI transfer after power-up) or
current register value that was addressed during SPI Transfer Address Phase.
7.3.1.3 Device Data Response
Figure 7. Device Data Response Bits
Bit
Function
REG [7:0]
D7
REG7
D6
REG6
D5
REG5
D4
REG4
D3
REG3
D2
REG2
D1
REG1
D0
REG0
Internal register value. All unused bits are set to 0.
Figure 8 shows a complete 16-bit SPI frame. Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, and Figure 14
show the frame examples.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0
X
SDO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
X
NCS
SCLK
8-bit SPI Transfer
8-bit SPI Transfer
16-bit SPI Frame
SPI Master (MCU) and SPI slave (DRV3220-Q1) sample received data on the rising SCLK edge, and transmit data
on the falling SCLK edge
Figure 8. 16-Bit SPI Frame
NCS
SDI
ADDR1, RW = 1 (WR)
1st Transfer
WR DATA1
2nd Transfer
ADDR2, RW = 0 (RD)
3rd Transfer
Zero Vector
SDO
Status Flags
Response to Transfer 1
Status Flags
Response to Transfer 3
Figure 9. Write Access Followed by Read Access
NCS
SDI
ADDR1, RW = 0 (RD)
1st Transfer
³=HUR 9HFWRU´
ADDR2, RW = 0 (RD)
3rd Transfer
Zero Vector
SDO
Status Flags
Response to Transfer 1
Status Flags
Response to Transfer 3
Figure 10. Read Access Followed by Read Access
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NCS
SDI
ADDR1, RW = 1 (WR)
1st Transfer
WR DATA1
2nd Transfer
ADDR2, RW = 1 (WR)
3rd Transfer
WR DATA2
4th Transfer
SDO
Status Flags
Response to Transfer 1
Status Flags
Response to Transfer 3
Figure 11. Write Access Followed by Write Access
NCS
SDI
ADDR1, RW = 0 (RD)
1st Transfer
ADDR2, RW = 1 (WR)
2nd Transfer
WR DATA2
3rd Transfer
Zero Vector
SDO
Status Flags
Response to Transfer 1
Response to Transfer 2
Status Flags
Figure 12. Read Access Followed by Write Access
NCS
SDI
ADDR1, RW = 0 (RD)
1st Transfer
ADDR2, RW = 0 (RD)
2nd Transfer
ADDR3, RW = 1 (WR)
3rd Transfer
WR DATA3
4th Transfer
SDO
Status Flags
Response to Transfer 1
Response to Transfer 2
Response to Transfer 3
Figure 13. Read Access Followed by Read Access Followed by Write Access
NCS
SDI
ADDR1, RW = 0 (RD)
1st Transfer
ADDR2, RW = 0 (RD)
2nd Transfer
ADDR3, RW = 0 (RD)
3rd Transfer
Zero Vector
SDO
Status Flags
Response to Transfer 1
Response to Transfer 2
Response to Transfer 3
Figure 14. Read Access Followed by Read Access Followed by Read Access
16
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7.4 Register Maps
Table 1. Register Address Map and Summary Table
Address Name
Reset Value
CRC
Check
Access State (1)
Reset Event (2)
(bit wide exception)
Section
0×01
Configuration register 0 (CFG0)
8'h3F
Yes
W/R : D,
A([6:3])
R : A(7,[2:0], SF
RST1-4
Go
0×02
Configuration register 1 (CFG1)
8'h3F
Yes
W/R: D
R: A, SF
RST1-4
Go
0×04
HS 1/2/3 drive register (CURR0) ON
8'h00
Yes
W/R: D
R: A, SF
RST1-4
Go
0×05
LS 1/2/3 drive register (CURR1) ON
8'h00
Yes
W/R: D
R: A, SF
RST1-4
Go
0×06
HS 1/2/3 drive register (CURR2) OFF
8'h00
Yes
W/R: D
R: A, SF
RST1-4
Go
0×07
LS 1/2/3 drive register (CURR3) OFF
8'h00
Yes
W/R: D
R: A, SF
RST1-4
Go
0×08
Safety/error configuration register
(SECR1)
8'hC0
Yes
W/R: D
R: A, SF
RST1
Go
0×09
Safety function configuration register
(SFCR1)
8'h80
Yes
W/R: D
R: A, SF
RST1-3
Go
0×0A
Status register 0 (STAT0)
8'h00
No
R: D, A, SF
RST1-4
Go
0×0B
Status register 1 (STAT1)
8'h80
No
R: D, A, SF
RST1-3
Go
0×0C
Status register 2 (STAT2)
8'h00
No
R: D, A, SF
RST1-3
Go
0×0D
Status register 3 (STAT3)
8'h03
No
R: D, A, SF
RST1-3
Go
0×0E
Status register 4 (STAT4)
8'h00
No
R: D, A, SF
RST1-3
Go
Go
0×0F
Status register 5 (STAT5)
8'h03
No
R: D, A, SF
RST1-3
(Bit[4]:RST1)
0×10
Status register 6 (STAT6)
8'h00
No
R: D, A, SF
RST1-3
Go
0×11
Status register 7 (STAT7)
8'h00
No
R: D, A, SF
RST1-4
Go
Go
0×12
Status register 8 (STAT8)
8'h00
No
R: D, A, SF
RST1-4
(Bit[0]:RST1)
0×13
Safety error status
(SAFETY_ERR_STAT)
8'h00
No
R: D, A, SF
RST1-3
(Bit[3:1]:RST1)
Go
0×14
Status register 9 (STAT9)
8'h00
No
R: D, A, SF
RST1-3
Go
0×15
Reserved 1
8'h00
No
W/R: D, A, SF
RST1-3
0×16
Reserved 2
8'h00
No
W/R: D, A, SF
RST1-3
0×1E
SPI transfer write CRC register
(SPIWR_CRC)
8'h00
No
W/R: D, A, SF
RST1-3
Go
0×1F
SPI transfer read CRC register
(SPIRD_CRC)
8'hFF
No
R: D, A, SF
RST1-3
Go
0×20
SAFETY_CHECK_CTRL register (
SFCC1)
8'h01
No
W/R: D
R: A, SF
RST1-3
Go
0×21
CRC control register (CRCCTL)
8'h00
No
W/R: D, A
R: SF
RST1-3
Go
0×22
CRC calculated check sum register
(CRCCALC)
N/A
No
W/R: D
R: A, SF
RST1-3
Go
0×23
Reserved 3
8'h00
No
W/R: D, A, SF
RST1-3
0×24
HS/LS read back (RB0)
8'h00
No
R: D, A, SF
RST1-3
Go
RST1-4
Go
0×25
HS/LS count control (RB1)
8'h00
No
W/R: D, A
R: SF
0×26
HS/LS count (RB2)
8'h00
No
R: D, A, SF
RST1-4
Go
Yes
W/R: D
R: A, SF
RST1-4
Go
0×27
(1)
(2)
Configuration register 3 (CFG3)
8'hAB
W/R: Write and Read access possible, W: Write access possible, R: Read access possible
D: DIAGNOSITC STATE, A: ACTIVE STATE, SF: SAFE STATE, SY: STANDBY STATE, R: RESET
RST1: Power up, RST2: System clock error detected by clock monitor RST3: VCC3 UV/OV or from other state to RESET, RST4: LBIST
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Register Maps (continued)
Table 1. Register Address Map and Summary Table (continued)
Address Name
18
Reset Value
CRC
Check
Access State (1)
Reset Event (2)
(bit wide exception)
Section
0×28
Configuration register 4 (CFG4)
8'h00
Yes
W/R: D
R: A, SF
RST1-4
Go
0×29
Configuration register 5 (CFG5)
8'hAB
Yes
W/R: D
R: A, SF
RST1-3
Go
0×2A
CSM unlock (CSM_UNLOCK1)
8'h00
No
W/R: D
R: A, SF
RST1-4
Go
0×2B
CSM unlock (CSM_UNLOCK2)
8'h3F
No
W/R: D
R: A, SF
RST1-4
Go
0×2C
Reserved 4
8'h00
Yes
W/R: D
R: A, SF
RST1-4
0×2D
Safety BIST control register 1
(SAFETY_BIST_CTL1)
8'h00
Yes
W/R: D
R: SF, A
RST1-3
Go
0×2E
SPI test register (SPI_TEST)
8'h00
No
W/R: D, A, SF
RST1-4
Go
0×2F
Reserved 5
8'h00
No
W/R: D, A, SF
RST1-3
0×30
Safety BIST control register 2
(SAFETY_BIST_CTL2)
8'h00
Yes
W/R: D
R: SF, A
RST1-3
(Bit[5]:RST1)
Go
0×31
Watch dog timer configuration register
(WDT_WIN1_CFG)
8'h02
Yes
W/R: D
R: SF, A
RST1-4
Go
0×32
Watch dog timer configuration register
(WDT_WIN2_CFG)
8'h08
Yes
W/R: D
R: SF, A
RST1-4
Go
0×33
Watch dog timer TOKEN register
(WDT_TOKEN_FDBCK)
8'h04
Yes
W/R: D
R: SF, A
RST1
Go
0×34
Watch dog timer TOKEN register
(WDT_TOKEN_VALUE)
8'h40
No
R: D, SF, A
RST1-4
Go
0×35
Watch dog timer ANSWER register
(WDT_ANSWER)
8'h00
No
W/R: D, A, SF
RST1-4
Go
0×36
Watch dog timer status register
(WDT_STATUS)
8'hC0
No
R: D, A, SG
RST1-4
Go
0×37
Watch dog failure detection configuration
register (WD_FAIL_CFG)
8'hEC
Yes
W/R: D
R: SF, A
RST1-4
Go
0×38
Configuration register 6 (CFG6)
8'h10
Yes
W/R: D
R: A, SF
RST1-4
Go
0×39
Configuration register 7 (CFG7)
8'h13
Yes
W/R : D
R : A, SF
RST1-4
Go
0×3A
Configuration register 8 (CFG8)
8'h20
Yes
W/R : D
R : A, SF
RST1-4
Go
0×3B
Reserved 6
0
—
—
—
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV3220-Q1 is a predriver for automotive applications featuring three-phase brushless DC-motor control.
Because this device has a boost regulator for charging high-side gates, it can handle gate charges of 250 nC. A
boost converter allows full control on the power-stages even for a low battery voltage down to 4.75 V.
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8.2 Typical Application
Rgate
Q3LS
From MCU
ADC or Vref
NU 31
GHS3
ADREF 33
4
NU 34
SHS3
NU 40
3
NU 42
GLS3
NU 39
1
NU 41
SLS3
IHS3 43
2
VDDIO 25
VSH
ILS3 44
5
ILS2 46
(3)
ILS1 48
10
IHS1 47
3
IHS2 45
From MCU
PGND
VBAT
From
TPS6538x(2)
8.2.1 Three-Phase Motor Drive-Device for Automotive Application
NU 37
NU 38
NU 36
Rgate
Q3HS
NU 35
16 GNDA
2.2 mF
PGND
Rgate
Q2LS
BLDC
Motor
8
SLS2
9
GLS2
6
SHS2
7
GHS2
VCC3 29
DRV3220-Q1(1)
0.1 µF
TEST (GND) 10
Rgate
Q2HS
VCC5 32
30 GNDA
2.2 mF
PGND
12 SLS1
ERR 17
Rgate
Q1LS
1 µF
To MCU
11 GLS1
RVSET 19
PGND
From MCU
23 GNDLS_B
21 SW
20 BOOST
15 VS
28 SDI
27 SDO
26 SCLK
2.2 mF
13 GHS1
22 NCS
Rgate
Q1HS
18 DRVOFF
14 SHS1
EN 24
From TPS6538x-Q1,
connect to ENDRV
330 m
D1(5)
MCU SPI
10 µF
5
(3)
1 …F
0.1 µF
L1(4)
22 µH
0.1 µF
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(1)
This schematic of the DRV3220-Q1 48-pin HTQFP does not provide a true representation of physical pin locations.
(2)
Use same supply from the TPS6538x as the supply used for the MCU IO.
(3)
Resistor not required for reverse protected battery.
(4)
L1 = B82442A1223K000 INDUCTOR, SMT, 22 uH, 10%, 480 mA). The maximum inductor current must be more than
VGNDLS_B / 330 mΩ.
(5)
D1 = SS28 (DIODE, SMT, SCHOTTKY, 80 V, 2 A). A fast recovery diode is recommended.
(6)
QxHS, QxLS = IRFS3004PBF (HEXFET, N-CHANNEL, POWER MOSFET, D2PACK)
(7)
Rgate = Must be adjust based on system requirement such as EMI, Slew rate, and power
Figure 15. Typical Application Diagram
8.3 System Example
Figure 16 shows a typical system example for an electric power-steering system.
20
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FR
Flexray
CAN
CAN
IGN
WakeUp
CAN
Supply
Preregulator
µC IO
Supply
Charge
Pump
µC Core
Supply
CAN
FR
OUT
OUT
VBAT
BOOST
EN
EN
Relay Driver
VBAT
Voltage
Monitoring
KL30
NHET
3 × PowerStage
- Input Capture
- Input Capture
Vds
Mon
Bandgap
Ref 2
VSH
GHSx
SHSx
Protected
Sensor
Supply
- PWM
Voltage
Monitoring
Bridge
Driver
3 × IHSx
3 × ILSx
SPR
Switch
SLSx
WD
Reset /
Enable
nRESET
µC ERROR
Monitor
nERROR
Motor
GLSx
Sensors
OFF
x = [1..3]
ADC1
ADC2
Q&A
Watchdog
SPI
Ta/Tj Over
Temp
shutdown
Diagnose
and Config
TPS6538x-Q1
SPI
INT
TMS570
SPI
Diagnose
and Config
Bridge Error
Monitoring
Tj Over
Temp
shutdown
Error Monitoring:
- VDS Monitoring
- Shoot-through
- Voltage Monitoring on
VBAT, VBOOST, and
internal supplies.
- Temperature Warning
- And so forth
DRV3220-Q1
Analog Sensor Signal
Digital Sensor Signal
Power Supply
Networks
Bridge Driver
Safety Diagnostics
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Figure 16. Typical System – Electrical Power Steering Example
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range of 4.75 V to 40 V. The protection circuit
must be placed for protection against reverse supply connection.
10 Layout
10.1 Layout Guidelines
Use the following guidelines when designing a PCB for the DRV3220-Q1:
• In addition to the GND pins, the DRV3220-Q1 makes an electrical connection to GND through the
PowerPAD. Always check that the PowerPAD has been properly soldered (see PowerPAD™ Thermally
Enhanced Package [SLMA002]).
• The VS bypass capacitors should be placed close to the power supply terminals. See the VS box in Figure 17
• Place the VCC5 and VCC5 bypass capacitors close to the corresponding pins with a low impedance path to
the ground plane pin (pin 16). See the VCC3 VCC5 bypass box in Figure 17.
• AGND should all be tied to the ground plane through a low impedance trace or copper fill.
• Add stitching vias to reduce the impedance of the GND path from the top to bottom side.
• Try to clear the space around and below the DRV3220-Q1 to allow for better heat spreading from the
PowerPAD.
• Keep the BOOST components close to the device and current loops small. See the BOOST boxes in
Figure 17.
• Place the GNDLS_B resistor close to the device pin. See the GNDLS_B box in Figure 17.
10.2 Layout Example
BOOST
Bypass
SENSE
GNDLS_B
BOOST
L
BOOST
D
VS
SENSE
VCC3
VCC5
Bypass
SENSE
Figure 17. Layout Schematic
22
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• DRV3220-Q1 Applications in 24-V Automotive Systems
• DRV3220-Q1 Negative Voltage Stress on Source Pins
• Electric Power Steering Design Guide with DRV3220-Q1
• PowerPAD™ Thermally Enhanced Package
• Protecting Automotive Motor Drive Systems from Reverse Polarity Conditions
• Q&A Watchdog Timer Configuration for DRV3220-Q1
• TPS653850-Q1 Multirail Power Supply for Microcontrollers in Safety-Relevant Applications
• TPS653853-Q1 Multirail Power Supply for Microcontrollers in Safety-Relevant Applications
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DRV3220QPHPRQ1
ACTIVE
HTQFP
PHP
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV3220Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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