DRV421RTJT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 DRV421 Integrated Magnetic Fluxgate Sensor for Closed-Loop Current Sensing 1 Features 3 Description • The DRV421 is designed for magnetic closed-loop current sensing solutions, enabling isolated, precise dc- and ac-current measurements. This device provides both, a proprietary integrated fluxgate sensor, and the required analog signal conditioning, thus minimizing component count and cost. The low offset and drift of the fluxgate sensor, along with an optimized front-end circuit results in unrivaled measurement precision. 1 • • • • • • • High-Precision Integrated Fluxgate Sensor – Offset and Drift: ±8 µT max, ±5 nT/°C typ Extended Current Measurement Range – H-Bridge Output Drive: ±250 mA typ at 5 V Precision Shunt Sense Amplifier – Offset and Drift (max): ±75 µV, ±2 µV/°C – Gain Error and Drift (max): ±0.3%, ±5 ppm/°C Precision Reference – Accuracy and Drift (max): ±2%, ±50 ppm/°C – Pin-Selectable Voltage: 2.5 V or 1.65 V – Selectable Ratiometric Mode: VDD / 2 Magnetic Core Degaussing Feature Diagnostic Features: Overrange and Error Flags Supply Voltage Range: 3.0 V to 5.5 V Fully Specified Over the Extended Industrial Temperature Range of –40°C to +125°C The DRV421 provides all the necessary circuit blocks to drive the current-sensing feedback loop. The sensor front-end circuit is followed by a filter that can be configured to work with a wide range of magnetic cores. The integrated 250-mA H-Bridge drives the compensation coil and doubles the current measurement range, as compared to conventional single-ended drive methods. The device also provides a precision voltage reference and shunt sense amplifier to generate and drive the analog output signal. Device Information(1) 2 Applications • • • • • PART NUMBER Closed-Loop DC- and AC-Current Sensor Modules Leakage Current Sensors Industrial Monitoring and Control Systems Overcurrent Detection Frequency, Voltage, and Solar Inverters DRV421 PACKAGE WQFN (20) BODY SIZE (NOM) 4.00 mm × 4.00 mm (1) For all available packages, see the package option addendum at the end of the datasheet. Typical Application optional 3.3 V or 5 V magnetic core RSHUNT DRV421 Fluxgate Sensor Front-End DRV421 H-Bridge Driver Fluxgate Sensor Shunt Sense Amplifier Integrator and Filter compensation coil return current conductor (optional) ADC primary current conductor Device Control and Degaussing Reference 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 16 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 16 16 17 26 8 Application and Implementation ........................ 27 8.1 Application Information............................................ 27 8.2 Typical Application ................................................. 29 9 Power-Supply Recommendations...................... 34 9.1 Power-Supply Decoupling....................................... 34 9.2 Power-On Start Up and Brownout .......................... 34 9.3 Power Dissipation ................................................... 34 10 Layout................................................................... 35 10.1 Layout Guidelines ................................................. 35 10.2 Layout Example .................................................... 36 11 Device and Documentation Support ................. 37 11.1 11.2 11.3 11.4 11.5 Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 37 37 37 37 37 12 Mechanical, Packaging, and Orderable Information ........................................................... 37 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2015) to Revision B Page • Added TI Design .................................................................................................................................................................... 1 • Added last two Applications bullets ....................................................................................................................................... 1 • Changed QFN to WQFN in pin configuration drawing .......................................................................................................... 3 • Changed QFN to WQFN in Thermal Information table ......................................................................................................... 4 • Changed QFN to WQFN in Power Dissipation section ....................................................................................................... 34 Changes from Original (May 2015) to Revision A • 2 Page Released to production........................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 DRV421 www.ti.com SBOS704B – MAY 2015 – REVISED MARCH 2016 5 Pin Configuration and Functions GSEL1 ER DEMAG GND GND 20 19 18 17 16 RTJ Package 20-Pin WQFN Top View GSEL0 1 15 OR RSEL1 2 14 AINN RSEL0 3 13 AINP REFOUT 4 12 ICOMP1 REFIN 5 11 ICOMP2 6 7 8 9 10 VOUT GND VDD VDD GND (Thermal Pad) Pin Functions PIN NAME NO. I/O DESCRIPTION AINN 14 I Inverting input of shunt sense amplifier AINP 13 I Noninverting input of shunt sense amplifier DEMAG 18 I Degauss control input ER 19 O Error flag; open-drain, active low output Ground reference GND 7, 10, 16, 17 — GSEL0 1 I Gain and bandwidth selection input 0 GSEL1 20 I Gain and bandwidth selection input 1 ICOMP1 12 O Output 1 of compensation coil driver ICOMP2 11 O Output 2 of compensation coil driver OR 15 O Shunt sense amplifier overrange indicator; open-drain, active-low output REFIN 5 I Common-mode reference input for the shunt sense amplifier REFOUT 4 O Voltage reference output RSEL0 3 I Voltage reference mode selection input 0 RSEL1 2 I Voltage reference mode selection input 1 8, 9 — Supply voltage, 3.0 V to 5.5 V. Decouple both pins using 1-µF ceramic capacitors placed as close as possible to the device. See the Power-Supply Decoupling and Layout sections for further details. 6 O Shunt sense amplifier output — Connect thermal pad to GND VDD VOUT PowerPAD™ Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 3 DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX –0.3 7 GND – 0.5 VDD + 0.5 GND – 6.0 VDD + 6.0 –300 300 Supply voltage (VDD to GND) Voltage Input voltage, except pins AINP and AINN (2) Shunt sense amplifier inputs (pins AINP and AINN) (3) Pins ICOMP1 and ICOMP2 (short circuit current ISC) Current (1) (2) (3) (4) pins AINP and AINN –5 5 All remaining pins –25 25 Junction, TJ max –50 150 Storage, Tstg –65 150 Shunt sense amplifier inputs Temperature (4) UNIT V mA °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited, except for the shunt sense amplifier input pins. These inputs are not diode-clamped to the power supply rails. Power-limited; observe maximum junction temperature. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Electrostatic discharge (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VDD Supply voltage 3.0 5.0 5.5 UNIT V TA Specified ambient temperature range –40 125 °C 6.4 Thermal Information SBOS704 THERMAL METRIC (1) RTJ (WQFN) UNITS 20 PINS RθJA Junction-to-ambient thermal resistance 34.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 33.1 °C/W RθJB Junction-to-board thermal resistance 11.0 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 11.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 DRV421 www.ti.com SBOS704B – MAY 2015 – REVISED MARCH 2016 6.5 Electrical Characteristics All minimum and maximum specifications at TA = +25°C, VDD = 3.0 V to 5.5 V, and ICOMP1 = ICOMP2 = 0 mA (unless otherwise noted). Typical values are at VDD = 5.0 V. PARAMETER TEST CONDITIONS MIN TYP MAX –8 ±2 8 UNIT FLUXGATE SENSOR FRONT-END Offset AOL (1) No magnetic field No magnetic field Noise f = 0.1 Hz to 10 Hz 17 nTrms Noise density f = 1 kHz 1.5 nT/√Hz VICOMP ±5 nT/°C Saturation trip level for pin ER 1.7 mT DC open-loop gain 16 V/µT AC open-loop gain IICOMP µT Offset drift Peak current at pins ICOMP1 and ICOMP2 Voltage swing at pins ICOMP1 and ICOMP2 GSEL[1:0] = 00, at 3.8 kHz, integration-to-flatband corner frequency 8.5 GSEL[1:0] = 01, at 3.8 kHz, integration-to-flatband corner frequency 38 GSEL[1:0] = 10, at 1.9 kHz, integration-to-flatband corner frequency 25 GSEL[1:0] = 11, at 1.9 kHz, integration-to-flatband corner frequency 70 V/mT VICOMP1 – VICOMP2 = 4.2 VPP,VDD = 5 V, TA = –40°C to +125°C 210 250 VICOMP1 – VICOMP2 = 2.5 VPP, VDD = 3.3 V, TA = –40°C to +125°C 125 150 20-Ω load, VDD = 5 V, TA = –40°C to +125°C 4.2 20-Ω load, VDD = 3.3 V, TA = –40°C to +125°C 2.5 mA Common-mode output voltage at pins ICOMP1 and ICOMP2 VPP VREFOUT V SHUNT SENSE AMPLIFIER VOO Output offset voltage VAINP = VAINN = VREFIN, VDD = 3.0 V Output offset voltage drift CMRR Common-mode rejection ratio, RTO PSRRAMP Power-supply rejection ratio, RTO VIC Common-mode input voltage range ZIND Differential input impedance ZIC Common-mode input impedance G Gain, VOUT / (VAINP – VAINN) EG Gain error (2) VCM = −1 V to VDD + 1 V, VREFIN = VDD / 2 VDD = 3.0 V to 5.5 V, VCM = VREFIN ±0.01 0.075 –2 ±0.4 2 µV/°C –250 ±50 250 µV/V –50 ±4 50 µV/V –1 V kΩ 16.5 20 23.5 40 50 60 ±0.02% 0.3% –5 ±1 5 RL = 1 kΩ 12 Voltage output swing from negative rail (OR pin trip level) VDD = 5.5 V, IVOUT = 2.5 mA 48 85 VDD = 3.0 V, IVOUT = 2.5 mA 56 100 Voltage output swing from positive rail (OR pin trip level) VDD = 5.5 V, IVOUT = –2.5 mA VDD – 85 VDD – 48 VDD = 3.0 V, IVOUT = –2.5 mA VDD – 100 VDD – 56 BW–3dB Bandwidth SR Slew rate kΩ V/V –0.3% VOUT connected to GND –18 VOUT connected to VDD 20 Signal overrange indication delay (OR pin) VIN = 1-V step Settling time, large-signal ΔV = ± 2 V to 1% accuracy, no external filter Settling time, small-signal ΔV = ± 0.4 V to 0.01% accuracy en Output voltage noise density, RTO f = 1 kHz, compensation loop disabled VREFIN Input voltage range at pin REFIN TA = –40°C to +125°C (1) (2) VDD + 1 Linearity error Short-circuit current mV 4 Gain error drift ISC –0.075 ppm/°C ppm mV mV mA 2.5 to 3.5 µs 2 MHz 6.5 V/µs 0.9 µs 8 µs 170 GND nV/√Hz VDD V Fluxgate sensor front-end offset can be reduced using the feature. Parameter value referred to output (RTO). Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 5 DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 www.ti.com Electrical Characteristics (continued) All minimum and maximum specifications at TA = +25°C, VDD = 3.0 V to 5.5 V, and ICOMP1 = ICOMP2 = 0 mA (unless otherwise noted). Typical values are at VDD = 5.0 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE REFERENCE VREFOUT Reference output voltage at pin REFOUT RSEL[1:0] = 00, no load 2.45 2.5 2.55 RSEL[1:0] = 01, no load 1.6 1.65 1.7 RSEL[1:0] = 1x, no load PSRRREF 45 50 55 % of VDD Reference output voltage drift RSEL[1:0] = 00, 01 –50 ±10 50 ppm/°C Voltage divider gain error drift RSEL[1:0] = 1x –50 ±10 50 ppm/°C Power-supply rejection ratio RSEL[1:0] = 00, 01 –300 ±15 300 µV/V RSEL[1:0] = 0x, load to GND or VDD, ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C 0.15 0.35 RSEL[1:0] = 1x, load to GND or VDD, ΔILOAD = 0 mA to 5 mA, TA = –40°C to +125°C 0.3 0.8 Load regulation ISC V Short-circuit current mV/mA REFOUT connected to VDD 20 REFOUT connected to GND –18 mA DIGITAL INPUTS/OUTPUTS Logic Inputs (CMOS) VIH High-level input voltage TA = –40°C to +125°C 0.7 × VDD VDD + 0.3 VIL Low-level input voltage TA = –40°C to +125°C –0.3 0.3 × VDD Input leakage current 0.01 V V µA Logic Outputs (Open-Drain) VOH High-level output voltage VOL Low-level output voltage Set by external pull-up resistor V 4-mA sink 0.3 V IICOMP1 = IICOMP2 = 0 mA, 3.0 V ≤ VDD ≤ 3.6 V, TA = –40°C to +125°C 6.5 9 IICOMP1 = IICOMP2 = 0 mA, 4.5 V ≤ VDD ≤ 5.5 V, TA = –40°C to +125°C 8.1 11 POWER SUPPLY IQ VRST 6 Quiescent current Power-on reset threshold mA 2.4 Submit Documentation Feedback V Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 DRV421 www.ti.com SBOS704B – MAY 2015 – REVISED MARCH 2016 6.6 Typical Characteristics 50 40 40 D001 Offset (PT) 8 7 6 5 4 3 2 1 0 -1 Figure 2. Fluxgate Sensor Front-End Offset Histogram 4 3 3 2 2 1 1 Offset (PT) Offset (PT) Figure 1. Fluxgate Sensor Front-End Offset Histogram 0 -1 -1 -2 -3 -3 -4 5 -4 -40 5.5 Device 1 Device 2 Device 3 0 -2 4 4.5 Supply Voltage (V) -2 VDD = 3.3 V 4 3.5 D002 Offset (PT) VDD = 5 V 3 -3 -8 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 0 -5 0 -6 10 -7 10 -4 20 -5 20 30 -6 30 -7 Devices (%) 50 -8 Devices (%) at VDD = 5 V and TA = +25°C (unless otherwise noted) -25 -10 D003 Figure 3. Fluxgate Sensor Front-End Offset vs Supply Voltage 5 20 35 50 65 Temperature (°C) 80 95 110 125 D004 Figure 4. Fluxgate Sensor Front-End Offset vs Temperature 100 50 Noise Density (nT/—Hz) Devices (%) 40 30 20 10 1 10 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 0 Offset Drift (nT/qC) 0.1 0.0001 D005 Figure 5. Fluxgate Sensor Front-End Offset Drift Histogram 0.001 0.01 0.1 1 Noise Frequency (kHz) 10 100 D006 Figure 6. Fluxgate Sensor Front-End Noise Density vs Noise Frequency Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 7 DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 www.ti.com Typical Characteristics (continued) 60 50 50 40 40 D007 40 35 30 25 20 15 10 -5 -10 2.1 2 1.9 0 1.8 0 1.7 10 1.6 10 1.5 20 1.4 20 Saturation Trip Level (mT) D008 DC Open-Loop Gain (V/PT) Figure 7. Fluxgate Sensor Saturation (ER Pin) Trip Level Histogram Figure 8. Fluxgate Sensor Front-End DC Open-Loop Gain Histogram 50 160 40 30 20 10 0 -40 GSEL[1:0]=00 GSEL[1:0]=01 GSEL[1:0]=10 GSEL[1:0]=11 140 AC Open-Loop Gain (dB) DC Open-Loop Gain (V/PT) 30 5 30 0 Devices (%) 60 1.3 Devices (%) at VDD = 5 V and TA = +25°C (unless otherwise noted) 120 100 80 60 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 40 0.001 110 125 0.01 D009 Figure 9. Fluxgate Sensor Front-End DC Open-Loop Gain vs Temperature 0.1 1 Frequency (kHz) 10 100 D010 Figure 10. Fluxgate Sensor Front-End AC Open-Loop Gain vs Frequency 5 0 VDD = 5 V VDD = 3.3 V -1 Voltage Swing (VPP) Voltage Swing (VPP) 4 3 2 1 -2 -3 -4 VDD = 5 V VDD = 3.3 V 0 -250 -225 -200 -175 -150 -125 -100 -75 Negative Peak Current (mA) -5 -50 -25 0 25 D011 Figure 11. Voltage Swing at ICOMPx Pins vs Negative Peak Current 8 0 50 75 100 125 150 175 Positive Peak Current (mA) 200 225 250 D012 Figure 12. Voltage Swing at ICOMPx Pins vs Positive Peak Current Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 DRV421 www.ti.com SBOS704B – MAY 2015 – REVISED MARCH 2016 Typical Characteristics (continued) at VDD = 5 V and TA = +25°C (unless otherwise noted) 0 5 VDD = 5 V VDD = 3.3 V 4 Voltage Swing (VPP) Voltage Swing (VPP) -1 -2 -3 -4 3 2 1 VDD = 5 V VDD = 3.3 V 20 35 50 65 Temperature (°C) 80 95 0 -40 110 125 -25 -10 5 D013 20 35 50 65 Temperature (°C) RLOAD = 20 Ω 60 60 50 50 D015 50 40 -50 50 40 30 20 0 10 0 0 10 -10 10 -20 20 -30 20 30 30 -20 30 -40 D014 40 -30 40 -40 Devices (%) 70 -50 Devices (%) 110 125 Figure 14. Positive Voltage Swing at ICOMPx Pins vs Temperature 70 Output Offset (PV) D015 D016 Output Offset (PV) VDD = 5 V VDD = 3.3 V Figure 15. Shunt Sense Amplifier Offset Histogram Figure 16. Shunt Sense Amplifier Offset Histogram 75 75 Device 1 Device 2 Device 3 50 Output Offset (PV) 50 Output Offset (PV) 95 RLOAD = 20 Ω Figure 13. Negative Voltage Swing at ICOMPx Pins vs Temperature 25 0 -25 25 0 -25 -50 -50 -75 -40 80 20 5 10 -10 0 -25 -10 -5 -40 -75 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 3 D017 Figure 17. Shunt Sense Amplifier Offset vs Temperature 3.5 4 4.5 Supply Voltage (V) 5 5.5 D018 Figure 18. Shunt Sense Amplifier Offset vs Supply Voltage Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 9 DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 www.ti.com Typical Characteristics (continued) at VDD = 5 V and TA = +25°C (unless otherwise noted) 100 Common-Mode Rejection Ratio (dB) 50 Devices (%) 40 30 20 10 -250 -225 -200 -175 -150 -125 -100 -75 -50 -25 0 25 50 75 100 125 150 175 200 225 250 0 Common-Mode Rejection Ratio (PV/V) 60 40 20 0 0.01 0.1 D019 1 10 100 Input Signal Frequency (kHz) 1000 D020 Figure 20. Shunt Sense Amplifier Common-Mode Rejection Ratio vs Input Signal Frequency Figure 19. Shunt Sense Amplifier Common-Mode Rejection Ratio Histogram 70 Power-Supply Rejection Ratio (dB) 100 60 50 Devices (%) 80 40 30 20 10 60 40 20 0 0.01 50 40 30 20 10 0 -10 -20 -30 -40 -50 0 80 0.1 1 10 Ripple Frequency (kHz) D021 Power-Supply Rejection Ratio (PV/V) 100 1000 D022 Figure 22. Shunt Sense Amplifier Power-Supply Rejection Ratio vs Ripple Frequency Figure 21. Shunt Sense Amplifier Power-Supply Rejection Ratio Histogram 100 51 50.8 AINP Input Impedance (k:) Devices (%) 80 60 40 20 50.6 50.4 50.2 50 49.8 49.6 49.4 49.2 AINP Input Impedance (k:) 49 -40 60 58 56 54 52 50 48 46 44 42 40 0 Figure 23. Shunt Sense Amplifier AINP Input Impedance Histogram 10 -25 D023 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 D024 Figure 24. Shunt Sense Amplifier AINP Input Impedance vs Temperature Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 DRV421 www.ti.com SBOS704B – MAY 2015 – REVISED MARCH 2016 Typical Characteristics (continued) at VDD = 5 V and TA = +25°C (unless otherwise noted) 50 11 10.8 10.6 AINN Input Impedance (k:) Devices (%) 40 30 20 10 10.4 10.2 10 9.8 9.6 9.4 9.2 9 -40 12 11.5 11.75 11 11.25 10.5 10.75 10 10.25 9.5 9.75 9 9.25 8.5 8.75 8 8.25 0 -25 -10 5 D025 20 35 50 65 Temperature (°C) 80 95 110 125 D026 AINN Input Impedance (k:) Figure 26. Shunt Sense Amplifier AINN Input Impedance vs Temperature Figure 25. Shunt Sense Amplifier AINN Input Impedance Histogram 100 0.3 0.25 0.2 80 0.1 Gain Error (%) Devices (%) 0.15 60 40 0.05 0 -0.05 -0.1 -0.15 20 -0.2 -0.25 -0.3 -40 0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 0 -25 -10 D027 5 20 35 50 65 Temperature (°C) 80 95 110 125 D028 Gain Error (%) Figure 27. Shunt Sense Amplifier Gain Error Histogram Figure 28. Shunt Sense Amplifier Gain Error vs Temperature 20 40 35 Linearity Error (ppm) Gain (dB) 15 10 5 30 25 20 15 10 5 0 0.01 0 0.1 1 10 100 Input Signal Frequency (kHz) 1000 10000 3 3.5 D029 Figure 29. Shunt Sense Amplifier Gain vs Frequency 4 4.5 Supply Voltage (V) 5 5.5 D030 Figure 30. Shunt Sense Amplifier Linearity vs Supply Voltage Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 11 DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 www.ti.com Typical Characteristics (continued) at VDD = 5 V and TA = +25°C (unless otherwise noted) 0.5 VDD = 5.5 V VDD = 3.0 V Voltage Difference to VDD or GND (V) Voltage Difference to VDD or GND (V) 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 Output Current (mA) 8 9 VDD = 5.5 V VDD = 3.0 V 0.4 0.3 0.2 0.1 0 -40 10 -25 Figure 31. OR Pin Trip Level vs Output Current 3.75 30 Short-Circuit Current (mA) 4 Trip Delay (Ps) 3.5 3.25 3 2.75 2.5 20 35 50 65 Temperature (°C) 80 95 110 125 D032 VOUT to GND VOUT to VDD 20 10 0 -10 -20 -30 2.25 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 -40 -40 110 125 -25 -10 5 D033 Figure 33. OR Pin Trip Delay vs Temperature 20 35 50 65 Temperature (°C) 80 95 110 125 D034 Figure 34. Shunt Sense Amplifier Output Short-Circuit Current vs Temperature 40 0.25 VOUT to GND VOUT to VDD 30 0.2 0.15 20 0.1 10 Voltage (V) Short-Circuit Current (mA) 5 Figure 32. OR Pin Trip Level vs Temperature 40 2 -40 -10 D031 0 -10 0.05 0 -0.05 -0.1 -20 -0.15 -30 VOUT VIN -0.2 -40 3 3.5 4 4.5 Supply Voltage (V) 5 5.5 -0.25 -2.5 D035 0 2.5 5 7.5 10 Time (Ps) 12.5 15 17.5 D048 Rising Edge Figure 35. Shunt Sense Amplifier Output Short-Circuit Current vs Supply Voltage 12 Figure 36. Shunt Sense Amplifier Small-Signal Settling Time Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 DRV421 www.ti.com SBOS704B – MAY 2015 – REVISED MARCH 2016 Typical Characteristics (continued) at VDD = 5 V and TA = +25°C (unless otherwise noted) 0.25 1.25 VOUT VIN 0.2 1 0.15 0.75 0.5 Voltage (V) Voltage (V) 0.1 0.05 0 -0.05 0.25 0 -0.25 -0.1 -0.5 -0.15 -0.75 -0.2 -1 -0.25 -2.5 0 2.5 5 7.5 10 Time (Ps) 12.5 15 VOUT VIN -1.25 -0.5 17.5 0 0.5 D049 Falling Edge 2 2.5 D050 Figure 38. Shunt Sense Amplifier Large-Signal Settling Time 1.25 5 VOUT VIN 1 0.75 3 0.5 2 0.25 0 -0.25 1 0 -1 -0.5 -2 -0.75 -3 -1 -4 -1.25 -0.5 0 0.5 1 Time (Ps) 1.5 2 VIN VOUT 4 Voltage (V) Voltage (V) 1.5 Rising Edge Figure 37. Shunt Sense Amplifier Small-Signal Settling Time -5 -0.1 2.5 D051 -0.075 -0.05 -0.025 0 0.025 Time (ms) Falling Edge 0.05 0.075 0.1 D036 VDD = 5 V Figure 39. Shunt Sense Amplifier Large-Signal Settling Time Figure 40. Shunt Sense Amplifier Overload Recovery Response 5 10000 Output Voltage Noise Density (nV/—Hz) VIN VOUT 4 3 2 Voltage (V) 1 Time (Ps) 1 0 -1 -2 -3 -4 -5 -0.1 -0.075 -0.05 -0.025 0 0.025 Time (ms) 0.05 0.075 0.1 1000 100 10 10 D037 100 1000 10000 Noise Frequency (Hz) 100000 D038 VDD = 3.3 V Figure 41. Shunt Sense Amplifier Overload Recovery Response Figure 42. Shunt Sense Amplifier Output Voltage Noise Density vs Noise Frequency Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 13 DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 www.ti.com Typical Characteristics (continued) at VDD = 5 V and TA = +25°C (unless otherwise noted) 50 2.55 Device 1 Device 2 Device 3 2.54 2.53 Reference Voltage (V) Devices (%) 40 30 20 2.52 2.51 2.5 2.49 2.48 10 2.47 2.46 2.505 2.504 2.503 2.502 2.501 2.5 2.499 2.498 2.497 2.496 2.495 0 2.45 -40 -25 -10 D039 5 20 35 50 65 Temperature (°C) 80 95 110 125 D040 Reference Voltge (V) Figure 44. Reference Voltage vs Temperature Figure 43. Reference Voltage Histogram 30 3 2.6 Reference Voltage (V) Devices (%) 25 20 15 10 2.4 2.2 2 1.8 5 1.6 0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 1.4 3 3.5 D041 Reference Voltage Drift (ppm/qC) 4 4.5 Supply Voltage (V) 5 5.5 D042 Figure 46. Reference Voltage vs Supply Voltage Figure 45. Reference Voltage Drift Histogram 50 3 RSEL[1:0] = 00 RESL[1:0] = 01 RSEL[1:0] = 1x 2.8 40 2.6 2.4 Devices (%) Reference Voltage (V) RSEL[1:0] = 00 RSEL[1:0] = 01 2.8 2.2 2 30 20 1.8 10 1.6 0 -4 -3 -2 -1 0 1 2 Referene Current (mA) 3 4 5 D043 -300 -270 -240 -210 -180 -150 -120 -90 -60 -30 0 30 60 90 120 150 180 210 240 270 300 1.4 -5 D044 Power-Supply Rejection Ratio (PV/V) Figure 47. Reference Voltage vs Reference Output Current 14 Figure 48. Reference Voltage Power-Supply Rejection Ratio Histogram Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 DRV421 www.ti.com SBOS704B – MAY 2015 – REVISED MARCH 2016 Typical Characteristics (continued) at VDD = 5 V and TA = +25°C (unless otherwise noted) 100 10 VDD = 3 V VDD = 5.5 V 9.5 Quiescent Current (mA) Devices (%) 80 60 40 20 9 8.5 8 7.5 7 6.5 6 5.5 0.3 0.35 0.2 0.25 0.15 0.1 0 0.05 -0.1 -0.05 -0.2 -0.15 -0.25 -0.3 -0.35 0 5 -40 -25 -10 D045 5 20 35 50 65 Temperature (°C) 80 95 110 125 D046 Load Regulation (mV/mA) Figure 49. Reference Voltage Load Regulation Histogram Figure 50. Quiescent Current vs Temperature Reset Threshold (V) 2.55 2.45 2.35 2.25 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 D047 Figure 51. Power-On Reset Threshold vs Temperature Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 15 DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 www.ti.com 7 Detailed Description 7.1 Overview The DRV421 is a fully-integrated, magnetic fluxgate sensor, with the necessary sensor conditioning and compensation circuitry for closed-loop current sensors. The device is inserted into an air gap of an external ferromagnetic toroid core to sense the magnetic field. A compensation coil wrapped around the magnetic core generates a magnetic field opposite to the one generated by the current flow to be measured. At dc and low-frequencies, the magnetic field induced by the current in the primary conductor generates a flux in the magnetic core. The fluxgate sensor detects the flux in the DRV421. The device filters the sensor output to provide loop stability. The filter output connects to the built-in H-bridge driver that drives an opposing current through the external compensation coil. The compensation coil generates an opposite magnetic field that brings the original magnetic flux in the core back to zero. At higher frequencies, the inductive coupling between the primary conductor and compensation coil directly drives a current through the compensation coil. The compensation current is proportional to the primary current (IPRIMARY), with a value that is calculated using Equation 1: IICOMP = IPRIMARY / NWINDING where • NWINDING = the number of windings of the compensation coil (1) This compensation current generates a voltage drop across a small external shunt resistor, RSHUNT. An integrated difference amplifier with a fixed gain of 4 V/V measures this voltage and generates an output voltage that is referenced to REFIN and proportional to the primary current. The Functional Block Diagram section shows the DRV421 used as a closed-loop current sensor, for both single-ended and differential primary currents. 7.2 Functional Block Diagram RSHUNT compensation coil magnetic core VDD GND ICOMP1 DRV421 DRV421 AINN VOUT Fluxgate H-Bridge Sensor Integrator and Filter Driver Device Control and Degaussing 16 AINP Shunt Sense Amplifier Fluxgate Sensor Front-End return current conductor (optional) ICOMP2 primary current conductor OR ER DEMAG GSEL0 GSEL1 Submit Documentation Feedback REFIN 1.65 V or 2.5 V Voltage Reference REFOUT RSEL0 RSEL1 Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 DRV421 www.ti.com SBOS704B – MAY 2015 – REVISED MARCH 2016 7.3 Feature Description 7.3.1 Fluxgate Sensor The fluxgate sensor of the DRV421 is uniquely suited for closed-loop current sensors because of its high sensitivity, low noise, and low offset. The fluxgate principle relies on repeatedly driving the sensor in and out of saturation; therefore, the sensor is free of any significant magnetic hysteresis. The feedback loop accurately drives the magnetic flux inside the core to zero. The DRV421 package is free of any ferromagnetic materials in order to prevent magnetization by external fields and to obtain accurate and hysteresis-free operation. Select nonmagnetizable materials for the printed circuit board (PCB) and passive components in the direct vicinity of the DRV421; see the Layout Guidelines section for more details. Figure 52 shows the orientation of the fluxgate sensor and the direction of magnetic sensitivity inside of the package. This orientation is marked by a straight line on top of the package. D421 TI Date Code Figure 52. Orientation and Magnetic Sensitivity Direction of the Integrated Fluxgate Sensor 7.3.2 Integrator-Filter Function and Compensation Loop Stability The DRV421 and the magnetic core are components of the system feedback loop that compensates the magnetic flux generated by the primary current. Therefore, the loop properties and stability depend on both components. Four key parameters determine the stability and effective loop gain at high frequencies: GSEL[1:0] Filter gain setting pins of the DRV421 GCORE Open-loop, current-to-field transfer of the magnetic core Amount of magnetic field generated by 1 A of uncompensated primary current (unit is T/A). NWINDING Number of compensation coil windings L Compensation coil inductance A minimum inductance of 100 mH is required for stability. Higher inductance improves overload current robustness (see the Overload Detection and Control section). To properly select the filter gain of the DRV421, combine these three parameters into a modified gain factor (GMOD) using Equation 2: GCORE u NWINDING GMOD (2) L The effective loop gain is proportional to the current-to-field transfer of the magnetic core (larger field means larger gain) and number of compensation coil windings (larger number of windings means larger compensation field for a given input current). The compensation coil inductance adds a low-frequency pole to the system, thus a larger inductance reduces the effective loop gain at higher frequencies. A more detailed review of system loop stability is provided in application report SLOA224, Designing with the DRV421: Control Loop Stability. For stable operation with a wide range of magnetic cores, the DRV421 features an adjustable loop filter controlled with pins GSEL1 and GSEL0. Table 1 lists the different filter settings and the related core properties. For standard closed-loop current transducer modules with medium inductance and small shunt resistor value, use gain setting 10. Gain setting 01 features a higher integrator-filter crossover frequency of 3.8 kHz, and is recommended for fault-current sensors with a large shunt resistor and medium inductance. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: DRV421 17 DRV421 SBOS704B – MAY 2015 – REVISED MARCH 2016 www.ti.com Feature Description (continued) Table 1. DRV421 Loop Gain Filter Settings and Relation to Magnetic Core Parameters COMPENSATION LOOP PROPERTIES AC OPEN-LOOP GAIN RANGE OF MODIFIED GAIN FACTOR GMOD RANGE OF COMPENSATION COIL INDUCTANCE L (NWINDING = 1000 and GCORE = 0.6 mT/A) 3.8 kHz 8.5 3 < GMOD < 12 100 mH < L < 200 mH 1 3.8 kHz 38 1 < GMOD < 3 200 mH < L < 600 mH 0 1.9 kHz 25 1 < GMOD