DRV8210PDSGR

DRV8210P DRV8210P SLVSGC3 – MAY 2020 SLVSGC3 – MAY 2020 www.ti.com DRV8210P 11-V H-Bridge Motor Driver with PWM Interface and Low-Power Sleep Mode 1 Features 3 Description • The DRV8210P is an integrated motor driver with four N-channel power FETs, charge pump regulator, and protection circuitry. The tripler charge pump architecture allows the device to operate down to 1.65 V to accommodate 1.8-V supply rails and low-battery conditions. The charge pump integrates all capacitors to reduce the overall solution size of the motor driver on a PCB and allows for 100% duty cycle operation. • • • • • • • N-channel H-bridge motor driver – MOSFET on-resistance: HS + LS 1 Ω – Drives one bidirectional brushed DC motor – One single- or dual-coil latching relay 1.65-V to 11-V operating supply voltage range High output current capability: 1.76-A peak Standard PWM Interface (IN1/IN2) Supports 1.8-V, 3.3-V, and 5-V logic inputs Ultra low-power sleep mode – VUVLO,VCC rising IOUT > IOCP Disabled tRETRY TJ > TTSD Disabled TJ < TTSD – THYS Overcurrent (OCP) Thermal Shutdown (TSD) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P 13 DRV8210P www.ti.com SLVSGC3 – MAY 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The application examples in this section highlight how to use the DRV8210P. 9.2 Typical Application 9.2.1 Full-Bridge Driving A typical application for the DRV8210P is driving a brushed DC motor or single-coil bistable latching relay bidriectionally (in forward and reverse) using the outputs as a full-bridge, or H-bridge, configuration. Figure 9-1 shows an example schematic for driving a motor, and Figure 9-2 shows an example schematic for driving a latching relay. VM VM VCC 0.1 …F CBulk VCC CBulk VCC 0.1 …F 0.1 …F 1 VM 0.1 …F 1 VM DRV821xPDSG 8 3 Thermal Pad nSLEEP OUT2 O Singlecoil relay 6 IN1 4 8 VCC 7 OUT1 3 7 OUT1 DRV821xPDSG 2 VCC 2 BDC Controller PWM VCC Controller Thermal Pad O nSLEEP 6 OUT2 IN1 GND IN2 4 PWM 5 PWM 5 GND IN2 PWM Figure 9-2. PWM interface relay-driving application Figure 9-1. PWM interface motor-driving application 9.2.1.1 Design Requirements Table 9-1 lists the required parameters for a typical usage case. Table 9-1. System design requirements DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor supply voltage VM 11 V Logic supply voltage VCC 3.3 V Target motor RMS current Imotor 300 mA Target relay current Irelay 50 mA 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 Supply Voltage The appropriate supply voltage depends on the ratings of the load (motor, solenoid, relay, etc.). In the case of a brushed DC motor, the supply voltage will impact the desired RPM. A higher voltage spins a brushed dc motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive windings of a motor, solenoid, or relay. 9.2.1.2.2 Control Interface Section 8.3.2.1 describes the PWM control interface. The DRV8210P is pin-to-pin compatible with the DRV8837 and DRV8837C PCB footprints. Figure 9-3 and Figure 9-4 show waveform examples of driving a motor with the PWM interface. Figure 9-5 and Figure 9-6 show waveform examples of driving a single-coil relay with the PWM 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P DRV8210P www.ti.com SLVSGC3 – MAY 2020 interface. The relay can be driven between the forward/reverse states and the brake/coast states as shown in the figures. 9.2.1.2.3 Low-Power Operation Section 8.4.2 describes how to enter low-power sleep mode. When entering sleep mode, TI recommends setting all inputs as a logic low to minimize system power. 9.2.1.3 Application Curves A. Channel 1 = IN1 Channel 2 = IN2 Channel 3 = OUT1 A. Channel 1 = IN1 Channel 4 = OUT2 Channel 2 = Motor Current Channel 3 = OUT1 Channel 4 = OUT2 Figure 9-3. PWM driving for a motor with 50% duty cycle, INx and OUTx voltages Figure 9-4. PWM driving for a motor with 50% duty cycle, signals and motor current A. Channel 1 = IN1 Channel 2 = IN2 Channel 3 = VOUT1 A. Channel 1 = IN1 Channel 2 = IN2 Channel 3 = VOUT1 Channel 4 = VOUT2 Channel 6 = Relay Switch Channel 7 = Relay Coil Current Channel 4 = VOUT2 Channel 6 = Relay Switch Channel 7 = Relay Coil Current Figure 9-5. PWM driving for a single-coil latching relay with driving profile FORWARD → COAST → REVERSE → COAST Figure 9-6. PWM driving for a single-coil latching relay with driving profile FORWARD → BRAKE → REVERSE → BRAKE 9.2.2 Dual-Coil Relay Driving The PWM interface may also be used to drive a dual-coil latching relay. Figure 9-7 shows an example schematic. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P 15 DRV8210P www.ti.com SLVSGC3 – MAY 2020 VM VCC CBulk 0.1 …F 0.1 …F 1 8 DRV821xPDSG VM 7 OUT1 3 Thermal Pad O nSLEEP OUT2 VM Controller VCC 2 Dualcoil relay VCC 6 IN1 4 PWM 5 GND IN2 PWM Figure 9-7. Dual-coil relay driving 9.2.2.1 Design Requirements Table 9-2 provides example requirements for a dual-coil relay application. Table 9-2. System design requirements DESIGN PARAMETER REFERENCE Motor supply voltage VM EXAMPLE VALUE 6V Logic supply voltage VCC 3.3 V Relay current IOUT1, IOUT2 500 mA pulse for 100 ms 9.2.2.2 Detailed Design Procedure 9.2.2.2.1 Supply Voltage The appropriate supply voltage depends on the ratings of the load. 9.2.2.2.2 Control Interface The PWM interface can be used to drive dual-coil relays. Section 8.3.2.1 describes the PWM control interface. Figure 9-8 and Figure 9-9 show a schematic and timing diagram for driving a dual-coil relay with the PWM interface. 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P DRV8210P www.ti.com SLVSGC3 – MAY 2020 VM Sleep mode Drive Coil1 Sleep mode Drive Coil2 Sleep mode IN1 IN2 VM Coil1 Coil2 VM VOUT2 VOUT1 IOUT1 VOUT1 Hi-Z IOUT2 Hi-Z Hi-Z Hi-Z Hi-Z GND Dual-coil relay VM VOUT2 Hi-Z GND IOUT1 Figure 9-8. Schematic of dual-coil relay driven by the OUTx H-bridge IOUT2 Figure 9-9. Timing diagram for driving a dual-coil relay with PWM interface Table 9-3 shows the logic table for the PWM interface. The descriptions in this table reflect how the input and output states drive the dual coil relay. When Coil1 is driven (OUT1 voltage is at GND), The voltage at OUT2 will go to VM. Because the center tap of the relay is also at VM, no current flows through Coil2. The same is true when Coil2 is driven; Coil1 shorts to VM. The body diodes of the high-side FETs act as freewheeling diodes, so extra external diodes are not needed. Figure 9-10 shows oscilloscope traces for this application. Table 9-3. PWM control table for dual-coil relay driving IN1 IN2 OUT1 OUT2 0 0 Hi-Z Hi-Z 0 1 L H 1 0 H L Drive Coil2 L Drive Coil1 and Coil2 (invalid state for a dual-coil latching relay) 1 1 L DESCRIPTION Outputs disabled (H-Bridge Hi-Z) Drive Coil1 9.2.2.2.3 Low-Power Operation Section 8.4.2 describes how to enter low-power sleep mode. When entering sleep mode, TI recommends setting all inputs as a logic low to minimize system power. To minimize leakage current into the OUTx pins (especially in battery-powered applications), connect the load from OUTx to GND. As shown in the previous section, connecting the load from OUTx to VM is also possible, but there may be some small leakage current into OUTx when it is disabled. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P 17 DRV8210P www.ti.com SLVSGC3 – MAY 2020 9.2.2.3 Application Curves A. Channel 1 = IN1 Channel 2 = IN2 Channel 3 = VOUT1 Channel 4 = VOUT2 Channel 6 = Relay Switch Channel 7 = Relay Coil1 Current Channel 8 = Relay Coil2 Current Figure 9-10. PWM driving for dual-coil relay 9.2.3 Current Sense A small shunt resistor on the GND pin can provide current sense information back to the microcontroller ADC. The microcontroller can use this information to detect motor load conditions, such as stall. shows an example schematic using the DRL package. If better current sensing dynamic range is needed, an amplifier can be added as shown in Figure 9-11. The DSG thermal pad may be connected to the board ground net or the GND pin/sense signal net. 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P DRV8210P www.ti.com SLVSGC3 – MAY 2020 VM VCC 0.1 …F CBulk 0.1 …F 1 VM 8 DRV821xPDSG Controller VCC 2 7 OUT1 BDC VCC nSLEEP Thermal Pad 3 O 6 OUT2 IN1 4 PWM 5 GND IN2 + PWM TLV905I ADC RSENSE CFILTER R1 ± R2 Figure 9-11. Current sense amplifier example 9.2.3.1 Design Requirements Table 9-4 provides example requirements for a current sensing application. Table 9-4. System design requirements DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor supply voltage VM 6V Logic supply voltage VCC 3.3 V Maximum voltage across RSENSE VSENSE 150 mV Motor RMS current IOUT1, IOUT2 500 mA Motor stall current IOUT1,stall, IOUT2,stall 1A 9.2.3.2 Detailed Design Procedure 9.2.3.2.1 Shunt Resistor Sizing The Absolute Maximum Ratings for the INx pins set the maximum voltage across the shunt resistor. If the signal on the INx pin is low, referenced at the board ground, then the INx pins are at a negative voltage with respect to the GND pin voltage. This sets the maximum sense voltage/GND pin voltage to 0.5 V. Figure 9-12 shows the relative pin voltages. IN1 VIN2 = 0 V + VGND,pin = -0.5 V + RSENSE IN2 GND VSENSE = 0.5 V - VGND,board = 0 V Figure 9-12. Pin voltages with respect to board ground using current sense resistor Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P 19 DRV8210P www.ti.com SLVSGC3 – MAY 2020 This example uses 150 mV for the maximum VSENSE, which is less than 0.5 V and provides some margin for safety or error. The maximum current through the motor will be the stall current, which is 1 A for this example. With this information, the sense resistance RSENSE can be calculated from the equation below. RSENSE = VSENSE / ISTALL = 0.15 / 1 = 0.15 Ω (1) Because the device GND pin voltage will vary with current through the sense resistor, the designers must also ensure that the logic pins meet VIL and VIH parameters,and the supply remains above VUVLO for proper operation. 9.3 Current Capability and Thermal Performance The output current and power dissipation capabilities of the driver depends heavily on the PCB design and external system conditions. This section provides some guidelines for calculating these values. 9.3.1 Power Dissipation and Output Current Capability Total power dissipation for the device consists of three main components: quiescent supply current dissipation (PVM and PVCC), the power MOSFET switching losses (PSW), and the power MOSFET RDS(on) (conduction) losses (PRDS). While other factors may contribute additional power losses, they are typically insignificant compared to the three main items. PTOT = PVM + PVCC + PSW + PRDS (2) PVM can be calculated from the nominal motor supply voltage (VVM) and the IVM active mode current specification. PVCC can be calculated from the nominal logic supply voltage (VVCC) and the IVCC active mode current specification. When VVCC < VVM, the DRV8210 draws active current from the VM pin rather than the VCC pin. During this operating condition, IVCC is typically less than 500 nA. PVM = VVM x IVM (3) PVM = 7 mW = 5 V x 1.4 mA (4) PVCC = VVCC x IVCC (5) PVCC = 0.594 mW = 3.3 V x 0.18 mA (6) PSW can be calculated from the nominal motor supply voltage (VVM), average output current (IRMS), switching frequency (fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications. PSW = PSW_RISE + PSW_FALL (7) PSW_RISE = 0.5 x VM x IRMS x tRISE x fPWM (8) PSW_FALL = 0.5 x VM x IRMS x tFALL x fPWM (9) PSW_RISE = 3.75 mW = 0.5 x 5 V x 0.5 A x 150 ns x 20 kHz (10) PSW_FALL = 3.75 mW = 0.5 x 5 V x 0.5 A x 150 ns x 20 kHz (11) PSW = 7.5 mW = 3.75 mW + 3.75 mW (12) PRDS can be calculated from the device RDS(on) and average output current (IRMS). PRDS = IRMS 2 x (RDS(ON)_HS + RDS(ON)_LS) (13) RDS(ON) has a strong correlation with the device temperature. Assuming a device junction temperature of 85 °C, RDS(on) could increase ~1.5x based on the normalized temperature data. The calculation below shows this derating factor. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P DRV8210P www.ti.com SLVSGC3 – MAY 2020 PRDS = 394 mW = (0.5 A)2 x (525 mΩ x 1.5 + 525 mΩ x 1.5) (14) Based on the example calculations above, the expressions below calculate the total expected power dissipation for the device. PTOT = PVM + PVCC + PSW + PRDS (15) PTOT = 409 mW = 7 mW + 0.594 mW + 7.5 mW + 394 mW (16) The driver's junction temperature can be estimated using PTOT, device ambient temperature (TA), and package thermal resistance (RθJA). The value for RθJA depends heavily on the PCB design and copper heat sinking around the device. Section 9.3.2 describes this dependence in greater detail. TJ = (PTOT x RθJA) + TA (17) TJ = 126°C = (0.409 W x 99.6 °C/W) + 85°C (18) The device junction temperature should remain below its absolute maximum rating for all system operating conditions. The calculations in this section provide reasonable estimates for junction temperature. However, other methods based on temperature measurements taken during system operation are more realistic and reliable. Additional information on motor driver current ratings and power dissipation can be found in Section 9.3.2 and Section 12.1.1. 9.3.2 Thermal Performance The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions. The data in this section was simulated using the following criteria: • • 2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). – Top layer: DRV8210P WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. – Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8210P. Bottom layer copper area varies with top copper area. 4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). – Top layer: DRV8210P WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. – Mid layer 1: GND plane thermally connected to DRV8210P thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. – Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. – Bottom layer: signal layer with small copper pad underneath DRV8210P and thermally connected through via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the package (2 mm x 2 mm). Bottom pad size remains constant as top copper plane is varied. Figure 9-13 shows an example of the simulated board for the HTSSOP package. Table 9-5 shows the dimensions of the board that were varied for each simulation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P 21 DRV8210P www.ti.com SLVSGC3 – MAY 2020 A A Figure 9-13. WSON PCB model top layer Table 9-5. Dimension A for 16-pin PWP package Cu area (mm2) Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 9.3.2.1 Steady-State Thermal Performance "Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout. Figure 9-14. WSON, PCB junction-to-ambient thermal resistance vs copper area Figure 9-15. WSON, junction-to-board characterization parameter vs copper area 9.3.2.2 Transient Thermal Performance The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include • 22 Motor start-up when the rotor is initially stationary. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P DRV8210P www.ti.com • • SLVSGC3 – MAY 2020 Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the WSON package. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance. Figure 9-16. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts Figure 9-17. WSON package Junction-to-ambient thermal impedance for 2-oz copper layouts Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P 23 DRV8210P www.ti.com SLVSGC3 – MAY 2020 10 Power Supply Recommendations 10.1 Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local bulk capacitance needed depends on a variety of factors, including: • The highest current required by the motor or load • The capacitance of the power supply and ability to source current • The amount of parasitic inductance between the power supply and motor system • The acceptable voltage ripple of the system • The motor braking method (if applicable) The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended minimum value, but system level testing is required to determine the appropriately sized bulk capacitor. Power Supply Parasitic Wire Inductance Motor Drive System VBB + ± + Motor Driver GND Local Bulk Capacitor IC Bypass Capacitor Figure 10-1. System Supply Parasitics Example 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P DRV8210P www.ti.com SLVSGC3 – MAY 2020 11 Layout 11.1 Layout Guidelines Since the DRV8210P device has integrated power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. For more information on layout recommendations, please see the application note Best Practices for Board Layout of Motor Drivers. • • • • • • • Low ESR ceramic capacitors should be utilized for the VM-to-GND and VCC-to-GND bypass capacitors. X5R and X7R types are recommended. The VM and VCC power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. GND should connect directly on the PCB ground plane. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. 11.2 Layout Example CBULK 0.1 …F 0.1 …F VM MOT+ VM 1 OUT1 2 8 VCC 7 nSLEEP 6 IN1 5 IN2 VCC Thermal MOT- OUT2 3 GND 4 Pad Figure 11-1. Simplified Layout Example Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P 25 DRV8210P www.ti.com SLVSGC3 – MAY 2020 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Texas Instruments, Calculating Motor Driver Power Dissipation application report • Texas Instruments, PowerPAD™ Made Easy application report application report • Texas Instruments, PowerPAD™ Thermally Enhanced Package application report • Texas Instruments, Understanding Motor Driver Current Ratings application report • Texas Instruments, Best Practices for Board Layout of Motor Drivers application report 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary 26 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P DRV8210P www.ti.com SLVSGC3 – MAY 2020 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8210P 27 PACKAGE OPTION ADDENDUM www.ti.com 3-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DRV8210PDSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 210P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of