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DRV8350, DRV8350R
DRV8353, DRV8353R
SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
DRV835x 100-V Three-Phase Smart Gate Driver
1 Features
3 Description
•
The DRV835x family of devices are highly-integrated
gate drivers for three-phase brushless DC (BLDC)
motor applications. These applications include fieldoriented control (FOC), sinusoidal current control, and
trapezoidal current control of BLDC motors. The
device variants provide optional integrated current
shunt amplifiers to support different motor control
schemes and a buck regulator to power the gate
driver or external controller.
•
•
•
•
•
•
•
•
9 to 100-V, Triple half-bridge gate driver
– Optional integrated buck regulator
– Optional triple low-side current shunt amplifiers
Smart gate drive architecture
– Adjustable slew rate control for EMI
performance
– VGS handshake and minimum dead-time
insertion to prevent shoot-through
– 50-mA to 1-A peak source current
– 100-mA to 2-A peak sink current
– dV/dt mitigation through strong pulldown
Integrated gate driver power supplies
– High-side doubler charge pump For 100%
PWM duty cycle control
– Low-side linear regulator
Integrated LM5008A buck regulator
– 6 to 95-V operating voltage range
– 2.5 to 75-V, 350-mA output capability
Integrated triple current shunt amplifiers
– Adjustable gain (5, 10, 20, 40 V/V)
– Bidirectional or unidirectional support
6x, 3x, 1x, and independent PWM modes
– Supports 120° sensored operation
SPI or hardware interface available
Low-power sleep mode (20 µA at VVM = 48-V)
Integrated protection features
– VM undervoltage lockout (UVLO)
– Gate drive supply undervoltage (GDUV)
– MOSFET VDS overcurrent protection (OCP)
– MOSFET shoot-through prevention
– Gate driver fault (GDF)
– Thermal warning and shutdown (OTW/OTSD)
– Fault condition indicator (nFAULT)
The DRV835x uses smart gate drive (SGD)
architecture to decrease the number of external
components that are typically necessary for MOSFET
slew rate control and protection circuits. The SGD
architecture also optimizes dead time to prevent
shoot-through conditions, provides flexibility in
decreasing electromagnetic interference (EMI) by
MOSFET slew rate control, and protects against gate
short circuit conditions through VGS monitors. A
strong gate pulldown circuit helps prevent unwanted
dV/dt parasitic gate turn on events
Various PWM control modes (6x, 3x, 1x, and
independent) are supported for simple interfacing to
the external controller. These modes can decrease
the number of outputs required of the controller for
the motor driver PWM control signals. This family of
devices also includes 1x PWM mode for simple
sensored trapezoidal control of a BLDC motor by
using an internal block commutation table.
Device Information(1)
PART NUMBER
5.00 mm × 5.00 mm
DRV8350R
VQFN (48)
7.00 mm × 7.00 mm
DRV8353
WQFN (40)
6.00 mm × 6.00 mm
DRV8353R
VQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
9 to 75 V
DRV835x
PWM
Controller
3-phase brushless-DC (BLDC) motor modules
Fans, blowers, and pumps
E-Bikes, E-scooters, and E-mobility
Power and garden tools, lawn mowers
Drones, robotics, and RC toys
Factory automation and textile machines
BODY SIZE (NOM)
WQFN (32)
2 Applications
•
•
•
•
•
•
PACKAGE
DRV8350
SPI or H/W
nFAULT
Current Sense
350 mA
Three-Phase
Smart Gate Driver
Protection
7 to 100 V
Drain
Sense
Gate Drive
N-Channel
MOSFETs
1
M
Current
Sense
3x Shunt Amplifiers
Buck Regulator
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8350, DRV8350R
DRV8353, DRV8353R
SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions ......................... 3
Specifications....................................................... 10
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
Absolute Maximum Ratings ....................................
ESD Ratings ..........................................................
Recommended Operating Conditions.....................
Thermal Information ................................................
Electrical Characteristics.........................................
SPI Timing Requirements .......................................
Typical Characteristics ............................................
10
11
11
11
12
18
19
Detailed Description ............................................ 21
8.1
8.2
8.3
8.4
8.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
21
22
30
53
54
8.6 Register Maps ......................................................... 56
9
Application and Implementation ........................ 65
9.1 Application Information............................................ 65
9.2 Typical Application ................................................. 65
10 Power Supply Recommendations ..................... 77
10.1 Bulk Capacitance Sizing ....................................... 77
11 Layout................................................................... 78
11.1 Layout Guidelines ................................................. 78
11.2 Layout Example .................................................... 79
12 Device and Documentation Support ................. 80
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
80
80
81
81
81
81
81
81
13 Mechanical, Packaging, and Orderable
Information ........................................................... 81
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2018) to Revision A
Page
•
Changed document status to production data........................................................................................................................ 1
•
Deleted preview only note from DRV8350 and DRV8353 devices. ....................................................................................... 1
2
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: DRV8350 DRV8350R DRV8353 DRV8353R
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com
SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
5 Device Comparison Table
DEVICE
VARIANT
SHUNT AMPLIFIERS
BUCK REGULATOR
DRV8350H
DRV8350
None
DRV8350S
DRV8353H
SPI (S)
Hardware (H)
None
DRV8353S
SPI (S)
3
DRV8353RH
DRV8353R
Hardware (H)
350 mA (R)
DRV8350RS
DRV8353
SPI (S)
0
DRV8350RH
DRV8350R
INTERFACE
Hardware (H)
Hardware (H)
350 mA (R)
DRV8353RS
SPI (S)
6 Pin Configuration and Functions
DVDD
INLC
INHC
INLB
INHB
28
27
26
25
INHB
25
GND
INLB
26
29
INHC
27
30
INLC
28
VGLS
DVDD
29
31
GND
30
CPL
VGLS
31
DRV8350S RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
32
CPL
32
DRV8350H RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
CPH
1
24
INLA
CPH
1
24
INLA
VM
2
23
INHA
VM
2
23
INHA
VDRAIN
3
22
ENABLE
VDRAIN
3
22
ENABLE
VCP
4
21
NC
VCP
4
21
nSCS
Thermal
Pad
Thermal
Pad
13
14
15
16
SHC
GLC
SLC
Not to scale
GHC
nFAULT
12
17
11
8
SHB
SLA
GHB
nFAULT
10
17
GLB
8
9
SLA
SLB
SDO
16
18
SLC
7
15
GLA
GLC
MODE
14
18
SHC
7
13
GLA
GHC
SDI
12
SCLK
19
11
20
6
SHB
5
SHA
GHB
GHA
IDRIVE
10
VDS
19
GLB
20
6
9
5
SHA
SLB
GHA
Not to scale
Pin Functions—32-Pin DRV8350 Devices
PIN
TYPE (1)
NO.
DESCRIPTION
NAME
DRV8350H
DRV8350S
CPH
1
1
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
32
32
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
DVDD
29
29
PWR
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This
regulator can source up to 10 mA externally.
ENABLE
22
22
I
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs pulse can be used
to reset fault conditions.
GHA
5
5
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB
12
12
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC
13
13
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA
7
7
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
10
10
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
(1)
PWR = power, I = input, O = output, NC = no connection, OD = open-drain
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRV8350 DRV8350R DRV8353 DRV8353R
3
DRV8350, DRV8350R
DRV8353, DRV8353R
SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
www.ti.com
Pin Functions—32-Pin DRV8350 Devices (continued)
PIN
TYPE (1)
NO.
DESCRIPTION
NAME
DRV8350H
DRV8350S
GLC
15
15
O
GND
30
30
PWR
IDRIVE
19
—
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA
23
23
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB
25
25
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC
27
27
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA
24
24
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB
26
26
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC
28
28
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE
18
—
I
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC
21
—
NC
No internal connection. This pin can be left floating or connected to system ground.
nFAULT
17
17
OD
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS
—
21
I
Serial chip select. A logic low on this pin enables serial interface communication.
SCLK
—
20
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI
—
19
I
Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO
—
18
OD
SHA
6
6
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
11
11
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
14
14
I
High-side source sense input. Connect to the high-side power MOSFET source.
SLA
8
8
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLB
9
9
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLC
16
16
I
Low-side source sense input. Connect to the low-side power MOSFET source.
VCP
4
4
PWR
VDRAIN
3
3
I
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS
20
—
I
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS
31
31
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VM
2
2
PWR
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Device primary ground. Connect to system ground.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VIN
SW
DGND
DVDD
INLC
INHC
INLB
42
41
40
39
38
37
INLB
37
VCC
INHC
38
43
INLC
39
BST
DVDD
40
44
DGND
41
45
SW
42
RCL
VIN
43
RT/SD
VCC
44
46
BST
45
FB
RCL
46
47
RT/SD
47
DRV8350RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
48
FB
48
DRV8350RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
GND
1
36
INHB
GND
1
36
INHB
VGLS
2
35
INLA
VGLS
2
35
INLA
CPL
3
34
INHA
CPL
3
34
INHA
CPH
4
33
ENABLE
CPH
4
33
ENABLE
VM
5
32
NC
VM
5
32
nSCS
VDRAIN
6
31
VDS
VDRAIN
6
31
SCLK
VCP
7
30
IDRIVE
VCP
7
30
SDI
GHA
8
29
MODE
GHA
8
29
SDO
SHA
9
28
nFAULT
SHA
9
28
nFAULT
GLA
10
27
AGND
GLA
10
27
AGND
SLA
11
26
NC
SLA
11
26
NC
NC
12
25
NC
NC
12
25
NC
4
19
20
21
22
23
24
SHC
GLC
SLC
NC
NC
NC
24
NC
18
23
NC
GHC
22
NC
17
21
SLC
16
20
GLC
SHB
19
SHC
GHB
18
GHC
15
17
GLB
16
SHB
GHB
14
15
GLB
Pad
13
14
Submit Documentation Feedback
Not to scale
Thermal
NC
13
NC
SLB
Pad
SLB
Thermal
Not to scale
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: DRV8350 DRV8350R DRV8353 DRV8353R
DRV8350, DRV8350R
DRV8353, DRV8353R
www.ti.com
SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
Pin Functions—48-Pin DRV8350R Devices
PIN
TYPE (1)
NO.
DESCRIPTION
NAME
DRV8350RH
DRV8350RS
AGND
27
27
PWR
Device analog ground. Connect to system ground.
BST
45
45
PWR
Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
CPH
4
4
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
3
3
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
DGND
41
41
PWR
Device digital ground. Connect to system ground.
DVDD
40
40
PWR
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This
regulator can source up to 10 mA externally.
ENABLE
33
33
I
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
FB
48
48
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GHA
8
8
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB
17
17
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC
18
18
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA
10
10
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
15
15
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC
20
20
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND
1
1
PWR
IDRIVE
30
—
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA
34
34
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB
36
36
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC
38
38
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA
35
35
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB
37
37
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC
39
39
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE
29
—
I
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC
12
12
NC
No internal connection. This pin can be left floating or connected to system ground.
NC
13
13
NC
No internal connection. This pin can be left floating or connected to system ground.
NC
22
22
NC
No internal connection. This pin can be left floating or connected to system ground.
NC
23
23
NC
No internal connection. This pin can be left floating or connected to system ground.
NC
24
24
NC
No internal connection. This pin can be left floating or connected to system ground.
NC
25
25
NC
No internal connection. This pin can be left floating or connected to system ground.
NC
26
26
NC
No internal connection. This pin can be left floating or connected to system ground.
NC
32
—
NC
No internal connection. This pin can be left floating or connected to system ground.
nFAULT
28
28
OD
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS
—
32
I
Serial chip select. A logic low on this pin enables serial interface communication.
RCL
46
46
I
Current limit off time set input. Connect a resistor between RCL and GND.
RT/SD
47
47
I
On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
SCLK
—
31
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI
—
30
I
Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO
—
29
OD
SHA
9
9
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
16
16
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
19
19
I
High-side source sense input. Connect to the high-side power MOSFET source.
SLA
11
11
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLB
14
14
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLC
21
21
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SW
42
42
O
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCC
44
44
PWR
7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between
the VCC and GND pins.
VCP
7
7
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN
6
6
I
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS
31
—
I
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS
2
2
PWR
(1)
Device primary ground. Connect to system ground.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
PWR = power, I = input, O = output, NC = no connection, OD = open-drain
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRV8350 DRV8350R DRV8353 DRV8353R
5
DRV8350, DRV8350R
DRV8353, DRV8353R
SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
www.ti.com
Pin Functions—48-Pin DRV8350R Devices (continued)
PIN
TYPE (1)
NO.
DESCRIPTION
NAME
DRV8350RH
DRV8350RS
VIN
43
43
PWR
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and GND pins.
VM
5
5
PWR
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
INHC
INLB
INHB
INLA
INHA
ENABLE
35
34
33
32
31
ENABLE
31
36
INHA
32
INLC
INLA
33
DVDD
INHB
34
37
INLB
35
38
INHC
36
GND
INLC
37
VGLS
DVDD
38
39
GND
39
DRV8353S RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
40
VGLS
40
DRV8353H RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
CPL
1
30
GAIN
CPL
1
30
nSCS
CPH
2
29
VDS
CPH
2
29
SCLK
VM
3
28
IDRIVE
VM
3
28
SDI
VDRAIN
4
27
MODE
VDRAIN
4
27
SDO
VCP
5
26
nFAULT
VCP
5
26
nFAULT
GHA
6
25
AGND
GHA
6
25
AGND
SHA
7
24
VREF
SHA
7
24
VREF
GLA
8
23
SOA
GLA
8
23
SOA
SPA
9
22
SOB
SPA
9
22
SOB
SNA
10
21
SOC
SNA
10
21
SOC
15
16
17
18
19
20
GHB
SHC
GLC
SPC
SNC
14
GHC
13
20
SNC
GLB
19
SPC
SHB
18
GLC
12
17
SHC
Pad
11
16
Not to scale
Thermal
SPB
15
GHB
14
GHC
13
GLB
12
SPB
SHB
11
SNB
Pad
SNB
Thermal
Not to scale
Pin Functions—40-Pin DRV8353 Devices
PIN
TYPE (1)
NO.
DESCRIPTION
NAME
DRV8353H
DRV8353S
AGND
25
25
PWR
Device analog ground. Connect to system ground.
CPH
2
2
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
1
1
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
DVDD
38
38
PWR
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This
regulator can source up to 10 mA externally.
ENABLE
31
31
I
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
GAIN
30
—
I
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND
39
39
PWR
GHA
6
6
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB
15
15
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC
16
16
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA
8
8
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
13
13
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC
18
18
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE
28
—
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA
32
32
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB
34
34
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC
36
36
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
(1)
6
Device power ground. Connect to system ground.
PWR = power, I = input, O = output, NC = no connection, OD = open-drain
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Pin Functions—40-Pin DRV8353 Devices (continued)
PIN
TYPE (1)
NO.
DESCRIPTION
NAME
DRV8353H
DRV8353S
INLA
33
33
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB
35
35
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC
37
37
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE
27
—
I
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT
26
26
OD
nSCS
—
30
I
Serial chip select. A logic low on this pin enables serial interface communication.
SCLK
—
29
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI
—
28
I
Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO
—
27
OD
SHA
7
7
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
14
14
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
17
17
I
High-side source sense input. Connect to the high-side power MOSFET source.
SNA
10
10
I
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB
11
11
I
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC
20
20
I
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA
23
23
O
Shunt amplifier output.
SOB
22
22
O
Shunt amplifier output.
SOC
21
21
O
Shunt amplifier output.
SPA
9
9
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
SPB
12
12
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
SPC
19
19
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
VCP
5
5
PWR
VDRAIN
4
4
I
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS
29
—
I
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS
40
40
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VM
3
3
PWR
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VREF
24
24
PWR
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the
VREF and AGND pins.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
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VIN
SW
DGND
DVDD
INLC
INHC
INLB
42
41
40
39
38
37
INLB
37
VCC
INHC
38
43
INLC
39
BST
DVDD
40
44
DGND
41
45
SW
42
RCL
VIN
43
RT/SD
VCC
44
46
BST
45
FB
RCL
46
47
RT/SD
47
DRV8353RS RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
48
FB
48
DRV8353RH RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
GND
1
36
INHB
GND
1
36
INHB
VGLS
2
35
INLA
VGLS
2
35
INLA
CPL
3
34
INHA
CPL
3
34
INHA
CPH
4
33
ENABLE
CPH
4
33
ENABLE
VM
5
32
GAIN
VM
5
32
nSCS
VDRAIN
6
31
SCLK
VDRAIN
6
31
Thermal
Pad
VDS
Thermal
Pad
19
20
21
22
23
24
GLC
SPC
SNC
SOC
SOB
Not to scale
SHC
SOA
18
25
GHC
12
17
SNA
16
SOA
SHB
25
GHB
12
15
VREF
SNA
GLB
26
14
11
13
SPA
SPB
VREF
SNB
26
24
11
SOB
AGND
SPA
23
27
SOC
10
22
GLA
SNC
AGND
21
27
SPC
10
20
nFAULT
GLA
GLC
28
19
9
SHC
SHA
18
nFAULT
GHC
28
17
9
16
SDO
SHA
SHB
SDI
29
GHB
30
8
15
7
GHA
GLB
VCP
MODE
14
IDRIVE
29
13
30
8
SPB
7
SNB
VCP
GHA
Not to scale
Pin Functions—48-Pin DRV8353R Devices
PIN
TYPE (1)
NO.
DESCRIPTION
NAME
DRV8353RH
DRV8353RS
AGND
27
27
PWR
Device analog ground. Connect to system ground.
BST
45
45
PWR
Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
CPH
4
4
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
3
3
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
DGND
41
41
PWR
Device ground. Connect to system ground.
DVDD
40
40
PWR
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins.
This regulator can source up to 10 mA externally.
ENABLE
33
33
I
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
FB
48
48
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GAIN
32
—
I
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND
1
1
PWR
GHA
8
8
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB
17
17
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC
18
18
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA
10
10
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
15
15
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC
20
20
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE
30
—
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA
34
34
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB
36
36
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC
38
38
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA
35
35
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB
37
37
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC
39
39
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE
29
—
I
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT
28
28
OD
(1)
8
Device power ground. Connect to system ground.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
PWR = power, I = input, O = output, NC = no connection, OD = open-drain
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Pin Functions—48-Pin DRV8353R Devices (continued)
PIN
TYPE (1)
NO.
DESCRIPTION
NAME
DRV8353RH
DRV8353RS
nSCS
—
32
I
Serial chip select. A logic low on this pin enables serial interface communication.
RCL
46
46
I
Current limit off time set input. Connect a resistor between RCL and GND.
RT/SD
47
47
I
On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
SCLK
—
31
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI
—
30
I
Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO
—
29
OD
SHA
9
9
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
16
16
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
19
19
I
High-side source sense input. Connect to the high-side power MOSFET source.
SNA
12
12
I
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB
13
13
I
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC
22
22
I
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA
25
25
O
Shunt amplifier output.
SOB
24
24
O
Shunt amplifier output.
SOC
23
23
O
Shunt amplifier output.
SPA
11
11
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
SPB
14
14
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
SPC
21
21
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the
current shunt resistor.
SW
42
42
O
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
VCC
44
44
PWR
7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between
the VCC and GND pins.
VCP
7
7
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN
6
6
I
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS
31
—
I
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS
2
2
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VIN
43
43
PWR
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
VM
5
5
PWR
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VREF
26
26
PWR
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the
VREF and AGND pins.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
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7 Specifications
7.1 Absolute Maximum Ratings
at TA = –40°C to +125°C (unless otherwise noted) (1)
MIN
MAX
UNIT
GATE DRIVER
Power supply pin voltage (VM)
–0.3
80
V
Voltage differential between ground pins (AGND, BGND, DGND, PGND)
–0.3
0.3
V
MOSFET drain sense pin voltage (VDRAIN)
–0.3
102
0
2
Charge pump pin voltage (CPH, VCP)
–0.3
VVDRAIN + 16
V
Charge-pump negative-switching pin voltage (CPL)
–0.3
VVDRAIN
V
Low-side gate drive regulator pin voltage (VGLS)
–0.3
18
V
Internal logic regulator pin voltage (DVDD)
–0.3
5.75
V
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO,
VDS)
–0.3
5.75
V
Continuous high-side gate drive pin voltage (GHx)
–5 (2)
VVCP + 0.3
V
Transient 200-ns high-side gate drive pin voltage (GHx)
–10
VVCP + 0.3
V
High-side gate drive pin voltage with respect to SHx (GHx)
–0.3
16
V
Continuous high-side source sense pin voltage (SHx)
–5 (2)
102
V
Continuous high-side source sense pin voltage (SHx)
–5 (2)
VVDRAIN + 5
V
Transient 200-ns high-side source sense pin voltage (SHx)
–10
VVDRAIN + 10
V
Continuous low-side gate drive pin voltage (GLx)
–1.0
VVGLS + 0.3
V
Transient 200-ns low-side gate drive pin voltage (GLx)
–5.0
VVGLS + 0.3
V
Gate drive pin source current (GHx, GLx)
Internally limited
Internally limited
A
Gate drive pin sink current (GHx, GLx)
Internally limited
Internally limited
A
Continuous low-side source sense pin voltage (SLx)
–1
1
V
Transient 200-ns low-side source sense pin voltage (SLx)
–5
5
V
Continuous shunt amplifier input pin voltage (SNx, SPx)
–1
1
V
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)
–5
5
V
Reference input pin voltage (VREF)
–0.3
5.75
V
Shunt amplifier output pin voltage (SOx)
–0.3
VVREF + 0.3
V
Power supply pin voltage (VIN)
–0.3
100
V
Bootstrap pin voltage (BST)
–0.3
114
V
Bootstrap pin voltage with respect to SW (BST)
–0.3
14
V
Bootstrap pin voltage with respect to VCC (BST)
–0.3
100
V
MOSFET drain sense pin voltage slew rate (VDRAIN)
V
V/µs
BUCK REGULATOR
Switching node pin voltage (SW)
–1
VVIN
V
Internal regulator pin voltage (VCC)
–0.3
14
V
Input pin voltage (FB, RCL, RT/SD)
–0.3
7
V
Ambient temperature, TA
–40
125
°C
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
DRV835x
(1)
(2)
10
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum.
This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V.
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SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
7.3 Recommended Operating Conditions
at TA = –40°C to +125°C (unless otherwise noted)
MIN
MAX
UNIT
GATE DRIVER
VVM
Gate driver power supply voltage (VM)
9
75
V
VVDRAIN
Charge pump reference and drain voltage sense (VDRAIN)
7
100
V
VI
Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS)
0
5.5
fPWM
Applied PWM signal (INHx, INLx)
0
200 (1)
kHz
tSH
Switch-node slew rate range (SHx)
0
2
V/ns
IGATE_HS
High-side average gate-drive current (GHx)
0
25 (1)
mA
IGATE_LS
Low-side average gate-drive current (GLx)
0
25 (1)
mA
IDVDD
External load current (DVDD)
0
10 (1)
mA
VVREF
Reference voltage input (VREF)
3
5.5
ISO
Shunt amplifier output current (SOx)
0
5
VOD
Open drain pullup voltage (nFAULT, SDO)
0
5.5
IOD
Open drain output current (nFAULT, SDO)
0
5
mA
6
95
V
V
V
mA
V
BUCK REGULATOR
VVIN
Power supply voltage (VIN)
DRV835x
TA
Operating ambient temperature
–40
125
°C
TJ
Operating junction temperature
–40
150
°C
(1)
Power dissipation and thermal limits must be observed.
7.4 Thermal Information
THERMAL METRIC (1)
DRV8350
DRV8353
DRV835xR
RTV (WQFN)
RTA (WQFN)
RGZ (VQFN)
32 PINS
40 PINS
48 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
29.2
26.1
24.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
15.2
13.1
12.0
°C/W
RθJB
Junction-to-board thermal resistance
9.2
8.4
7.1
°C/W
ψJT
Junction-to-top characterization parameter
0.1
0.1
0.1
°C/W
ψJB
Junction-to-board characterization parameter
9.2
8.4
7.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.2
1.1
0.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (DVDD, VCP, VGLS, VM)
IVM
VM operating supply current
VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V
8.5
13
mA
IVDRAIN
VDRAIN operating supply current
VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V
1.9
4
mA
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C
20
40
ISLEEP
Sleep mode supply current
tRST
Reset pulse time
ENABLE = 0 V period to reset faults
tWAKE
Turnon time
VVM > VUVLO, ENABLE = 3.3 V to outputs ready
tSLEEP
Turnoff time
ENABLE = 0 V to device sleep mode
VDVDD
DVDD regulator voltage
IDVDD = 0 to 10 mA
VVCP
VVGLS
VCP operating voltage
with respect to VDRAIN
VGLS operating voltage
with respect to GND
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C
100
5
µA
40
µs
1
ms
1
ms
4.75
5
5.25
VVM = 15 V, IVCP = 0 to 25 mA
9
10.5
12
VVM = 12 V, IVCP = 0 to 20 mA
7.5
10
11.5
VVM = 10 V, IVCP = 0 to 15 mA
6
8
9.5
8.5
VVM = 9 V, IVCP = 0 to 10 mA
5.5
7.5
VVM = 15 V, IVGLS = 0 to 25 mA
13
14.5
16
VVM = 12 V, IVGLS = 0 to 20 mA
10
11.5
12.5
VVM = 10 V, IVGLS = 0 to 15 mA
8
9.5
10.5
VVM = 9 V, IVGLS = 0 to 10 mA
7
8.5
9.5
V
V
V
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI)
VIL
Input logic low voltage
VIH
Input logic high voltage
0
0.8
1.5
5.5
VHYS
Input logic hysteresis
IIL
Input logic low current
VVIN = 0 V
IIH
Input logic high current
VVIN = 5 V
RPD
Pulldown resistance
To GND
100
kΩ
tPD
Propagation delay
INHx/INLx transition to GHx/GLx transition
200
ns
100
–5
50
V
V
mV
5
µA
70
µA
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
VI1
Input mode 1 voltage
Tied to GND
0
V
VI2
Input mode 2 voltage
47 kΩ ± 5% to tied GND
1.9
V
VI3
Input mode 3 voltage
Hi-Z
3.1
V
VI4
Input mode 4 voltage
Tied to DVDD
5
V
RPU
Pullup resistance
Internal pullup to DVDD
50
kΩ
RPD
Pulldown resistance
Internal pulldown to GND
84
kΩ
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
VI1
Input mode 1 voltage
Tied to GND
0
V
VI2
Input mode 2 voltage
18 kΩ ± 5% tied to GND
0.8
V
VI3
Input mode 3 voltage
75 kΩ ± 5% tied to GND
1.7
V
VI4
Input mode 4 voltage
Hi-Z
2.5
V
VI5
Input mode 5 voltage
75 kΩ ± 5% tied to DVDD
3.3
V
VI6
Input mode 6 voltage
18 kΩ ± 5% tied to DVDD
4.2
V
VI7
Input mode 7 voltage
Tied to DVDD
RPU
Pullup resistance
RPD
Pulldown resistance
5
V
Internal pullup to DVDD
73
kΩ
Internal pulldown to GND
73
kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)
VOL
Output logic low voltage
IO = 5 mA
IOZ
Output high impedance leakage
VO = 5 V
12
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–2
0.125
V
2
µA
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: DRV8350 DRV8350R DRV8353 DRV8353R
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DRV8353, DRV8353R
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SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GATE DRIVERS (GHx, GLx)
VVM = 15 V, IVCP = 0 to 25 mA
VGSH
VGSL
tDEAD
High-side gate drive voltage
with respect to SHx
Low-side gate drive voltage
with respect to PGND
Gate drive
dead time
SPI Device
9
10.5
12
7.5
10
11.5
6
8
9.5
VVM = 9 V, IVCP = 0 to 10 mA
5.5
7.5
8.5
VVM = 15 V, IVGLS = 0 to 25 mA
9.5
11
12.5
VVM = 12 V, IVGLS = 0 to 20 mA
9
10.5
12
VVM = 10 V, IVGLS = 0 to 15 mA
7.5
9
10.5
VVM = 9 V, IVGLS = 0 to 10 mA
6.5
8
9.5
VVM = 12 , IVCP = 0 to 20 mA
VVM = 10 V, IVCP = 0 to 15 mA
DEAD_TIME = 00b
50
DEAD_TIME = 01b
100
DEAD_TIME = 10b
200
DEAD_TIME = 11b
400
H/W Device
tDRIVE
Peak current
gate drive time
SPI Device
500
TDRIVE = 01b
1000
TDRIVE = 10b
2000
TDRIVE = 11b
4000
Peak source
gate current
50
IDRIVEP_HS or IDRIVEP_LS = 0010b
100
IDRIVEP_HS or IDRIVEP_LS = 0011b
150
IDRIVEP_HS or IDRIVEP_LS = 0100b
300
IDRIVEP_HS or IDRIVEP_LS = 0101b
350
IDRIVEP_HS or IDRIVEP_LS = 0110b
400
IDRIVEP_HS or IDRIVEP_LS = 0111b
450
IDRIVEP_HS or IDRIVEP_LS = 1000b
550
IDRIVEP_HS or IDRIVEP_LS = 1001b
600
IDRIVEP_HS or IDRIVEP_LS = 1010b
650
IDRIVEP_HS or IDRIVEP_LS = 1011b
700
IDRIVEP_HS or IDRIVEP_LS = 1100b
850
IDRIVEP_HS or IDRIVEP_LS = 1101b
900
IDRIVEP_HS or IDRIVEP_LS = 1110b
950
IDRIVEP_HS or IDRIVEP_LS = 1111b
1000
mA
50
IDRIVE = 18 kΩ ± 5% tied to GND
100
IDRIVE = 75 kΩ ± 5% tied to GND
150
IDRIVE = Hi-Z
300
IDRIVE = 75 kΩ ± 5% tied to DVDD
450
IDRIVE = 18 kΩ ± 5% tied to DVDD
700
IDRIVE = Tied to DVDD
Copyright © 2018–2019, Texas Instruments Incorporated
ns
50
IDRIVEP_HS or IDRIVEP_LS = 0001b
IDRIVE = Tied to GND
H/W Device
ns
4000
IDRIVEP_HS or IDRIVEP_LS = 0000b
IDRIVEP
V
100
TDRIVE = 00b
H/W Device
SPI Device
V
1000
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SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
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Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPI Device
IDRIVEN
Peak sink
gate current
H/W Device
MIN
TYP
IDRIVEN_HS or IDRIVEN_LS = 0000b
100
IDRIVEN_HS or IDRIVEN_LS = 0001b
100
IDRIVEN_HS or IDRIVEN_LS = 0010b
200
IDRIVEN_HS or IDRIVEN_LS = 0011b
300
IDRIVEN_HS or IDRIVEN_LS = 0100b
600
IDRIVEN_HS or IDRIVEN_LS = 0101b
700
IDRIVEN_HS or IDRIVEN_LS = 0110b
800
IDRIVEN_HS or IDRIVEN_LS = 0111b
900
IDRIVEN_HS or IDRIVEN_LS = 1000b
1100
IDRIVEN_HS or IDRIVEN_LS = 1001b
1200
IDRIVEN_HS or IDRIVEN_LS = 1010b
1300
IDRIVEN_HS or IDRIVEN_LS = 1011b
1400
IDRIVEN_HS or IDRIVEN_LS = 1100b
1700
IDRIVEN_HS or IDRIVEN_LS = 1101b
1800
IDRIVEN_HS or IDRIVEN_LS = 1110b
1900
IDRIVEN_HS or IDRIVEN_LS = 1111b
2000
IDRIVE = Tied to GND
100
IDRIVE = 18 kΩ ± 5% tied to GND
200
IDRIVE = 75 kΩ ± 5% tied to GND
300
IDRIVE = Hi-Z
600
IDRIVE = 75 kΩ ± 5% tied to DVDD
900
IDRIVE = 18 kΩ ± 5% tied to DVDD
1400
IDRIVE = Tied to DVDD
2000
Source current after tDRIVE
MAX
UNIT
mA
50
IHOLD
Gate holding current
ISTRONG
Gate strong pulldown current
GHx to SHx and GLx to SPx/SLx
2
A
ROFF
Gate hold off resistor
GHx to SHx and GLx to SPx/SLx
150
kΩ
Sink current after tDRIVE
mA
100
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
SPI Device
GCSA
Amplifier gain
H/W Device
CSA_GAIN = 00b
4.85
5
5.15
CSA_GAIN = 01b
9.7
10
10.3
CSA_GAIN = 10b
19.4
20
20.6
CSA_GAIN = 11b
38.8
40
41.2
GAIN = Tied to GND
4.85
5
5.15
GAIN = 47 kΩ ± 5% tied to GND
9.7
10
10.3
GAIN = Hi-Z
19.4
20
20.6
GAIN = Tied to DVDD
38.8
40
41.2
VO_STEP = 0.5 V, GCSA = 5 V/V
250
VO_STEP = 0.5 V, GCSA = 10 V/V
500
VO_STEP = 0.5 V, GVSA = 20 V/V
1000
tSET
Settling time to ±1%
VCOM
Common mode input range
VDIFF
Differential mode input range
VOFF
Input offset error
VSP = VSN = 0 V
VDRIFT
Drift offset
VSP = VSN = 0 V
VO_STEP = 0.5 V, GCSA = 40 V/V
VLINEAR
14
ns
2000
–0.15
0.15
–0.3
0.3
–3
3
10
SOx output voltage linear range
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V/V
0.25
V
V
mV
µV/°C
VVREF –
0.25
V
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: DRV8350 DRV8350R DRV8353 DRV8353R
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DRV8353, DRV8353R
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SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VSP = VSN = 0 V, VREF_DIV = 0b
VSP = VSN = 0 V, VREF_DIV = 1b
VVREF /
2
VSP = VSN = 0 V
VVREF /
2
SPI Device
VBIAS
SOx output voltage bias
H/W Device
TYP
VVREF –
0.3
MAX
UNIT
V
IBIAS
SPx/SNx input bias current
VSLEW
SOx output slew rate
60-pF load
10
IVREF
VREF input current
VVREF = 5 V
1.5
DRV835x: 60-pF load
10
MHz
1
MHz
UGB
Unity gain bandwidth
250
DRV835xR: 60-pF load
µA
V/µs
2.5
mA
PROTECTION CIRCUITS
DRV835x: VM falling, UVLO report
8.0
8.3
8.8
DRV835x: VM rising, UVLO recovery
8.2
8.5
9.0
DRV835xR: VM falling, UVLO report
8.0
8.3
8.6
DRV835xR: VM rising, UVLO recovery
8.2
8.5
8.8
VVM_UV
VM undervoltage lockout
VVM_UVH
VM undervoltage hysteresis
Rising to falling threshold
tVM_UVD
VM undervoltage deglitch time
VM falling, UVLO report
200
µs
6.1
6.4
6.8
DRV835x: VDRAIN rising, UVLO recovery
6.3
6.6
7.0
DRV835xR: VDRAIN falling, UVLO report
6.1
6.4
6.7
DRV835xR: VDRAIN rising, UVLO recovery
6.3
6.6
6.9
VDRAIN undervoltage lockout
VVDR_UVH
VDRAIN undervoltage hysteresis
Rising to falling threshold
tVDR_UVD
VDRAIN undervoltage deglitch time
VDRAIN falling, UVLO report
VVCP_UV
VCP charge pump undervoltage lockout
VCP falling, GDUV report
VVGLS_UV
VGLS low-side regulator undervoltage
lockout
VGLS falling, GDUV report
VGS_CLAMP
High-side gate clamp
Positive clamping voltage
12.5
Negative clamping voltage
Copyright © 2018–2019, Texas Instruments Incorporated
mV
10
DRV835x: VDRAIN falling, UVLO report
VVDR_UV
V
200
mV
10
µs
VDRAIN
+5
V
4.25
V
13.5
16
–0.7
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V
V
15
DRV8350, DRV8350R
DRV8353, DRV8353R
SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
www.ti.com
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPI Device
VVDS_OCP
VDS overcurrent
trip voltage
MIN
TYP
MAX
DRV835x: VDS_LVL = 0000b
0.041
0.06
0.072
DRV835x: VDS_LVL = 0001b
0.051
0.07
0.084
DRV835x: VDS_LVL = 0010b
0.061
0.08
0.096
DRV835x: VDS_LVL = 0011b
0.071
0.09
0.108
DRV835x: VDS_LVL = 0100b
0.081
0.1
0.115
DRV835xR: VDS_LVL = 0000b
0.048
0.06
0.072
DRV835xR: VDS_LVL = 0001b
0.056
0.07
0.084
DRV835xR: VDS_LVL = 0010b
0.064
0.08
0.096
DRV835xR: VDS_LVL = 0011b
0.072
0.09
0.108
DRV835xR: VDS_LVL = 0100b
0.085
0.1
0.115
VDS_LVL = 0101b
0.18
0.2
0.22
VDS_LVL = 0110b
0.27
0.3
0.33
VDS_LVL = 0111b
0.36
0.4
0.44
VDS_LVL = 1000b
0.45
0.5
0.55
VDS_LVL = 1001b
0.54
0.6
0.66
VDS_LVL = 1010b
0.63
0.7
0.77
VDS_LVL = 1011b
0.72
0.8
0.88
VDS_LVL = 1100b
0.81
0.9
0.99
VDS_LVL = 1101b
0.9
1.0
1.1
VDS_LVL = 1110b
1.35
1.5
1.65
VDS_LVL = 1111b
H/W Device
1.8
2
2.2
DRV835x: VDS = Tied to GND
0.041
0.06
0.072
DRV835x: VDS = 18 kΩ ± 5% tied to GND
0.081
0.1
0.115
DRV835xR: VDS = Tied to GND
0.048
0.06
0.072
DRV835xR: VDS = 18 kΩ ± 5% tied to GND
0.085
0.1
0.115
VDS = 75 kΩ ± 5% tied to GND
0.18
0.2
0.22
VDS = Hi-Z
0.36
0.4
0.44
VDS = 75 kΩ ± 5% tied to DVDD
0.63
0.7
0.77
VDS = 18 kΩ ± 5% tied to DVDD
0.9
1
1.1
VDS = Tied to DVDD
VDS and VSENSE
overcurrent deglitch time
tOCP_DEG
SPI Device
OCP_DEG = 00b
1
OCP_DEG = 01b
2
OCP_DEG = 10b
4
OCP_DEG = 11b
8
SPI Device
Overcurrent retry time
SPI Device
µs
0.25
SEN_LVL = 01b
0.5
SEN_LVL = 10b
0.75
SEN_LVL = 11b
1
H/W Device
tRETRY
V
4
SEN_LVL = 00b
VSENSE overcurrent trip
voltage
V
Disabled
H/W Device
VSEN_OCP
UNIT
V
1
TRETRY = 0b
8
TRETRY = 1b
50
μs
8
ms
H/W Device
ms
TOTW
Thermal warning temperature
Die temperature, TJ
130
150
170
°C
TOTSD
Thermal shutdown temperature
Die temperature, TJ
150
170
190
°C
THYS
Thermal hysteresis
Die temperature, TJ
20
°C
BUCK REGULATOR VCC
VVCC_REG
VCC regulator voltage
VVCC_BYT
VCC bypass threshold
16
6.6
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7
7.4
V
VVIN = 6 to 8.5 V
100
mV
VVIN increasing
8.5
V
Copyright © 2018–2019, Texas Instruments Incorporated
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SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
Electrical Characteristics (continued)
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
VVCC_BYH
VVCC_OUT
TEST CONDITIONS
MIN
VCC bypass hysteresis
VCC output impedance
TYP
MAX
UNIT
300
mV
VVIN = 6 V
100
Ω
VVIN = 10 V
8.8
Ω
VVIN = 48 V
0.8
Ω
9.2
mA
VVCC_LIM
VCC current limit
VVCC_UV
VCC undervoltage lockout
5.3
V
VVCC_UVH
VCC undervoltage lockout hysteresis
190
mV
VVCC_UVFD
VCC filter delay
3
μs
IIN_OP
IIN operating current
FB = 3 V
550
750
μA
IIN_OP
IIN shutdown current
RT/SD = 0 V
110
176
μA
1.25
2.57
Ω
3.8
4.8
V
BUCK REGULATOR SWITCHING
RDS(on)
Buck switch RDS(on)
ITEST = 200 mA
VGATE_UV
Gate drive undervoltage lockout
VBST - VSW rising
VGATE_UVH
Gate drive undervoltage lockout
hysteresis
VSWITCH
Pre-charge switch voltage
tON
Pre-charge switch on-time
2.8
490
At 1 mA
mV
0.8
V
150
ns
BUCK REGULATOR CURRENT LIMIT
ILIMIT
Current limit threshold
tLIM
Current limit response time
ISW overdrive = 0.1 A, time to switch off
0.41
tOFF1
Off time generator
FB = 0 V, RCL = 100 kΩ
tOFF2
Off time generator
FB = 2.3 V, RCL = 100 kΩ
0.51
0.61
A
350
ns
35
μs
2.56
μs
BUCK REGULATOR ON TIME GENERATOR
tON1
Ton 1
VVIN = 10 V, RON = 200 kΩ
2.15
2.77
3.5
μs
tON2
Ton 2
VVIN = 95 V, RON = 200 kΩ
200
300
420
μs
VSDT
Remote shutdown threshold
Rising
0.4
0.7
1.05
VSDH
Remote shutdown hysteresis
V
35
mV
300
ns
BUCK REGULATOR MINIMUM OFF TIME
tOFF_MIN
Minimum off time
FB = 0 V
BUCK REGULATOR REGULATIONS AND OV COMPARATORS
VFB
FB reference threshold
Internal reference, trip point for switch on
VFB_OV
FB overvoltage threshold
Trip point for switch off
IFB_BIAS
FB bias current
2.445
2.5
2.55
V
2.875
V
100
μA
BUCK REGULATOR THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
165
°C
TSDH
Thermal shutdown hysteresis
25
°C
Copyright © 2018–2019, Texas Instruments Incorporated
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7.6 SPI Timing Requirements
at TA = –40°C to +125°C, VVM = 9 to 75 V (unless otherwise noted)
MIN
tREADY
SPI ready after enable
tCLK
SCLK minimum period
tCLKH
NOM
MAX
VM > UVLO, ENABLE = 3.3 V
1
UNIT
ms
100
ns
SCLK minimum high time
50
ns
tCLKL
SCLK minimum low time
50
ns
tSU_SDI
SDI input data setup time
20
ns
tH_SDI
SDI input data hold time
30
tD_SDO
SDO output data delay time
tSU_nSCS
nSCS input setup time
50
ns
tH_nSCS
nSCS input hold time
50
ns
tHI_nSCS
nSCS minimum high time before active low
400
ns
tDIS_nSCS
nSCS disable time
tHI_nSCS
ns
SCLK high to SDO valid
30
nSCS high to SDO high impedance
ns
10
tSU_nSCS
ns
tH_nSCS
nSCS
tCLK
SCLK
tCLKH
SDI
X
tCLKL
MSB
LSB
X
tSU_SDI tH_SDI
SDO
Z
MSB
LSB
tD_SDO
Z
tDIS_nSCS
Figure 1. SPI Slave Mode Timing Diagram
18
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SLVSDY6A – AUGUST 2018 – REVISED JUNE 2019
7.7 Typical Characteristics
2
10
TA = 40°C
TA = 25°C
TA = 125°C
1.95
1.9
Supply Current (mA)
Operating Current (mA)
9.5
9
8.5
8
1.85
1.8
1.75
1.7
1.65
1.6
7.5
TA = 40°C
TA = 25°C
TA = 125°C
1.55
7
1.5
0
10
20
30
40
50
Supply Voltage (V)
60
70
80
0
VVM = VVDRAIN
Figure 2. VM Supply Current Over Supply Voltage
30
40
50
60
70
Supply Voltage (V)
80
90
100
D002
Figure 3. VDRAIN Supply Current Over Supply Voltage
40
TA = 40°C
TA = 25°C
TA = 125°C
VSUP = 9 V
VSUP = 48 V
VSUP = 100 V
35
Sleep Current (PA)
35
Sleep Current (PA)
20
VVM = VVDRAIN
40
30
25
20
30
25
20
15
15
10
-40
10
0
10
20
30
40
50
60
70
Supply Voltage (V)
80
90
100
-20
0
D003
20
40
60
80
Temperature (qC)
100
120
140
D004
IVM + IVDRAIN
IVM + IVDRAIN
Figure 5. Sleep Current Over Temperature
Figure 4. Sleep Current Over Supply Voltage
11
15.5
TA = 40qC
TA = 25qC
TA = 125qC
10.9
10.8
TA = 40qC
TA = 25qC
TA = 125qC
15.4
15.3
10.7
VGLS Voltage (V)
VCP Voltage (V)
10
D001
10.6
10.5
10.4
10.3
10.2
15.2
15.1
15
14.9
14.8
14.7
10.1
14.6
10
14.5
0
5
10
15
VCP Load Current (mA)
20
VVM = 48-V
25
0
5
D005
10
15
VGLS Load Current (mA)
20
25
D006
VVM = 48-V
Figure 6. VCP Voltage Over Load
Copyright © 2018–2019, Texas Instruments Incorporated
Figure 7. VGLS Voltage Over Load Current
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www.ti.com
Typical Characteristics (continued)
11
16
TA = 40qC
TA = 25qC
TA = 125qC
10.9
15.6
10.7
VGLS Voltage (V)
VCP Voltage (V)
10.8
TA = 40qC
TA = 25qC
TA = 125qC
15.8
10.6
10.5
10.4
10.3
15.4
15.2
15
14.8
14.6
10.2
14.4
10.1
14.2
10
14
0
5
10
15
VCP Load Current (mA)
20
25
0
VVM = 15-V
Figure 8. VCP Voltage Over Load Current
25
D008
Figure 9. VGLS Voltage Over Load Current
TA = 40qC
TA = 25qC
TA = 25qC
10.6
TA = 40qC
TA = 25qC
TA = 125qC
12.8
12.6
10.4
VGLS Voltage (V)
VCP Voltage (V)
20
13
10.8
10.2
10
9.8
9.6
12.4
12.2
12
11.8
11.6
9.4
11.4
9.2
11.2
9
11
0
5
10
15
VCP Load Current (mA)
20
0
5
D009
VVM = 12-V
10
15
VGLS Load Current (mA)
20
D010
VVM = 12-V
Figure 10. VCP Voltage Over Load Current
Figure 11. VGLS Voltage Over Load Current
9
10
TA = 40qC
TA = 25qC
TA = 125qC
8.8
8.6
TA = 40qC
TA = 25qC
TA = 125qC
9.8
9.6
8.4
VGLS Voltage (V)
VCP Voltage (V)
10
15
VGLS Load Current (mA)
VVM = 15-V
11
8.2
8
7.8
7.6
9.4
9.2
9
8.8
8.6
7.4
8.4
7.2
8.2
7
8
0
2
4
6
VCP Load Current (mA)
8
VVM = 9-V
10
0
2
D011
4
6
VGLS Load Current (mA)
8
10
D012
VVM = 9-V
Figure 12. VCP Voltage Over Load Current
20
5
D007
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Figure 13. VGLS Voltage Over Load Current
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8 Detailed Description
8.1 Overview
The DRV835x family of devices are integrated 100-V gate drivers for three-phase motor drive applications.
These devices decrease system component count, cost, and complexity by integrating three independent halfbridge gate drivers, charge pump and linear regulator for the high-side and low-side gate driver supply voltages,
optional triple current shunt amplifiers, and an optional 350-mA buck regulator. A standard serial peripheral
interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic
information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring
the most commonly used settings through fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A
source, 2-A sink peak currents with a 25-mA average output current. The high-side gate drive supply voltage is
generated using a doubler charge-pump architecture that regulates the VCP output to VVDRAIN + 10.5-V. The lowside gate drive supply voltage is generated using a linear regulator from the VM power supply that regulates the
VGLS output to 14.5-V. The VGLS supply is further regulated to 11-V on the GLx low-side gate driver outputs. A
smart gate-drive architecture provides the ability to dynamically adjust the output gate-drive current strength
allowing for the gate driver to control the power MOSFET VDS switching speed. This allows for the removal of
external gate drive resistors and diodes reducing BOM component count, cost, and PCB area. The architecture
also uses an internal state machine to protect against gate-drive short-circuit events, control the half-bridge dead
time, and protect against dV/dt parasitic turnon of the external power MOSFET.
The gate drivers can operate in either a single or dual supply architecture. In the single supply architecture, VM
can be tied to VDRAIN and is regulated to the correct supply voltages internally. In the dual supply architecture,
VM can be connected to a lower voltage supply from a more efficient switching regulator to improve the device
efficiency. VDRAIN stays connected to the external MOSFETs to set the correct charge pump and overcurrent
monitor reference.
The DRV8353 and DRV8353R devices integrate three, bidirectional current-shunt amplifiers for monitoring the
current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of the
shunt amplifier can be adjusted through the SPI or hardware interface with the SPI providing additional flexibility
to adjust the output bias point.
The DRV8350R and DRV8353R devices integrate a 350-mA buck regulator that can be used to power an
external controller or other logic circuits. The buck regulator is implemented as a separate internal die that can
use either the same or a different power supply from the gate driver.
In addition to the high level of device integration, the DRV835x family of devices provides a wide range of
integrated protection features. These features include power-supply undervoltage lockout (UVLO), gate drive
undervoltage lockout (GDUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and
overtemperature shutdown (OTW/OTSD). Fault events are indicated by the nFAULT pin with detailed information
available in the SPI registers on the SPI device version.
The DRV835x family of devices are available in 0.5-mm pin pitch, QFN surface-mount packages. The QFN sizes
are 5 × 5 mm for the 32-pin package, 6 × 6 mm for the 40-pin package, and 7 × 7 mm for the 48-pin package.
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8.2 Functional Block Diagram
VM
>10 …F
VM
VCP
VCP
GHA
HS
1 …F
CPH
VDRAIN
47 nF
VCP
Charge
Pump
SHA
VGLS
CPL
GLA
LS
VGLS
1 …F
VDRAIN
VDRAIN
0.1 …F
DVDD
1 …F
GND
VGLS
Linear
Regulator
SLA
Gate Driver
DVDD
Linear
Regulator
VDRAIN
VCP
GHB
HS
Power Supplies
SHB
ENABLE
VGLS
Digital
Core
INHA
GLB
LS
SLB
INLA
Gate Driver
INHB
VDRAIN
Smart Gate
Drive
INLB
Control
Inputs
INHC
VCP
GHC
HS
Protection
SHC
VGLS
INLC
GLC
LS
MODE
SLC
IDRIVE
Gate Driver
VDS
Fault Output
VCC
nFAULT
RPU
Figure 14. Block Diagram for DRV8350H
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Functional Block Diagram (continued)
VM
>10 …F
VM
VDRAIN
VDRAIN
0.1 …F
VCP
VCP
HS
1 …F
CPH
VDRAIN
VCP
Charge
Pump
SHA
VGLS
CPL
47 nF
LS
VGLS
1 …F
DVDD
1 …F
GND
GHA
VGLS
Linear
Regulator
GLA
SLA
Gate Driver
DVDD
Linear
Regulator
VDRAIN
VCP
HS
Power Supplies
GHB
SHB
ENABLE
VGLS
Digital
Core
INHA
LS
GLB
SLB
INLA
Gate Driver
INHB
Control
Inputs
INLB
VDRAIN
Smart Gate
Drive
VCP
HS
GHC
Protection
INHC
SHC
VGLS
INLC
LS
VCC
RPU
SDI
GLC
SLC
SPI
Gate Driver
VCC
SDO
SCLK
Fault Output
nFAULT
RPU
nSCS
Figure 15. Block Diagram for DRV8350S
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Functional Block Diagram (continued)
VM
>10 …F
VM
0.1 …F
VCP
VCP
GHA
HS
1 …F
CPH
VDRAIN
47 nF
VCP
Charge
Pump
SHA
VGLS
CPL
GLA
LS
VGLS
1 …F
VDRAIN
VDRAIN
DVDD
1 …F
GND
VGLS
Linear
Regulator
SLA
Gate Driver
DVDD
Linear
Regulator
VDRAIN
VCP
GHB
HS
Power Supplies
SHB
ENABLE
VGLS
Digital
Core
INHA
GLB
LS
SLB
INLA
Gate Driver
INHB
VDRAIN
Smart Gate
Drive
INLB
Control
Inputs
INHC
VCP
GHC
HS
Protection
SHC
VGLS
INLC
GLC
LS
MODE
SLC
IDRIVE
Gate Driver
VDS
Fault Output
VCC
VIN
BST
VIN
CIN
RRT/SD
RT/SD
SW
Buck Regulator
(LM5008A)
RCL
RRCL
nFAULT
RPU
0.01 µF
LOUT
350 mA
FB
VCC
GND
DOUT
RFB1
ROUT
COUT
RFB2
0.47 µF
Figure 16. Block Diagram for DRV8350RH
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Functional Block Diagram (continued)
VM
>10 …F
VM
VDRAIN
VDRAIN
0.1 …F
VCP
VCP
HS
1 …F
CPH
VDRAIN
VCP
Charge
Pump
SHA
VGLS
CPL
47 nF
LS
VGLS
1 …F
DVDD
1 …F
GND
GHA
VGLS
Linear
Regulator
GLA
SLA
Gate Driver
DVDD
Linear
Regulator
VDRAIN
VCP
HS
Power Supplies
GHB
SHB
ENABLE
VGLS
Digital
Core
INHA
LS
GLB
SLB
INLA
Gate Driver
INHB
Control
Inputs
INLB
VDRAIN
Smart Gate
Drive
VCP
HS
GHC
Protection
INHC
SHC
VGLS
INLC
LS
VCC
RPU
SDI
GLC
SLC
SPI
Gate Driver
SDO
SCLK
Fault Output
VCC
nFAULT
RPU
nSCS
VIN
BST
VIN
CIN
RRT/SD
RT/SD
SW
Buck Regulator
(LM5008A)
RCL
RRCL
LOUT
350 mA
FB
VCC
GND
0.01 µF
DOUT
RFB1
ROUT
COUT
RFB2
0.47 µF
Figure 17. Block Diagram for DRV8350RS
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Functional Block Diagram (continued)
VM
>10 …F
VM
0.1 …F
VCP
VCP
GHA
HS
1 …F
CPH
VDRAIN
47 nF
VCP
Charge
Pump
SHA
VGLS
CPL
GLA
LS
VGLS
1 …F
VDRAIN
VDRAIN
DVDD
1 …F
GND
VGLS
Linear
Regulator
SPA
Gate Driver
DVDD
Linear
Regulator
VDRAIN
VCP
GHB
HS
Power Supplies
SHB
ENABLE
VGLS
Digital
Core
INHA
GLB
LS
SPB
INLA
Gate Driver
INHB
VDRAIN
Smart Gate
Drive
INLB
VCP
GHC
HS
Control
Inputs
INHC
Protection
SHC
VGLS
INLC
GLC
LS
MODE
SPC
IDRIVE
Gate Driver
VDS
Fault Output
VCC
RPU
nFAULT
GAIN
VCC
SPC
VREF
AV
0.1 …F
SNC
RSENC
SOC
Output
Offset
Bias
SOB
SOA
SPB
AV
SNB
RSENB
SPA
AGND
AV
SNA
RSENA
Figure 18. Block Diagram for DRV8353H
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Functional Block Diagram (continued)
VM
>10 …F
VM
VDRAIN
VDRAIN
0.1 …F
VCP
VCP
GHA
HS
1 …F
CPH
VDRAIN
VCP
Charge
Pump
SHA
VGLS
CPL
47 nF
GLA
LS
VGLS
1 …F
DVDD
1 …F
GND
VGLS
Linear
Regulator
SPA
Gate Driver
DVDD
Linear
Regulator
VDRAIN
VCP
GHB
HS
Power Supplies
SHB
ENABLE
VGLS
Digital
Core
INHA
GLB
LS
SPB
INLA
Gate Driver
INHB
Control
Inputs
INLB
VDRAIN
Smart Gate
Drive
VCP
GHC
HS
Protection
INHC
SHC
VGLS
INLC
GLC
LS
VCC
RPU
SDI
SPC
SPI
Gate Driver
SDO
SCLK
Fault Output
VCC
RPU
nFAULT
nSCS
VCC
SPC
VREF
AV
0.1 …F
SNC
RSENC
SOC
SOB
SOA
Output
Offset
Bias
SPB
AV
SNB
RSENB
SPA
AGND
AV
SNA
RSENA
Figure 19. Block Diagram for DRV8353S
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Functional Block Diagram (continued)
VM
>10 …F
VM
0.1 …F
VCP
VCP
GHA
HS
1 …F
CPH
VDRAIN
47 nF
VCP
Charge
Pump
SHA
VGLS
CPL
GLA
LS
VGLS
1 …F
VDRAIN
VDRAIN
DVDD
1 …F
GND
VGLS
Linear
Regulator
SPA
Gate Driver
DVDD
Linear
Regulator
VDRAIN
VCP
GHB
HS
Power Supplies
SHB
ENABLE
VGLS
Digital
Core
INHA
GLB
LS
SPB
INLA
Gate Driver
INHB
VDRAIN
Smart Gate
Drive
INLB
VCP
GHC
HS
Control
Inputs
INHC
Protection
SHC
VGLS
INLC
GLC
LS
MODE
SPC
IDRIVE
Gate Driver
VDS
Fault Output
VCC
RPU
nFAULT
GAIN
VCC
SPC
VREF
AV
0.1 …F
SNC
RSENC
SOC
SPB
Output
Offset
Bias
SOB
SOA
AV
RSENB
SNB
SPA
AGND
AV
VIN
BST
VIN
CIN
RRT/SD
RT/SD
SW
Buck Regulator
(LM5008A)
RCL
RRCL
RSENA
SNA
0.01 µF
LOUT
350 mA
FB
VCC
GND
DOUT
RFB1
ROUT
COUT
RFB2
0.47 µF
Figure 20. Block Diagram for DRV8353RH
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Functional Block Diagram (continued)
VM
>10 …F
VM
VDRAIN
VDRAIN
0.1 …F
VCP
VCP
GHA
HS
1 …F
CPH
VDRAIN
VCP
Charge
Pump
SHA
VGLS
CPL
47 nF
GLA
LS
VGLS
1 …F
DVDD
1 …F
GND
VGLS
Linear
Regulator
SPA
Gate Driver
DVDD
Linear
Regulator
VDRAIN
VCP
GHB
HS
Power Supplies
SHB
ENABLE
VGLS
Digital
Core
INHA
GLB
LS
SPB
INLA
Gate Driver
INHB
Control
Inputs
INLB
VDRAIN
Smart Gate
Drive
VCP
GHC
HS
Protection
INHC
SHC
VGLS
INLC
GLC
LS
VCC
RPU
SDI
SPC
SPI
Gate Driver
SDO
SCLK
VCC
RPU
nFAULT
Fault Output
nSCS
VCC
SPC
VREF
AV
0.1 …F
SNC
RSENC
SOC
SOB
SOA
SPB
Output
Offset
Bias
AV
RSENB
SNB
SPA
AGND
AV
VIN
BST
VIN
CIN
RRT/SD
RT/SD
SW
Buck Regulator
(LM5008A)
RCL
RRCL
RSENA
SNA
0.01 µF
LOUT
350 mA
FB
VCC
GND
DOUT
RFB1
ROUT
COUT
RFB2
0.47 µF
Figure 21. Block Diagram for DRV8353RS
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8.3 Feature Description
8.3.1 Three Phase Smart Gate Drivers
The DRV835x family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. The VCP doubler charge pump provides the correct gate bias voltage to
the high-side MOSFET across a wide operating voltage range in addition to providing 100% duty-cycle support.
The internal VGLS linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-bridge
gate drivers can be used in combination to drive a three-phase motor or separately to drive other types of loads.
The DRV835x family of devices implement a smart gate-drive architecture which allows the user to dynamically
adjust the gate drive current without requiring external gate current limiting resistors. Additionally, this
architecture provides a variety of protection features for the external MOSFETs including automatic dead-time
insertion, parasitic dV/dt gate turnon prevention, and gate-fault detection.
8.3.1.1 PWM Control Modes
The DRV835x family of devices provides four different PWM control modes to support various commutation and
control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register
during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before making a MODE or
PWM_MODE change.
8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 1.
Table 1. 6x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
0
0
L
L
Hi-Z
0
1
L
H
H
1
0
H
L
L
1
1
L
L
Hi-Z
8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is
used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx
pins logic high. The corresponding INHx and INLx signals control the output state as listed in Table 2.
Table 2. 3x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
0
X
L
L
Hi-Z
1
0
H
L
L
1
1
L
H
H
8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
In this mode, the DRV835x family of devices uses 6-step block commutation tables that are stored internally.
This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple
controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the halfbridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital
outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode usually
operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling
rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction
of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the INHC pin
low if this feature is not required.
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The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this
feature is not required.
Table 3. Synchronous 1x PWM Mode
LOGIC AND HALL INPUTS
STATE
INHC = 0
GATE-DRIVE OUTPUTS
INHC = 1
PHASE A
INLA
INHB
INLB
INLA
INHB
INLB
GHA
PHASE B
GLA
GHB
PHASE C
GLB
GHC
GLC
DESCRIPTION
Stop
0
0
0
0
0
0
L
L
L
L
L
L
Stop
Align
1
1
1
1
1
1
PWM
!PWM
L
H
L
H
Align
1
1
1
0
0
0
1
L
L
PWM
!PWM
L
H
B→C
2
1
0
0
0
1
1
PWM
!PWM
L
L
L
H
A→C
3
1
0
1
0
1
0
PWM
!PWM
L
H
L
L
A→B
4
0
0
1
1
1
0
L
L
L
H
PWM
!PWM
C→B
5
0
1
1
1
0
0
L
H
L
L
PWM
!PWM
C→A
6
0
1
0
1
0
1
L
H
PWM
!PWM
L
L
B→A
Table 4. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)
LOGIC AND HALL INPUTS
STATE
INHC = 0
GATE-DRIVE OUTPUTS
INHC = 1
PHASE A
INLA
INHB
INLB
INLA
INHB
INLB
PHASE B
GHA
GLA
GHB
PHASE C
GLB
GHC
GLC
DESCRIPTION
Stop
0
0
0
0
0
0
L
L
L
L
L
L
Stop
Align
1
1
1
1
1
1
PWM
L
L
H
L
H
Align
1
1
1
0
0
0
1
L
L
PWM
L
L
H
B→C
2
1
0
0
0
1
1
PWM
L
L
L
L
H
A→C
3
1
0
1
0
1
0
PWM
L
L
H
L
L
A→B
4
0
0
1
1
1
0
L
L
L
H
PWM
L
C→B
5
0
1
1
1
0
0
L
H
L
L
PWM
L
C→A
6
0
1
0
1
0
1
L
H
PWM
L
L
L
B→A
Figure 22 and Figure 23 show the different possible configurations in 1x PWM mode.
MCU_PWM
MCU_GPIO
MCU_GPIO
INHA
INLA
INHB
INLB
MCU_GPIO
MCU_GPIO
MCU_GPIO
INHC
INLC
INHA
MCU_PWM
PWM
INLA
STATE0
INHB
STATE1
INLB
BLDC Motor
STATE2
INHC
MCU_GPIO
DIR
INLC
MCU_GPIO
PWM
H
STATE0
STATE1
H
BLDC Motor
STATE2
H
DIR
nBRAKE
nBRAKE
Figure 22. 1x PWM—Simple Controller
Figure 23. 1x PWM—Hall Sensor
8.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This
control mode allows for the external controller to bypass the internal dead-time handshake of the DRV835x or to
utilize the high-side and low-side drivers to drive separate high-side and low-side loads with each half-bridge.
These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side switches.
In this mode, If the system is configured in a half-bridge configuration, shoot-through occurs when the high-side
and low-side MOSFETs are turned on at the same time.
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Table 5. Independent PWM Mode Truth Table
INLx
INHx
GLx
GHx
0
0
L
L
0
1
L
H
1
0
H
L
1
1
H
H
Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using both of the
monitors is not possible if both the high-side and low-side gate drivers are being operated independently.
In this case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in
Figure 24.
Disable
VDS
+
±
VM
VDRAIN
VCP
GHx
HS
INHx
Load
SHx
VGLS
INLx
GLx
LS
Load
SLx/SPx
Gate Driver
Disable
VDS
+
±
Figure 24. Independent PWM High-Side and Low-Side Drivers
If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is
still possible. Connect the SHx pin as shown in Figure 25 or Figure 26. The unused gate driver and the
corresponding input can be left disconnected.
VDS
+
±
VDS
VM
+
±
VCP
VCP
INHx
GHx
HS
INHx
GHx
HS
VGLS
INLx
GLx
LS
Load
SLx/SPx
Gate Driver
VGLS
GLx
LS
SLx/SPx
Gate Driver
+
VDS ±
+
VDS ±
Figure 25. Single High-Side Driver
32
Load
SHx
SHx
INLx
VM
VDRAIN
VDRAIN
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Figure 26. Single Low-Side Driver
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8.3.1.2 Device Interface Modes
The DRV835x family of devices support two different interface modes (SPI and hardware) to allow the end
application to design for either flexibility or simplicity. The two interface modes share the same four pins, allowing
the different versions to be pin to pin compatible. This allows for application designers to evaluate with one
interface version and potentially switch to another with minimal modifications to their design.
8.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that allows for an external controller to send and receive
data with the DRV835x. This allows for the external controller to configure device settings and read detailed fault
information. The interface is a four wire interface utilizing the SCLK, SDI, SDO, and nSCS pins.
•
•
•
•
The SCLK pin is an input which accepts a clock signal to determine when data is captured and propagated on
SDI and SDO.
The SDI pin is the data input.
The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
resistor.
The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV835x.
For more information on the SPI, see the SPI Communication section.
8.3.1.2.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE,
MODE, and VDS. This allows for the application designer to configure the most commonly used device settings
by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement
for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT
pin.
•
•
•
•
The
The
The
The
GAIN pin configures the current shunt amplifier gain.
IDRIVE pin configures the gate drive current strength.
MODE pin configures the PWM control mode.
VDS pin configures the voltage threshold of the VDS overcurrent monitors.
For more information on the hardware interface, see the Pin Diagrams section.
DVDD
RGAIN
SCLK
SPI
Interface
DVDD
GAIN
DVDD
Hardware
Interface
DVDD
IDRIVE
SDI
DVDD
VCC
RPU
MODE
SDO
DVDD
VDS
nSCS
RVDS
Figure 27. SPI
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8.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations
The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM and
VDRAIN voltage supply inputs. The charge pump allows the gate driver to correctly bias the high-side MOSFET
gate with respect to the source across a wide input supply voltage range. The charge pump is regulated to keep
a fixed output voltage of VVDRAIN + 10.5 V and supports an average output current of 25 mA. When VVM is less
than 12 V, the charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V with respect to
VVDRAIN when unloaded. The charge pump is continuously monitored for undervoltage to prevent under-driven
MOSFET conditions.
The charge pump requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VDRAIN and VCP pins to
act as the storage capacitor. Additionally, a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor is required
between the CPH and CPL pins to act as the flying capacitor.
VDRAIN
VDRAIN
1 …F
VCP
CPH
VM
47 nF
Charge
Pump
Control
CPL
Figure 29. Charge Pump Architecture
The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply
input. The VGLS linear regulator allows the gate driver to correctly bias the low-side MOSFET gate with respect
to ground. The VGLS linear regulator output is fixed at 14.5 V and further regulated to 11-V on the GLx outputs
during operation. The VGLS regulator supports an output current of 25 mA. The VGLS linear regulator is
monitored for undervoltage to prevent under driver MOSFET conditions. The VGLS linear regulator requires a
X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND.
Since the charge pump output is regulated to VVDRAIN + 10.5 V this allows for VM to be supplied either directly
from the high voltage motor supply (up to 75 V) to support a single supply system or from a low voltage gate
driver power supply derived from a switching or linear regulator to improve the device efficiency or utilize an
externally available power supply. On the DRV8350R and DRV8353R devices the integrated buck regulator can
be used to create the efficient low voltage supply for VM without the need for an additional regulator. Figure 30
and Figure 31 show examples of the DRV835x configured in either single supply or dual supply configuration.
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48-V
Power
Supply
48-V
Power
Supply
48-V to 15-V
DC/DC
VM
VDRAIN
VM
VDRAIN
DRV835x
Power
MOSFETs
Figure 30. Single Supply Example
DRV835x
Power
MOSFETs
Figure 31. Dual Supply Example
8.3.1.4 Smart Gate Drive Architecture
The DRV835x gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and lowside drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external
power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between
efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE
which are detailed in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive
Control section. Figure 32 shows the high-level functional block diagram of the gate driver.
The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters
of the external power MOSFET used in the system and the desired rise and fall times (see the Application and
Implementation section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.
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VCP
INHx
INLx
VDRAIN
Control
Inputs
GHx
Level
Shifters
150 k
SHx
VGS
+
±
VGLS
Digital
Core
GLx
Level
Shifters
150 k
SLx/SPx
VGS
+
±
Figure 32. Gate Driver Block Diagram
8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
The IDRIVE component implements adjustable gate-drive current to control the MOSFET VDS slew rates. The
MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode
recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to parasitics
in the external half-bridge. IDRIVE operates on the principal that the MOSFET VDS slew rates are predominately
determined by the rate of gate charge (or gate current) delivered during the MOSFET QGD or Miller charging
region. By allowing the gate driver to adjust the gate current, it can effectively control the slew rate of the external
power MOSFETs.
IDRIVE allows the DRV835x family of devices to dynamically switch between gate drive currents either through a
register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI devices provide 16
IDRIVE settings ranging between 50-mA to 1-A source and 100-mA to 2-A sink. Hardware interface devices
provides 7 IDRIVE settings between the same ranges. The gate drive current setting is delivered to the gate during
the turnon and turnoff of the external power MOSFET for the tDRIVE duration. After the MOSFET turnon or turnoff,
the gate driver switches to a smaller hold IHOLD current to improve the gate driver efficiency. Additional details on
the IDRIVE settings are described in the Register Maps section for the SPI devices and in the Pin Diagrams
section for the hardware interface devices.
8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate-drive state machine that provides automatic dead time insertion
through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.
The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is period of time
between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross
conduct and cause shoot-through. The DRV835x family of devices use VGS voltage monitors to measure the
MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time value.
This feature allows the gate-driver dead time to adjust for variation in the system such a temperature drift and
variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is adjustable
through the registers on SPI devices.
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The automatic dead-time insertion has a limitation when the gate driver is transitioning from high-side MOSFET
on to low-side MOSFET on when the phase current is coming into the external half-bridge. In this case, the highside diode will conduct during the dead-time and hold up the switch-node voltage to VDRAIN. In this case, an
additional delay of approximately 100-200 ns is introduced into the dead-time handshake. This is introduced due
to the need to discharge the voltage present on the internal VGS detection circuit.
The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state
machine enables a strong pulldown ISTRONG current on the opposite MOSFET gate whenever a MOSFET is
switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic charge that
couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET
gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair
of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a
command to change the state of the half-bridge it starts to monitor the gate voltage of the external MOSFET. If at
the end of the tDRIVE period the VGS voltage has not reached the correct threshold the gate driver will report a
fault. To make sure that a false fault is not detected, a tDRIVE time should be selected that is longer than the time
required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the PWM time and will
terminate if another PWM command is received while active. Additional details on the TDRIVE settings are
described in the Register Maps section for SPI devices and in the Pin Diagrams section for hardware interface
devices.
Figure 33 shows an example of the TDRIVE state machine in operation.
VINHx
VINLx
VGHx
tDEAD
IHOLD
IDRIVE
tDEAD
IHOLD
IHOLD
ISTRONG
IGHx
IDRIVE
tDRIVE
IHOLD
tDRIVE
VGLx
tDEAD
tDEAD
IHOLD
IDRIVE
IHOLD
ISTRONG
IHOLD
IGLx
IDRIVE
tDRIVE
IHOLD
tDRIVE
Figure 33. TDRIVE State Machine
8.3.1.4.3 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,
and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.
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8.3.1.4.4 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the
device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three
current-shunt amplifiers (DRV8353 and DRV8353R), the low-side VDS monitors measure the voltage between the
SHx and SPx pins. If the current shunt amplifier is unused, tie the SP pins to the common ground point of the
external half-bridges. On device options without the current shunt amplifiers (DRV8350 and DRV8350R) the lowside VDS monitor measures between the SHx and SLx pins.
For the SPI devices, the low-side VDS monitor reference point can be changed between the SPx and SNx pins if
desired with the LS_REF register setting. This is only for the low-side VDS monitor. The high-side VDS monitor
stays between the VDRAIN and SHx pins.
The VVDS_OCP threshold is programmable between 0.06 V and 2 V on SPI device and between 0.06 V and 1 V on
hardware interface devices. Additional information on the VDS monitor levels are described in the Register Maps
section for SPI devices and in the Pin Diagrams section hardware interface device.
VDRAIN
VDRAIN
VDS
VDS
+
±
+
±
VDS
VVDS_OCP
VDS
VVDS_OCP
VDRAIN
+
±
VDS
+
±
GHx
+
VDS
±
VVDS_OCP
SHx
+
±
VDS
GLx
+
±
VDRAIN
VDS
VVDS_OCP
GHx
SHx
+
±
GLx
SPx
SLx
0
1
Figure 34. DRV8350 and DRV8350R VDS Monitors
SNx
RSENSE
LS_REF
(SPI Only)
Figure 35. DRV8353 and DRV8353R VDS Monitors
8.3.1.4.5 VDRAIN Sense and Reference Pin
The DRV835x family of devices provides a separate sense and reference pin for the common point of the highside MOSFET drain. This pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors
(VDRAIN) and the power supply (VM) to stay separate and prevent noise on the VDRAIN sense line.
The VDRAIN pin serves as the reference point for the integrated charge pump. This makes sure that the charge
pump reference stays with respect to the power MOSFET supply through voltage transient conditions.
Since the charge pump is referenced to VDRAIN, this also allows for VM to supplied either directed from the
power MOSFET supply (VDRAIN) or from an independent supply. This allows for a configuration where VM can
be supplied from an efficient low voltage supply to increase the device efficiency. On the DRV8350R and
DRV8353R devices, the integrated buck regulator can be used to create the efficient low voltage supply.
8.3.2 DVDD Linear Voltage Regulator
A 5-V, 10-mA linear regulator is integrated into the DRV835x family of devices and is available for use by
external circuitry. This regulator can provide the supply voltage for low-current supporting circuitry. The output of
the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor
routed directly back to the adjacent DGND or GND ground pin.
The DVDD nominal, no-load output voltage is 5 V. When the DVDD load current exceeds 10 mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than 10
mA.
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VM
REF
+
±
DVDD
5 V, 10 mA
GND/
DGND
1 …F
Figure 36. DVDD Linear Regulator Block Diagram
Use Equation 1 to calculate the power dissipated in the device because of the DVDD linear regulator.
P
VVM VDVDD u IDVDD
(1)
For example, at VVM = 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in Equation 2.
P 24 V 3.3 V u 20 mA 414 mW
(2)
8.3.3 Pin Diagrams
Figure 37 shows the input structure for the logic-level pins, INHx, INLx, ENABLE, nSCS, SCLK, and SDI.
DVDD
STATE
RESISTANCE
INPUT
VIH
Tied to DVDD
Logic High
VIL
Tied to AGND
Logic Low
100 k
Figure 37. Logic-Level Input Pin Structure
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Figure 38 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices. The
input can be set with an external resistor.
MODE
GAIN
Independent
40 V/V
1x PWM
20V/V
3x PWM
10 V/V
6x PWM
5 V/V
DVDD
STATE
RESISTANCE
DVDD
+
VI4
Tied to DVDD
VI3
Hi-Z (>500 kŸ WR
AGND)
VI2
47 NŸ “5%
to AGND
VI1
Tied to AGND
50 k
84 k
±
+
±
+
±
Figure 38. Four Level Input Pin Structure
Figure 39 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices.
The input can be set with an external resistor.
IDRIVE
VDS
1/2 A
Disabled
700/1400 mA
1V
450/900 mA
0.7 V
300/600 mA
0.4 V
150/300 mA
0.2 V
100/200 mA
0.1 V
50/100 mA
0.06 V
+
STATE
RESISTANCE
VI7
Tied to DVDD
VI6
18 k ± 5%
to DVDD
VI5
75 k ± 5%
to DVDD
VI4
Hi-Z (>500 kŸ
to AGND)
VI3
75 k ± 5%
to AGND
VI2
18 NŸ “5%
to AGND
VI1
±
DVDD
DVDD
+
±
73 k
+
±
73 k
+
±
+
Tied to AGND
±
+
±
Figure 39. Seven Level Input Pin Structure
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Figure 40 shows the structure of the open-drain output pins nFAULT and SDO. The open-drain output requires
an external pullup resistor to function correctly.
DVDD
RPU
STATE
STATUS
No Fault
Inactive
OUTPUT
Fault
Active
Active
Inactive
Figure 40. Open-Drain Output Pin Structure
8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)
The DRV8353 and DRV8353R integrate three, high-performance low-side current-shunt amplifiers for current
measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are
commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with
the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one
amplifier can be used to sense the sum of the half-bridge legs. The current shunt amplifiers include features such
as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference pin
(VREF).
8.3.4.1 Bidirectional Current Sense Operation
The SOx pin on the DRV8353 and DRV8353R outputs an analog voltage equal to the voltage across the SPx
and SNx pins multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels (5
V/V, 10 V/V, 20 V/V, and 40 V/V). Use Equation 3 to calculate the current through the shunt resistor.
VVREF
VSOx
2
I
GCSA u RSENSE
(3)
R2
R3
R4
R5
R6
SOx
I
R1
VCC
±
VREF
+
0.1 …F
R2
SPx
R1
RSENSE
SNx
½
+
R3
±
R4
R5
Figure 41. Bidirectional Current-Sense Configuration
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SO (V)
VREF
VVREF / 2
VLINEAR
SP ± SN (V)
Figure 42. Bidirectional Current-Sense Output
I
SP
SO
R
AV
SN
SO
VREF
SP ± SN
±0.3 V
VVREF ± 0.25 V
±I × R
VSO(range±)
VSO(off)max
VVREF / 2
VOFF,
VDRIFT
0V
VSO(off)min
VSO(range+)
0.25 V
I×R
0.3 V
0V
Figure 43. Bidirectional Current Sense Regions
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8.3.4.2 Unidirectional Current Sense Operation (SPI only)
On the DRV8353 and DRV8353R SPI devices, use the VREF_DIV bit to remove the VREF divider. In this case
the shunt amplifier operates unidirectionally and SOx outputs an analog voltage equal to the voltage across the
SPx and SNx pins multiplied by the gain setting (GCSA). Use Equation 4 to calculate the current through the shunt
resistor.
VVREF VSOx
I
GCSA u RSENSE
(4)
R2
R3
R4
R5
SOx
R6
I
R1
±
+
SPx
R1
RSENSE
SNx
VCC
R2
VREF
+
0.1 …F
R3
±
R4
R5
Figure 44. Unidirectional Current-Sense Configuration
SO (V)
VREF
VVREF ± 0.3 V
VLINEAR
SP ± SN (V)
Figure 45. Unidirectional Current-Sense Output
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I
SP
SO
R
AV
SN
SO
VREF
VVREF ± 0.25 V
VSO(off)max
SP ± SN
VOFF,
VVREF ± 0.3 V
0V
VDRIFT
VSO(off)min
VSO(range)
I×R
0.3 V
0.25 V
0V
Figure 46. Unidirectional Current-Sense Regions
8.3.4.3 Amplifier Calibration Modes
To minimize DC offset and drift over temperature, a DC calibration mode is provided and enabled through the
SPI register (CSA_CAL_X). This option is not available on hardware interface devices. When the calibration
setting is enabled the inputs to the amplifier are shorted and the load is disconnected. DC calibration can be
done at any time, even when the half-bridges are operating. For the best results, do the DC calibration during the
switching OFF period to decrease the potential noise impact to the amplifier. A diagram of the calibration mode is
shown below. When a CSA_CAL_X bit is enabled, the corresponding amplifier goes to the calibration mode.
RF
ROUT
SOx
RSP
!CAL
SP
RSN
!CAL
SN
VREF
+
CAL
RSENSE
CAL
RG
+
-
Figure 47. Amplifier Manual Calibration
In addition to the manual calibration method provided on the SPI devices versions, the DRV835x family of
devices provide an auto calibration feature on both the hardware and SPI device versions in order to minimize
the amplifier input offset after power up and during run time to account for temperature and device variation.
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Auto calibration occurs automatically on device power up for both the hardware and SPI device options. The
power up auto calibration starts immediately after the VREF pin crosses the minimum operational VREF voltage.
50 us should be allowed for the power up auto calibration routine to complete after the VREF pin voltage crosses
the minimum VREF operational voltage. The auto calibration functions by doing a trim routine of the amplifier to
minimize the amplifier input offset. After this the amplifiers are ready for normal operation.
For the SPI device options, auto calibration can also be done again during run time by enabling the AUTO_CAL
register setting. Auto calibration can then be commanded with the corresponding CSA_CAL_X register setting to
rerun the auto calibration routine. During auto calibration all of the amplifiers will be configured for the max gain
setting in order to improve the accuracy of the calibration routine.
8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
The current-sense amplifiers on the DRV8353 and DRV8353R SPI devices can be configured to amplify the
voltage across the external low-side MOSFET VDS. This allows for the external controller to measure the voltage
drop across the MOSFET RDS(on) without the shunt resistor and then calculate the half-bridge current level.
To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to
the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier
inputs. During this mode of operation, the SPx pins should stay connected to the source of the low-side MOSFET
as it serves as the reference for the low-side gate driver. When the CSA_FET bit is set to 1, the negative
reference for the low-side VDS monitor is automatically set to SNx, regardless of the state of the LS_REF bit
state. This setting is implemented to prevent disabling of the low-side VDS monitor.
If the system operates in MOSFET VDS sensing mode, route the SHx and SNx pins with Kelvin connections
across the drain and source of the external low-side MOSFETs.
VDRAIN
VDRAIN
VDRAIN
High-Side
High-Side
VCP
VDS Monitor
VDRAIN
VCP
VDS Monitor
+
VDS
±
+
VDS
±
GHx
GHx
(SPI only)
(SPI only)
CSA_FET = 0
CSA_FET = 1
SHx
LS_REF = 0
SHx
LS_REF = X
VGLS
Low-Side
Low-Side
VDS Monitor
VDS Monitor
+
VDS
±
GLx
VDS
VGLS
+
±
GLx
0
0
1
1
10 k
10 k
10 k
SPx
SOx
AV
RSEN
10 k
10 k
SNx
AV
GND
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SPx
SOx
SNx
Figure 48. Resistor Sense Configuration
10 k
GND
Figure 49. VDS Sense Configuration
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When operating in MOSFET VDS sense mode, the amplifier is enabled at the end of the tDRIVE time. At this time,
the amplifier input is connected to the SHx pin, and the SOx output is valid. When the low-side MOSFET
receives a signal to turn off, the amplifier inputs, SPx and SNx, are shorted together internally.
8.3.5 Step-Down Buck Regulator
The DRV8350R and DRV8353R have an integrated buck regulator (LM5008A) to supply power for an external
controller or system voltage rail.
The LM5008A regulator is an easy-to-use buck (step-down) DC-DC regulator that operates from 6-V to 95-V
supply voltage. The device is intended for step-down conversions from 12-V, 24-V, and 48-V unregulated, semiregulated and fully-regulated supply rails. With integrated buck power MOSFET, the LM5008A delivers up to
350-mA DC load current with exceptional efficiency and low input quiescent current in a very small solution size.
Designed for simple implementation, an almost fixed-frequency, constant on-time (COT) operation with
discontinuous conduction mode (DCM) at light loads is ideal for low-noise, high current, fast transient load
requirements. Control loop compensation is not required reducing design time and external component count.
The LM5008A incorporates other features for comprehensive system requirements, including VCC undervoltage
lockout (UVLO), gate drive undervoltage lockout, maximum duty cycle limiter, intelligent current limit off-timer, a
precharge switch, and thermal shutdown with automatic recovery. These features enable a flexible and easy-touse platform for a wide range of applications. The pin arrangement is designed for simple and optimized PCB
layout, requiring only a few external components.
For additional details and design information refer to the LM5008A 100-V 350-mA Constant On-Time Buck
Switching Regulator data sheet.
8.3.5.1 Functional Block Diagram
7 V Bias
Regulator
6 V to 95 V
Input
VIN
C5
C1
VCC
UVLO
VIN SENSE
Bypass
Switch
Q2
GND
Thermal
Shutdown
VCC
RT
C3
On Timer
± +
Start
0.7 V
RT
RT/SD
+
SHUTDOWN
Finish
BST
Over-Voltage
Comparator
±
2.875 V
Start
GD
UVLO
300 ns MIN
Off Timer
Level
Shift
±
RTN
+
RCL
+
Finish
Start
Current Limit
Off Timer
VOUT
D1
RCLR Q
Regulation
Comparator
FB
RCL
L1
SW
SSET Q
±
RCL
C4
Driver
Finish
2.5 V
FB
Vin
SD
0.51 A
Buck
Switch
Current
Sense
PreCharge
RFB2
RFB1
R3
C2
Figure 50. Functional Block Diagram
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8.3.5.2 Feature Description
8.3.5.2.1 Control Circuit Overview
The LM5008A is a Buck DC-DC regulator that uses a control scheme in which the on-time varies inversely with
line voltage (VIN). Control is based on a comparator and the on-time one-shot, with the output voltage feedback
(FB) compared to an internal reference (2.5 V). If the FB level is below the reference the buck switch is turned on
for a fixed time determined by the line voltage and a programming resistor (RT). Following the ON period, the
switch stays off for at least the minimum off-timer period of 300 ns. If FB is still below the reference at that time,
the switch turns on again for another on-time period. This continues until regulation is achieved.
The LM5008A operates in discontinuous conduction mode at light load currents, and continuous conduction
mode at heavy load current. In discontinuous conduction mode, current through the output inductor starts at zero
and ramps up to a peak during the on-time, then ramps back to zero before the end of the off-time. The next ontime period starts when the voltage at FB falls below the internal reference; until then, the inductor current stays
zero. In this mode, the operating frequency is lower than in continuous conduction mode and varies with load
current. Therefore, at light loads, the conversion efficiency is kept because the switching losses decrease with
the reduction in load and frequency. The discontinuous operating frequency can be calculated with Equation 5.
F
§ VOUT 2 u L u 1.04 u 1020 ·
¨
¸
¨
¸
RL u (R T )2
©
¹
where
•
RL = the load resistance
(5)
In continuous conduction mode, current flows continuously through the inductor and never ramps down to zero.
In this mode the operating frequency is greater than the discontinuous mode frequency and stays relatively
constant with load and line variations. The approximate continuous mode operating frequency can be calculated
with Equation 6.
§
·
VOUT
F ¨
¨ 1.385 u 10 10 u R ¸¸
T¹
©
(6)
The output voltage (VOUT) is programmed by two external resistors as shown in Figure 50. The regulation point
can be calculated with Equation 7.
VOUT = 2.5 × (RFB1 + RFB2) / RFB1
(7)
The LM5008A regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor C2. A minimum of 25 mV to 50 mV of ripple voltage at the feedback pin
(FB) is required for the LM5008A. In cases where the capacitor ESR is too small, additional series resistance
may be required (R3 in the Figure 50).
For applications where lower output voltage ripple is required, the output can be taken directly from a low-ESR
output capacitor as shown in Figure 51. However, R3 slightly degrades the load regulation.
SW
L1
RFB2
R3
FB
VOUT2
RFB1
C2
Figure 51. Low-Ripple Output Configuration
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8.3.5.2.2 Start-Up Regulator (VCC)
The high voltage bias regulator is integrated within the LM5008A. The input pin (VIN) can be connected directly
to line voltages between 6 V and 95 V, with transient capability to 100 V. Referring to the Figure 50, when VIN is
between 6 V and the bypass threshold (nominally 8.5 V), the bypass switch (Q2) is on, and VCC tracks VIN within
100 mV to 150 mV. The bypass switch on-resistance is approximately 100 Ω, with inherent current limiting at
approximately 100 mA. When VIN is above the bypass threshold Q2 is turned off, and VCC is regulated at 7 V.
The VCC regulator output current is limited at approximately 9.2 mA. When the LM5008A is shut down using the
RT/SD pin, the VCC bypass switch is shut off regardless of the voltage at VIN.
When VIN exceeds the bypass threshold, the time required for Q2 to shut off is approximately 2 µs to 3 µs. The
capacitor at VCC (C3) must be a minimum of 0.47 µF to prevent the voltage at VCC from rising above its absolute
maximum rating in response to a step input applied at VIN. C3 must be placed as near as possible to the VCC
and RTN pins. In applications with a relatively high input voltage, power dissipation in the bias regulator is a
concern. An auxiliary voltage of between 7.5 V and 14 V can be diode connected to the VCC pin to shut off the
VCC regulator, thereby reducing internal power dissipation. The current required into the VCC pin is shown in the
typical characteristics curves. Internally a diode connects VCC to VIN requiring that the auxiliary voltage be less
than VIN.
The turnon sequence is shown in Figure 52. During the initial delay (t1), VCC ramps up at a rate determined by
its current limit and C3 while internal circuitry stabilizes. When VCC reaches the upper threshold of its
undervoltage lockout (UVLO, typically 5.3 V), the buck switch is enabled. The inductor current increases to the
current limit threshold (ILIM), and during t2 the VOUT increases as the output capacitor charges up. When VOUT
reaches the intended voltage the average inductor current decreases (t3) to the nominal load current (IO).
VIN
t1
7V
UVLO
VCC
Vin
SW Pin
0V
ILIM
Inductor
Current
IO
t2
t3
VOUT
Figure 52. Start-Up Sequence
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8.3.5.2.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 2.5-V reference. In normal operation (the output voltage is
regulated), an on-time period is initiated when the voltage at FB falls below 2.5 V. The buck switch stays on for
the on-time, causing the FB voltage to rise above 2.5 V. After the on-time period, the buck switch stays off until
the FB voltage again falls below 2.5 V. During start-up, the FB voltage is below 2.5 V at the end of each on-time,
resulting in the minimum off-time of 300 ns. Bias current at the FB pin is nominally 100 nA.
8.3.5.2.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 2.875-V reference. If the voltage at FB rises above 2.875
V, the on-time pulse is immediately terminated. This condition can occur if the input voltage or the output load
change suddenly. The buck switch does not turn on again until the voltage at FB falls below 2.5 V.
8.3.5.2.5 On-Time Generator and Shutdown
The on-time for the LM5008A is determined by the RT resistor and is inversely proportional to the input voltage
(VIN), resulting in an almost constant frequency as Vin is varied over its range. The on-time equation for the
LM5008A is Equation 8.
TON = 1.385 × 10–10 × RT / VIN
(8)
RT must be selected for a minimum on-time (at maximum VIN) greater than 400 ns, for correct current limit
operation. This requirement limits the maximum frequency for each application, depending on VIN and VOUT.
The LM5008A can be remotely disabled by taking the RT/SD pin to ground. See Figure 53. The voltage at the
RT/SD pin is between 1.5 V and 3 V, depending on VIN and the value of the RT resistor.
Input
Voltage
VIN
RT
RT/SD
STOP
RUN
Figure 53. Shutdown Implementation
8.3.5.2.6 Current Limit
The LM5008A has an intelligent current limit OFF timer. If the current in the Buck switch exceeds 0.51 A the
present cycle is immediately terminated and a non-resetable OFF timer is initiated. The length of off-time is
controlled by an external resistor (RCL) and the FB voltage. When FB = 0 V, a maximum off-time is required, and
the time is preset to 35 µs. This condition occurs when the output is shorted and during the initial part of start-up.
This amount of time makes sure that safe short-circuit operation occurs up to the maximum input voltage of 95 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit), the current limit off-time is less
than 35 µs. Reducing the off-time during less severe overloads decreases the amount of foldback, recovery time,
and the start-up time. The off-time is calculated from Equation 9.
TOFF
§
¨
¨
¨
¨ 0.285
¨
©
10
5
VFB
6.35 u 10
6
u RCL
·
¸
¸
¸
¸
¸
¹
(9)
The current limit-sensing circuit is blanked for the first 50 ns to 70 ns of each on-time, so it is not falsely tripped
by the current surge which occurs at turnon. The current surge is required by the re-circulating diode (D1) for its
turnoff recovery.
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8.3.5.2.7 N-Channel Buck Switch and Driver
The LM5008A integrates an N-Channel Buck switch and associated floating high voltage gate driver. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.01µF ceramic capacitor (C4) connected between the BST pin and SW pin provides the voltage to the driver during
the on-time.
During each off-time, the SW pin is at approximately 0 V and the bootstrap capacitor charges from VCC through
the internal diode. The minimum off-timer, set to 300 ns, makes sure that a minimum time each cycle to recharge
the bootstrap capacitor.
The internal precharge switch at the SW pin is turned on for ≊ 150 ns during the minimum off-time period,
ensuring sufficient voltage exists across the bootstrap capacitor for the on-time. This feature helps prevent
operating problems which can occur during very light-load conditions, involving a long off-time, during which the
voltage across the bootstrap capacitor could otherwise decrease to less than the threshold for the gate drive
UVLO. The precharge switch also helps prevent start-up problems which can occur if the output voltage is
precharged prior to turnon. After current limit detection, the precharge switch is turned on for the entire duration
of the forced off-time.
8.3.5.2.8 Thermal Protection
The LM5008A must be operated so the junction temperature does not exceed 125°C during normal operation. An
internal Thermal Shutdown circuit is provided to shutdown the LM5008A in the event of a higher than normal
junction temperature. When activated, typically at 165°C, the controller is forced into a low-power reset state by
disabling the buck switch. This feature prevents catastrophic failures from accidental device overheating. When
the junction temperature decreases below 140°C (typical hysteresis = 25°C), normal operation continues.
8.3.6 Gate Driver Protective Circuits
The DRV835x family of devices are fully protected against VM undervoltage, charge pump and low-side regulator
undervoltage, MOSFET VDS overcurrent, gate driver shorts, and overtemperature events.
8.3.6.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls below the VVM_UV threshold or voltage on VDRAIN pin
falls below the VVDR_UV, all of the external MOSFETs are disabled, the charge pump is disabled, and the nFAULT
pin is driven low. The FAULT and UVLO bits are also latched high in the registers on SPI devices. Normal
operation continues (gate driver operation and the nFAULT pin is released) when the undervoltage condition is
removed. The UVLO bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).
VM supply or VDRAIN undervoltage may also lead to VCP charge pump or VGLS regulator undervoltage
conditions to report. This behavior is expected because the VCP and VGLS supply voltages are dependent on
VM and VDRAIN pin voltages.
8.3.6.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
If at any time the voltage on the VCP pin (charge pump) falls below the VVCP_UV threshold or voltage on the
VGLS pin falls below the VVGLS_UV threshold, all of the external MOSFETs are disabled and the nFAULT pin is
driven low. The FAULT and GDUV bits are also latched high in the registers on SPI devices. Normal operation
continues (gate-driver operation and the nFAULT pin is released) when the undervoltage condition is removed.
The GDUV bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the
DIS_GDUV bit high on the SPI devices disables this protection feature. On hardware interface devices, the
GDUV protection is always enabled.
8.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET RDS(on).
If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG deglitch
time, a VDS_OCP event is recognized and action is done according to the OCP_MODE. On hardware interface
devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4 µs, and the OCP_MODE is
configured for 8-ms automatic retry but can be disabled by tying the VDS pin to DVDD. On SPI devices, the
VVDS_OCP threshold is set through the VDS_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI
register, and the OCP_MODE bit can operate in four different modes: VDS latched shutdown, VDS automatic retry,
VDS report only, and VDS disabled.
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The MOSFET VDS overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled
on SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the
PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the VDS_OCP overcurrent
response between linked and individual shutdown modes. When OCP_ACT is 0, a VDS_OCP fault will only
effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a
VDS_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.
8.3.6.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation continues (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.2 VDS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation continues automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, VDS_OCP, and MOSFET OCP bits stay latched until the tRETRY period expires.
8.3.6.3.3 VDS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI
registers. The gate drivers continue to operate as normal. The external controller manages the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.4 VDS Disabled (OCP_MODE = 11b)
No action occurs after a VDS_OCP event in this mode.
8.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor
with the SP pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the VSEN_OCP
threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done
according to the OCP_MODE. On hardware interface devices, the VSENSE threshold is fixed at 1 V, tOCP_DEG is
fixed at 4 µs, and the OCP_MODE for VSENSE is fixed for 8-ms automatic retry. On SPI devices, the VSENSE
threshold is set through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and
the OCP_MODE bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry,
VSENSE report only, and VSENSE disabled.
The VSENSE overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled on
SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the
PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the SEN_OCP overcurrent
response between linked and individual shutdown modes. When OCP_ACT is 0, a SEN_OCP fault will only
effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a
SEN_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.
8.3.6.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation continues (gate driver
operation and the nFAULT pin is released) when the SEN_OCP condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
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8.3.6.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation continues automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT , SEN_OCP, and sense OCP bits stay latched until the tRETRY period expires.
8.3.6.4.3 VSENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition is removed and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the
VDS_OCP bit by using the DIS_SEN SPI register.
8.3.6.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or
decrease after the tDRIVE time, a gate driver fault is detected. This fault may be encountered if the GHx or GLx
pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the
selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate drive
fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the FAULT,
GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation continues (gate driver
operation and the nFAULT pin is released) when the gate driver fault condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). On SPI devices, setting the
DIS_GDF_UVLO bit high disables this protection feature.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external MOSFET
in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve gate driver faults in these cases.
Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported because of
the MOSFET gate not turning on.
8.3.6.6 Overcurrent Soft Shutdown (OCP Soft)
In the case of a MOSFET VDS or VSENSE overcurrent fault the driver uses a special shutdown sequence to protect
the driver and MOSFETs from large voltage switching transients. These large voltage transients can be created
when rapidly switching off the external MOSFETs when a large drain to source current is present, such as during
an overcurrent event.
To mitigate this issue, the DRV835x family of devices reduce the IDRIVEN pull down current setting for both the
high-side and low-side gate drivers during the MOSFET turn off in response to the fault event. If the programmed
IDRIVEN value is less than 1100 mA, the IDRIVEN value is set to the minimum IDRIVEN setting. If the programmed
IDRIVEN value is greater than or equal to 1100mA, the IDRIVEN value is reduced by seven code settings.
8.3.6.7 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers of
SPI devices. The device does no additional action and continues to function. When the die temperature falls
below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also be
configured to report on the nFAULT pin and FAULT bit by setting the OTW_REP bit to 1 through the SPI
registers.
52
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8.3.6.8 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits
are latched high. Normal operation continues (gate driver operation and the nFAULT pin is released) when the
overtemperature condition is removed. The TSD bit stays latched high indicating that a thermal event occurred
until a clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This
protection feature cannot be disabled.
8.3.6.9 Fault Response Table
Table 6. Fault Action and Response
FAULT
CONDITION
CONFIGURATION
REPORT
GATE DRIVER
RECOVERY
VM Undervoltage
(VM_UV)
VVM < VVM_UV
—
nFAULT
Hi-Z
Automatic:
VVM > VVM_UV
VDRAIN Undervoltage
(VDR_UV)
VVDRAIN < VVDR_UV
—
nFAULT
Hi-Z
Automatic:
VVM > VVDR_UV
Charge Pump Undervoltage
(VCP_UV)
DIS_GDUV = 0b
nFAULT
Hi-Z
VVCP < VVCP_UV
DIS_GDUV = 1b
None
Active
VGLS Regulator Undervoltage
(VGLS_UV)
DIS_GDUV = 0b
nFAULT
Hi-Z
VVGLS < VVGLS_UV
DIS_GDUV = 1b
None
Active
OCP_MODE = 00b
nFAULT
Hi-Z
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 01b
nFAULT
Hi-Z
Retry:
tRETRY
OCP_MODE = 10b
nFAULT
Active
No action
OCP_MODE = 11b
None
Active
No action
OCP_MODE = 00b
nFAULT
Hi-Z
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 01b
nFAULT
Hi-Z
Retry:
tRETRY
VDS Overcurrent
(VDS_OCP)
VSENSE Overcurrent
(SEN_OCP)
Gate Driver Fault
(GDF)
Thermal Warning
(OTW)
Thermal Shutdown
(OTSD)
VDS > VVDS_OCP
VSP > VSEN_OCP
Automatic:
VVGLS > VVGLS_UV
OCP_MODE = 10b
nFAULT
Active
No action
OCP_MODE = 11b or
DIS_SEN = 1b
None
Active
No action
DIS_GDF = 0b
nFAULT
Hi-Z
Latched:
CLR_FLT, ENABLE Pulse
DIS_GDF = 1b
None
Active
No action
Automatic:
TJ < TOTW – THYS
VGS Stuck > tDRIVE
OTW_REP = 1b
nFAULT
Active
OTW_REP = 0b
None
Active
No action
Hi-Z
Automatic:
TJ < TOTSD – THYS
TJ > TOTW
TJ > TOTSD
Automatic:
VVCP > VVCP_UV
—
nFAULT
8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV835x family of devices. When the ENABLE pin is low, the device
goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are
disabled, the VCP charge pump and VGLS regulator are disabled, the DVDD regulator is disabled, the sense
amplifiers are disabled, and the SPI bus is disabled. In sleep mode all the device registers will reset to their
default values. The tSLEEP time must elapse after a falling edge on the ENABLE pin before the device goes to
sleep mode. The device comes out of sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time
must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
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Device Functional Modes (continued)
8.4.1.2 Operating Mode
When the ENABLE pin is high and VVM > VUVLO, the device goes to operating mode. The tWAKE time must elapse
before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD regulator,
and SPI bus are active
8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV835x family of devices goes to a partial shutdown state to help
protect the external power MOSFETs and system.
When the fault condition has been removed the device can reenter the operating state by either setting the
CLR_FLT SPI bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The
ENABLE reset pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the
sequence should fall with the tRST time window or else the device will start the complete shutdown sequence.
The reset pulse has no effect on any of the regulators, device settings, or other functional blocks
8.4.2 Buck Regulator Functional Modes
8.4.2.1 Shutdown Mode
The RT/SD pin provides ON and OFF control for the LM5008A. When VSD is below approximately 0.7 V, the
device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in
shutdown mode drops to 110 µA (typical) at VIN = 48 V. The LM5008A also employs VCC bias rail undervoltage
protection. If the VCC bias supply voltage is below its UV threshold, the regulator stays off.
8.4.2.2 Active Mode
LM5008A is in active mode when the internal bias rail, VCC, is above its UV threshold. Depending on the load
current, the device operates in either DCM or CCM mode.
Whenever the load current is decreased to a level less than half the peak-to-peak inductor ripple current, the
device goes to discontinuous conduction mode (DCM). Calculate the critical conduction boundary using
Equation 10.
IBOUNDARY
'IL
2
VOUT u 1 D
2 u LF u fSW
(10)
When the inductor current reaches zero, the SW node becomes high impedance. Resonant ringing occurs at SW
as a result of the LC tank circuit formed by the buck inductor and the parasitic capacitance at the SW node. At
light loads, several pulses may be skipped in between switching cycles, effectively reducing the switching
frequency and further improving light-load efficiency.
8.5 Programming
This section applies only to the DRV835x SPI devices.
8.5.1 SPI Communication
8.5.1.1 SPI
On DRV835x SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input data
(SDI) word consists of a 16 bit word, with a 5 bit command and 11 bits of data. The SPI output data (SDO) word
consists of 11-bit register data. The first 5 bits are don’t care bits.
A
•
•
•
54
valid frame must meet the following conditions:
The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
The nSCS pin should be pulled high for at least 400 ns between words.
When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is set
Hi-Z.
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Programming (continued)
•
•
•
•
•
•
Data is captured on the falling edge of SCLK and data is propagated on the rising edge of SCLK.
The most significant bit (MSB) is shifted in and out first.
A full 16 SCLK cycles must occur for transaction to be valid.
If the data word sent to the SDI pin is not 16 bits, a frame error occurs and the data word is ignored.
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5 bit command data.
The SDO pin is an open-drain output and requires an external pullup resistor.
8.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit B15)
• 4 address bits, A (bits B14 through B11)
• 11 data bits, D (bits B11 through B0)
Set the read/write bit (W0, B15) to 0b for a write command. Set the read/write bit (W0, B15) to 1b for a read
command.
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The response word is the data
currently in the register being accessed.
Table 7. SDI Input Data Word Format
R/W
ADDRESS
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
W0
A3
A2
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 8. SDO Output Data Word Format
DON'T CARE BITS
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
nSCS
SCLK
SDI
X
MSB
LSB
X
SDO
Z
MSB
LSB
Z
Capture
Point
Propagate
Point
Figure 54. SPI Slave Timing Diagram
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8.6 Register Maps
This section applies only to the DRV835x SPI devices.
NOTE
Do not modify reserved registers or addresses not listed in the register maps (Table 9). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller,
set the LOCK bits to lock the SPI registers.
Table 9. Register Map
Name
10
9
8
7
6
5
4
3
2
1
0
Type
Address
DRV8350S and DRV8350RS
Fault Status 1
FAULT
VDS_OCP
GDF
UVLO
OTSD
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
R
0h
VGS Status 2
SA_OC
SB_OC
SC_OC
OTW
GDUV
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
R
1h
Driver Control
OCP_ACT
DIS_GDUV
DIS_GDF
OTW_REP
1PWM_COM
1PWM_DIR
COAST
BRAKE
CLR_FLT
RW
2h
Gate Drive HS
PWM_MODE
LOCK
Gate Drive LS
CBC
TDRIVE
OCP Control
TRETRY
DEAD_TIME
IDRIVEP_HS
IDRIVEN_HS
RW
3h
IDRIVEP_LS
IDRIVEN_LS
RW
4h
VDS_LVL
RW
5h
OCP_MODE
OCP_DEG
Reserved
Reserved
RW
6h
Reserved
Reserved
RW
7h
DRV8353S and DRV8353RS
Fault Status 1
FAULT
VDS_OCP
GDF
UVLO
OTSD
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
R
0h
VGS Status 2
SA_OC
SB_OC
SC_OC
OTW
GDUV
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
R
1h
Driver Control
OCP_ACT
DIS_GDUV
DIS_GDF
OTW_REP
1PWM_COM
1PWM_DIR
COAST
BRAKE
CLR_FLT
RW
2h
Gate Drive HS
LOCK
Gate Drive LS
CBC
TDRIVE
OCP Control
TRETRY
DEAD_TIME
CSA Control
CSA_FET
VREF_DIV
Reserved
56
LS_REF
PWM_MODE
IDRIVEP_HS
IDRIVEN_HS
RW
3h
IDRIVEP_LS
IDRIVEN_LS
RW
4h
VDS_LVL
RW
5h
RW
6h
RW
7h
OCP_MODE
CSA_GAIN
OCP_DEG
DIS_SEN
CSA_CAL_A
CSA_CAL_B
Reserved
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CSA_CAL_C
SEN_LVL
CAL_MODE
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8.6.1 Status Registers
The status registers are used to reporting warning and fault conditions. The status registers are read-only
registers
Complex bit access types are encoded to fit into small table cells. Table 10 shows the codes that are used for
access types in this section.
Table 10. Status Registers Access Type Codes
Access Type
Code
Description
R
Read
Read Type
R
Reset or Default Value
-n
Value after reset or the default value
8.6.1.1 Fault Status Register 1 (address = 0x00h)
The fault status register 1 is shown in Figure 55 and described in Table 11.
Register access type: Read only
Figure 55. Fault Status Register 1
10
9
8
7
6
5
4
3
2
1
0
FAULT
VDS_OCP
GDF
UVLO
OTSD
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
Table 11. Fault Status Register 1 Field Descriptions
Bit
Field
Type
Default
Description
10
FAULT
R
0b
Logic OR of FAULT status registers. Mirrors nFAULT pin.
9
VDS_OCP
R
0b
Indicates VDS monitor overcurrent fault condition
8
GDF
R
0b
Indicates gate drive fault condition
7
UVLO
R
0b
Indicates undervoltage lockout fault condition
6
OTSD
R
0b
Indicates overtemperature shutdown
5
VDS_HA
R
0b
Indicates VDS overcurrent fault on the A high-side MOSFET
4
VDS_LA
R
0b
Indicates VDS overcurrent fault on the A low-side MOSFET
3
VDS_HB
R
0b
Indicates VDS overcurrent fault on the B high-side MOSFET
2
VDS_LB
R
0b
Indicates VDS overcurrent fault on the B low-side MOSFET
1
VDS_HC
R
0b
Indicates VDS overcurrent fault on the C high-side MOSFET
0
VDS_LC
R
0b
Indicates VDS overcurrent fault on the C low-side MOSFET
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8.6.1.2 Fault Status Register 2 (address = 0x01h)
The fault status register 2 is shown in Figure 56 and described in Table 12.
Register access type: Read only
Figure 56. Fault Status Register 2
10
9
8
7
6
5
4
3
2
1
0
SA_OC
SB_OC
SC_OC
OTW
GDUV
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
Table 12. Fault Status Register 2 Field Descriptions
58
Bit
Field
Type
Default
Description
10
SA_OC
R
0b
Indicates overcurrent on phase A sense amplifier (DRV8353xS)
9
SB_OC
R
0b
Indicates overcurrent on phase B sense amplifier (DRV8353xS)
8
SC_OC
R
0b
Indicates overcurrent on phase C sense amplifier (DRV8353xS)
7
OTW
R
0b
Indicates overtemperature warning
6
GDUV
R
0b
Indicates VCP charge pump and/or VGLS undervoltage fault
condition
5
VGS_HA
R
0b
Indicates gate drive fault on the A high-side MOSFET
4
VGS_LA
R
0b
Indicates gate drive fault on the A low-side MOSFET
3
VGS_HB
R
0b
Indicates gate drive fault on the B high-side MOSFET
2
VGS_LB
R
0b
Indicates gate drive fault on the B low-side MOSFET
1
VGS_HC
R
0b
Indicates gate drive fault on the C high-side MOSFET
0
VGS_LC
R
0b
Indicates gate drive fault on the C low-side MOSFET
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8.6.2 Control Registers
The control registers are used to configure the device. The control registers are read and write capable
Complex bit access types are encoded to fit into small table cells. Table 13 shows the codes that are used for
access types in this section.
Table 13. Control Registers Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default value
8.6.2.1 Driver Control Register (address = 0x02h)
The driver control register is shown in Figure 57 and described in Table 14.
Register access type: Read/Write
Figure 57. Driver Control Register
10
9
8
7
4
3
2
1
0
OCP
_ACT
DIS
_GDUV
DIS
_GDF
OTW
_REP
6
PWM_MODE
5
1PWM
_COM
1PWM
_DIR
COAST
BRAKE
CLR
_FLT
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-00b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
Table 14. Driver Control Field Descriptions
Bit
Field
Type
Default
Description
10
OCP_ACT
R/W
0b
0b = Associated half-bridge is shutdown in response to
VDS_OCP and SEN_OCP
1b = All three half-bridges are shutdown in response to
VDS_OCP and SEN_OCP
9
DIS_GDUV
R/W
0b
8
DIS_GDF
R/W
0b
7
OTW_REP
R/W
0b
PWM_MODE
R/W
00b
0b =VCP and VGLS undervoltage lockout fault is enabled
1b = VCP and VGLS undervoltage lockout fault is disabled
0b = Gate drive fault is enabled
1b = Gate drive fault is disabled
0b = OTW is not reported on nFAULT or the FAULT bit
1b = OTW is reported on nFAULT and the FAULT bit
6-5
00b = 6x PWM Mode
01b = 3x PWM mode
10b = 1x PWM mode
11b = Independent PWM mode
4
1PWM_COM
R/W
0b
0b = 1x PWM mode uses synchronous rectification
1b = 1x PWM mode uses asynchronous rectification
3
1PWM_DIR
R/W
0b
In 1x PWM mode this bit is ORed with the INHC (DIR) input
2
COAST
R/W
0b
Write a 1 to this bit to put all MOSFETs in the Hi-Z state
1
BRAKE
R/W
0b
Write a 1 to this bit to turn on all three low-side MOSFETs
This bit is ORed with the INLC (BRAKE) input in 1x PWM mode.
0
CLR_FLT
R/W
0b
Write a 1 to this bit to clear latched fault bits.
This bit automatically resets after being writen.
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8.6.2.2 Gate Drive HS Register (address = 0x03h)
The gate drive HS register is shown in Figure 58 and described in Table 15.
Register access type: Read/Write
Figure 58. Gate Drive HS Register
10
9
8
7
6
5
4
3
2
1
LOCK
IDRIVEP_HS
IDRIVEn_HS
R/W-011b
R/W-1111b
R/W-1111b
0
Table 15. Gate Drive HS Field Descriptions
Bit
Field
Type
Default
Description
10-8
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x02h bits 0-2.
Writing any sequence other than 110b has no effect when
unlocked.
Write 011b to this register to unlock all registers.
Writing any sequence other than 011b has no effect when
locked.
7-4
IDRIVEP_HS
R/W
1111b
0000b = 50 mA
0001b = 50 mA
0010b = 100 mA
0011b = 150 mA
0100b = 300 mA
0101b = 350 mA
0110b = 400 mA
0111b = 450 mA
1000b = 550 mA
1001b = 600 mA
1010b = 650 mA
1011b = 700 mA
1100b = 850 mA
1101b = 900 mA
1110b = 950 mA
1111b = 1000 mA
3-0
IDRIVEN_HS
R/W
1111b
0000b = 100 mA
0001b = 100 mA
0010b = 200 mA
0011b = 300 mA
0100b = 600 mA
0101b = 700 mA
0110b = 800 mA
0111b = 900 mA
1000b = 1100 mA
1001b = 1200 mA
1010b = 1300 mA
1011b = 1400 mA
1100b = 1700 mA
1101b = 1800 mA
1110b = 1900 mA
1111b = 2000 mA
60
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8.6.2.3 Gate Drive LS Register (address = 0x04h)
The gate drive LS register is shown in Figure 59 and described in Table 16.
Register access type: Read/Write
Figure 59. Gate Drive LS Register
10
9
8
7
6
5
4
3
2
1
CBC
TDRIVE
IDRIVEP_LS
IDRIVEN_LS
R/W-1b
R/W-11b
R/W-1111b
R/W-1111b
0
Table 16. Gate Drive LS Register Field Descriptions
Bit
Field
Type
Default
Description
10
CBC
R/W
1b
Active only when OCP_MODE = 01b
0b = For VDS_OCP and SEN_OCP, the fault is cleared after
tRETRY
1b = For VDS_OCP and SEN_OCP, the fault is cleared when
a new PWM input is given or after tRETRY
9-8
TDRIVE
R/W
11b
00b = 500-ns peak gate-current drive time
01b = 1000-ns peak gate-current drive time
10b = 2000-ns peak gate-current drive time
11b = 4000-ns peak gate-current drive time
7-4
IDRIVEP_LS
R/W
1111b
0000b = 50 mA
0001b = 50 mA
0010b = 100 mA
0011b = 150 mA
0100b = 300 mA
0101b = 350 mA
0110b = 400 mA
0111b = 450 mA
1000b = 550 mA
1001b = 600 mA
1010b = 650 mA
1011b = 700 mA
1100b = 850 mA
1101b = 900 mA
1110b = 950 mA
1111b = 1000 mA
3-0
IDRIVEN_LS
R/W
1111b
0000b = 100 mA
0001b = 100 mA
0010b = 200 mA
0011b = 300 mA
0100b = 600 mA
0101b = 700 mA
0110b = 800 mA
0111b = 900 mA
1000b = 1100 mA
1001b = 1200 mA
1010b = 1300 mA
1011b = 1400 mA
1100b = 1700 mA
1101b = 1800 mA
1110b = 1900 mA
1111b = 2000 mA
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8.6.2.4 OCP Control Register (address = 0x05h)
The OCP control register is shown in Figure 60 and described in Table 17.
Register access type: Read/Write
Figure 60. OCP Control Register
10
9
8
7
6
5
4
3
2
1
TRETRY
DEAD_TIME
OCP_MODE
OCP_DEG
VDS_LVL
R/W-0b
R/W-01b
R/W-01b
R/W-01b
R/W-1101b
0
Table 17. OCP Control Field Descriptions
Bit
Field
Type
Default
Description
10
TRETRY
R/W
0b
0b = VDS_OCP and SEN_OCP retry time is 8 ms
9-8
DEAD_TIME
R/W
01b
1b = VDS_OCP and SEN_OCP retry time is 50 µs
00b = 50-ns dead time
01b = 100-ns dead time
10b = 200-ns dead time
11b = 400-ns dead time
7-6
OCP_MODE
R/W
01b
00b = Overcurrent causes a latched fault
01b = Overcurrent causes an automatic retrying fault
10b = Overcurrent is report only but no action is taken
11b = Overcurrent is not reported and no action is taken
5-4
OCP_DEG
R/W
10b
00b = Overcurrent deglitch of 1 µs
01b = Overcurrent deglitch of 2 µs
10b = Overcurrent deglitch of 4 µs
11b = Overcurrent deglitch of 8 µs
3-0
VDS_LVL
R/W
1001b
0000b = 0.06 V
0001b = 0.07 V
0010b = 0.08 V
0011b = 0.09 V
0100b = 0.1 V
0101b = 0.2 V
0110b = 0.3 V
0111b = 0.4 V
1000b = 0.5 V
1001b = 0.6 V
1010b = 0.7 V
1011b = 0.8 V
1100b = 0.9 V
1101b = 1 V
1110b = 1.5 V
1111b = 2 V
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8.6.2.5 CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
The CSA control register is shown in Figure 61 and described in Table 18.
Register access type: Read/Write
This register is only available with the DRV8353x family of devices.
Figure 61. CSA Control Register
10
9
8
5
4
3
2
CSA
_FET
VREF
_DIV
LS
_REF
7
CSA
_GAIN
6
DIS
_SEN
CSA
_CAL_A
CSA
_CAL_B
CSA
_CAL_C
1
SEN
_LVL
0
R/W-0b
R/W-1b
R/W-0b
R/W-10b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-11b
Table 18. CSA Control Field Descriptions
Bit
Field
Type
Default
Description
10
CSA_FET
R/W
0b
0b = Sense amplifier positive input is SPx
1b = Sense amplifier positive input is SHx (also automatically
sets the LS_REF bit to 1)
9
VREF_DIV
R/W
1b
8
LS_REF
R/W
0b
0b = Sense amplifier reference voltage is VREF (unidirectional
mode)
1b = Sense amplifier reference voltage is VREF divided by 2
0b = VDS_OCP for the low-side MOSFET is measured
across SHx to SPx
1b = VDS_OCP for the low-side MOSFET is measured across
SHx to SNx
7-6
CSA_GAIN
R/W
10b
00b = 5-V/V shunt amplifier gain
01b = 10-V/V shunt amplifier gain
10b = 20-V/V shunt amplifier gain
11b = 40-V/V shunt amplifier gain
5
DIS_SEN
R/W
0b
0b = Sense overcurrent fault is enabled
1b = Sense overcurrent fault is disabled
4
CSA_CAL_A
R/W
0b
0b = Normal sense amplifier A operation
1b = Short inputs to sense amplifier A for offset calibration
3
CSA_CAL_B
R/W
0b
2
CSA_CAL_C
R/W
0b
SEN_LVL
R/W
11b
0b = Normal sense amplifier B operation
1b = Short inputs to sense amplifier B for offset calibration
0b = Normal sense amplifier C operation
1b = Short inputs to sense amplifier C for offset calibration
1-0
00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V
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8.6.2.6 Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
The driver configuration register is shown in Figure 62 and described in Table 19.
Register access type: Read/Write
This register is only available with the DRV8353 and DRV8353R devices.
Figure 62. Driver Configuration Register
10
9
8
7
6
5
4
3
2
1
0
Reserved
CAL
_MODE
R/W-000 0000 000b
R/W-0b
Table 19. Driver Configuration Field Descriptions
Bit
10-1
0
Field
Type
Default
Description
Reserved
R/W
000 0000
000b
Reserved
CAL_MODE
R/W
0b
0b = Amplifier calibration operates in manual mode
1b = Amplifier calibration uses internal auto calibration routine
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DRV835x family of devices are primarily used in three-phase brushless DC motor control applications. The
design procedures in the Typical Application section highlight how to use and configure the DRV835x family of
devices.
9.2 Typical Application
9.2.1 Primary Application
The DRV8353R is shown being used for a single supply, three-phase BLDC motor drive with individual halfbridge current sense in this application example.
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Typical Application (continued)
37
INLB
INHC
38
39
VREF
SNA
SOA
GHA
GLA
SHB
31
VCC
30
1k
10 k
28
27
VCC
1 …F
26
25
VM
CBYP
SHC
CBULK
MOTC
GLC
SPC
RSENB
SNB
VCC
29
VM
MOTB
SPB
RSENA
SNA
32
GHC
GLB
SPA
33
CBYP
GHB
MOTA
34
24
23
SNC
22
SHC
VM
CBYP
35
SNC
21
SPC
20
GLC
SPB
19
SPB
14
13
VM
36
SOB
SPA
SOC
AGND
SPC
GLA
GLC
nFAULT
CBULK
SHA
INLC
40
DVDD
41
DGND
42
VIN
SW
0.47 …F
44
VCC
43
0.01 …F
SHA
SNB
VM
BST
RRCL
46
SDO
SHC
12
SDI
GHA
SNB
SNA
11
VCP
GHC
SPA
10
SCLK
Thermal
Pad
18
GLA
9
VDRAIN
GHC
SHA
8
nSCS
GHB
GHA
VM
17
7
ENABLE
GHB
6
1 …F
CPH
SHB
0.1 …F
INHA
16
5
INHB
CPL
SHB
4
1 …F
INLA
GLB
47 nF
VM
VM
CIN
VGLS
15
3
GND
GLB
2
RT/SD
FB
1
1 …F
RCL
RFB2
48
COUT
RRT/SD
VM
DOUT
RFB1
47
ROUT
45
LOUT
VCC
RSENC
SNC
Figure 63. Primary Application Schematic
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Typical Application (continued)
9.2.1.1 Design Requirements
Table 20 lists the example input parameters for the system design.
Table 20. Design Parameters
EXAMPLE DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Power supply voltage
VVM, VVDRAIN, VVIN
48 V
MOSFET part number
MOSFET
CSD19535KCS
MOSFET total gate charge
Qg
78 nC (typical) at VVGS = 10 V
MOSFET gate to drain charge
Qgd
13 nC (typical)
Target output rise time
tr
100 to 300 ns
Target output fall time
tf
50 to 150 ns
PWM frequency
ƒPWM
45 kHz
Buck regulator output voltage
VVCC
3.3 V
Buck regulator output current
IVCC
100 mA
Maximum motor current
Imax
100 A
ADC reference voltage
VVREF
3.3 V
Winding sense current range
ISENSE
–40 A to +40 A
IRMS
28.3 A
Motor RMS current
Sense resistor power rating
PSENSE
3W
TA
–20°C to +60°C
System ambient temperature
9.2.1.2 Detailed Design Procedure
Table 21 lists the recommended values of the external components for the gate driver. Table 22 lists the
recommended values of the external components for the buck regulator.
Table 21. DRV835x Gate-Driver External Components
COMPONENTS
PIN 1
PIN 2
RECOMMENDED
CVM1
VM
GND
X5R or X7R, 0.1-µF, VM-rated capacitor
CVM2
VM
GND
≥ 10 µF, VM-rated capacitor
CVCP
VCP
VM
X5R or X7R, 1-µF, 16-V capacitor
CVGLS
VGLS
GND
X5R or X7R, 1-µF, 16-V capacitor
CSW
CPH
CPL
X5R or X7R, 47-nF, VDRAIN-rated capacitor
CDVDD
DVDD
DGND
X5R or X7R, 1-µF, 6.3-V capacitor
nFAULT
Pullup resistor
RnFAULT
(1)
VCC
(1)
RSDO
VCC (1)
SDO
Pullup resistor
RIDRIVE
IDRIVE
GND or DVDD
DRV835x hardware interface
RVDS
VDS
GND or DVDD
DRV835x hardware interface
RMODE
MODE
GND or DVDD
DRV835x hardware interface
RGAIN
GAIN
GND or DVDD
DRV835x hardware interface
CVREF
VREF
GND or DGND
Optional capacitor rated for VREF
RASENSE
SPA
SNA and GND
Sense shunt resistor
RBSENSE
SPB
SNB and GND
Sense shunt resistor
RCSENSE
SPC
SNC and GND
Sense shunt resistor
VCC is not a pin on the DRV835x family of devices, but a VCC supply voltage pullup is required for the open-drain output nFAULT and
SDO. These pins can also be pulled up to DVDD.
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Table 22. DRV835xR Buck Regulator External Components
COMPONENT
CIN
(1)
(2)
(1)
PIN 1
PIN 2
RECOMMENDED
VIN
GND
X5R or X7R, VIN-rated capacitor
CBST (1)
BST
SW
X5R or X7R, 0.01-µF, 16-V rated capacitor
CVCC (1)
VCC
GND
X5R or X7R, 0.47-µF, 16-V rated capacitor
DSW (1)
SW
GND
Schottky diode
LSW (1)
SW
OUT (2)
Output filter inductor
COUT
(1)
OUT (2)
GND
X5R or X7R, OUT-rated capacitor
ROUT
(1)
OUT (2)
GND
Output ripple resistor
RFB1 (1)
OUT (2)
FB
RFB2 (1)
FB
GND
Resistor divider to set buck output voltage
For detailed design procedures, refer to the LM5008A 100-V 350-mA Constant On-Time Buck Switching Regulator data sheet.
OUT is not a pin on the DRV8350R and DRV8353R devices, but the regulated output voltage of the buck regulator after the output
inductor.
9.2.1.2.1 External MOSFET Support
The DRV835x family of devices MOSFET support is based on the MOSFET gate charge, VCP charge-pump
capacity, VGLS regulator capacity, and output PWM switching frequency. For a quick calculation of MOSFET
driving capacity, use Equation 11 and Equation 12 for three phase BLDC motor applications.
Trapezoidal 120° Commutation: IVCP/VGLS > Qg × ƒPWM
Sinusoidal 180° Commutation: IVCP/VGLS > 3 × Qg × ƒPWM
(11)
where
•
•
•
•
ƒPWM is the maximum desired PWM switching frequency.
Qg is the MOSFET total gate charge
IVCP/VGLS is the charge pump or low-side regulator capacity, dependent on the VM pin voltage.
The MOSFET multiplier based on the commutation control method, may vary based on implementation.
(12)
9.2.1.2.1.1 MOSFET Example
If a system is using VVM = 48 V (IVCP = 25 mA) and a maximum PWM switching frequency of 45 kHz, then the
VCP charge-pump and VGLS regulator can support MOSFETs using trapezoidal commutation with a Qg < 556
nC, and MOSFETs using sinusoidal commutation with a Qg < 185 nC.
9.2.1.2.2 IDRIVE Configuration
The gate drive current strength, IDRIVE, is selected based on the gate-to-drain charge of the external MOSFETs
and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given MOSFET, then the
MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be asserted. Additionally,
slow rise and fall times will lead to higher switching power losses. TI recommends adjusting these values in
system with the required external MOSFETs and motor to determine the best possible setting for any application.
The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable on
SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are selected
at the same time on the IDRIVE pin.
For MOSFETs with a known gate-to-drain charge Qgd, desired rise time (tr), and a desired fall time (tf), use
Equation 13 and Equation 14 to calculate the value of IDRIVEP and IDRIVEN (respectively).
Qgd
IDRIVEP !
tr
(13)
IDRIVEN !
Qgd
tf
(14)
9.2.1.2.2.1 IDRIVE Example
Use Equation 15 and Equation 16 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate to drain
charge of 13 nC and a rise time from 100 to 300 ns.
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IDRIVEP1
IDRIVEP2
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13 nC
130 mA
100 ns
13 nC
43 mA
300 ns
(15)
(16)
Select a value for IDRIVEP that is between 43 mA and 130 mA. For this example, the value of IDRIVEP was selected
as 100-mA source.
Use Equation 17 and Equation 18 to calculate the value of IDRIVEN1 and IDRIVEN2 (respectively) for a gate to drain
charge of 13 nC and a fall time from 50 to 150 ns.
13 nC
IDRIVEN1
260 mA
50 ns
(17)
13 nC
IDRIVEN2
87 mA
150 ns
(18)
Select a value for IDRIVEN that is between 87 mA and 260 mA. For this example, the value of IDRIVEN was selected
as 200-mA sink.
9.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in Equation 19.
VDS _ OCP ! Imax u RDS(on)max
(19)
9.2.1.2.3.1 VDS Overcurrent Example
The goal of this example is to set the VDS monitor to trip at a current greater than 75 A. According to the
CSD19535KCS 100 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 2.2 times higher at
175°C, and the maximum RDS(on) value at a VGS of 10 V is 3.6 mΩ at TA = 25°C. From these values, the
approximate worst-case value of RDS(on) is 2.2 × 3.6 mΩ = 7.92 mΩ.
Using Equation 19 with a value of 7.92 mΩ for RDS(on) and a worst-case motor current of 75 A, Equation 20
shows the calculated desired value of the VDS overcurrent monitors.
VDS _ OCP ! 75 A u 7.92 m:
VDS _ OCP ! 0.594 V
(20)
For this example, the value of VDS_OCP was selected as 0.6 V.
The SPI devices allow for adjustment of the deglitch time for the VDS overcurrent monitor. The deglitch time can
be set to 1 µs, 2 µs, 4 µs, or 8 µs.
9.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353 and DRV8353R)
The sense amplifier gain on the DRV8353 and DRV8353R devices and sense resistor value are selected based
on the target current range, VREF reference voltage, sense-resistor power rating, and operating temperature
range. In bidirectional operation of the sense amplifier, the dynamic range at the output is approximately
calculated as shown in Equation 21.
VVREF
VO
VVREF 0.25 V
2
(21)
Use Equation 22 to calculate the approximate value of the selected sense resistor with VO calculated using
Equation 21.
VO
R
PSENSE ! IRMS2 u R
AV u I
(22)
From Equation 21 and Equation 22, select a target gain setting based on the power rating of the target sense
resistor.
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9.2.1.2.4.1 Sense-Amplifier Example
In this system example, the value of VREF voltage is 3.3 V with a sense current from –40 to +40 A. The linear
range of the SOx output is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential range of the
sense amplifier input is –0.3 to +0.3 V (VDIFF).
3.3 V
VO
3.3 V 0.25 V
1.4 V
(23)
2
1.4 V
R
2 W ! 28.32 u R o R 2.5 m:
A V u 40 A
(24)
2.5 m: !
1.4 V
o A V ! 14
A V u 40 A
(25)
Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 2.5 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst case current can be verified that R < 2.5 mΩ and Imax =
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
9.2.1.2.5 Single Supply Power Dissipation
Design care must be taken to make sure that the thermal ratings of the DRV835x are not violated during normal
operation of the device. The is especially critical in higher voltage and higher ambient operation applications
where power dissipation or the device ambient temperature are increased.
To determine the temperature of the device in single supply operation, first the power internal power dissipation
must be calculated. The internal power dissipation has four primary components:
• VCP charge pump power dissipation (PVCP)
• VGLS low-side regulator power dissipation (PVGLS)
• VM device nominal power dissipation (PVM)
• VIN buck regulator power dissipation (PBUCK)
The values of PVCP and PVGLS can be approximated by referring to External MOSFET Support to first determine
IVCP and IVGLS and then referring to Equation 26 and Equation 27.
PVCP = IVCP × (VVM + VVDRAIN)
(26)
PVGLS = IVGLS × VVM
(27)
The value of PVM can be calculated by referring to the data sheet parameter for IVM current and Equation 28.
PVM = IVM × VVM
(28)
PBUCK = (PO / η) - PO
where
PO = VVCC × IVCC
(30)
(30)
The value of PBUCK can be calculated with the buck output voltage (VVCC), buck output current (IVCC), and by
referring to the typical characteristic curve for efficiency (η) in the LM5008A data sheet.
The total power dissipation is then calculated by summing the four components as shown in Equation 31.
Ptot = PVCP + PVGLS + PVM + PBUCK
(31)
Lastly, the device junction temperature can be estimate by referring to Thermal Information and Equation 32.
TJmax = TAmax + (RθJA × Ptot)
(32)
The information in Thermal Information is based off of a standardized test metric for package and PCB thermal
dissipation. The actual values may vary based on the actual PCB design used in the application.
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9.2.1.2.6 Single Supply Power Dissipation Example
In this application example the device is configured for single supply operation. This configuration requires only
one power supply for the DRV835x but comes at the tradeoff of increased internal power dissipation. The
junction temperature is estimated in the example below.
Use Equation 11 to calculate the value of IVCP and IVGLS for a MOSFET gate charge of 78 nC, all 3 high-side and
3 low-side MOSFETs switching, and a switching frequency of 45 kHz.
IVCP/VGLS = 78 nC × 3 × 45 kHz = 10.5 mA
(33)
Use Equation 26, Equation 27, Equation 28, Equation 29, and Equation 31 to calculate the value of Ptot for VVM =
VVDRAIN = VVIN = 48 V, IVM = 9.5 mA, IVCP = 10.5 mA, IVGLS = 10.5 mA, VVCC = 3.3 V, IVCC = 100 mA, and η =
86 %.
PVCP = 10.5 mA × (48 V + 48 V) = 1 W
(34)
PVGLS = 10.5 mA × 48 V = 0.5 W
(35)
PVM = 9.5 mA × 48 V = 0.5 W
(36)
PBUCK = [(3.3 V × 100 mA) / 0.86] – (3.3 V × 100 mA) = 0.054 W
(37)
Ptot = 1 W + 0.5 W + 0.5 W + 0.054 = 2.054 W
(38)
Lastly, to estimate the device junction temperature during operation, use Equation 32 to calculate the value of
TJmax for TAmax = 60°C, RθJA = 26.6°C/W for the RGZ package, and Ptot = 2.054 W. Again, please note that the
RθJA is highly dependent on the PCB design used in the actual application and should be verified. For more
information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
application report.
TJmax = 60°C + (26.6°C/W × 2.054 W) = 115°C
(39)
As shown in this example, the device is within its operational limits, but is operating almost to its maximum
operational junction temperature. Design care should be taken in the single supply configuration to correctly
manage the power dissipation of the device.
9.2.1.2.7 Buck Regulator Configuration (DRV8350R and DRV8353R)
For a detailed design procedure and information on selecting the correct buck regulator external components,
refer to LM5008A 100-V 350-mA Constant On-Time Buck Switching Regulator.
9.2.1.3 Application Curves
Figure 64. Gate Driver Operation 30% Duty Cycle
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Figure 65. Gate Driver Operation 90% Duty Cycle
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Figure 66. IDRIVE Minimum Setting Positive Current
Figure 67. IDRIVE Minimum Setting Negative Current
Figure 68. IDRIVE 300-mA and 600-mA Setting Positive
Current
Figure 69. IDRIVE 300-mA and 600-mA Setting Negative
Current
Figure 70. IDRIVE Maximum Setting Positive Current
Figure 71. IDRIVE Maximum Setting Negative Current
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Figure 72. FOC Motor Commutation
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9.2.2 Alternative Application
In this application, the DRV8353R is configured to use one sense amplifier in unidirectional mode for a summing
current sense scheme often used in trapezoidal or hall-based BLDC commutation control. Additionally, the device
is configured in dual supply mode using the integrated buck regulator for the VM gate drive voltage supply to
decrease internal power dissipation.
LOUT
3
4
VM
5
6
8
SDI
SDO
GHA
GHA
MOTA
33
32
31
VCC
30
1k
SHB
VCC
29
10 k
28
27
1 …F
26
VCC
25
24
23
SNC
34
VDRAIN
VDRAIN
CBYP
GHB
SHA
22
21
VDRAIN
CBYP
35
SPC
20
GLC
19
SHC
18
GHC
SPB
14
SPB
VDRAIN
CBULK
36
SOB
SOA
SOC
SNA
SPC
VREF
GLC
SPA
SHC
AGND
GHC
GLA
GHB
12
nFAULT
17
11
SHA
GHB
10
SHB
9
VCC
CLOUT
37
INLB
INHC
38
39
INLC
40
DVDD
41
42
SW
43
VIN
0.47 …F
44
VCC
DGND
SCLK
Thermal
Pad
VCP
13
VDRAIN
0.01 …F
nSCS
SNB
SNA
ENABLE
16
SPA
CPH
SHB
GLA
INHA
GLB
SHA
INHB
CPL
VDRAIN
External
LDO
CLIN
VM
7
GHA
1 …F
INLA
15
1 …F
CIN
VGLS
GLB
VDRAIN
0.1 …F
45
RRCL
46
GND
2
47 nF
RT/SD
FB
1
1 …F
RCL
RFB2
48
COUT
VM
VDRAIN
RRT/SD
VDRAIN
DOUT
RFB1
47
ROUT
BST
VM
CBYP
CBULK
GHC
MOTB
SHC
GLA
GLB
GLC
SPA
SPB
SPC
MOTC
RSEN
SNA
Figure 73. Alternative Application Schematic
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9.2.2.1 Design Requirements
Table 23 lists the example design input parameters for system design.
Table 23. Design Parameters
EXAMPLE DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Power supply voltage
VVM
12 V
Buck supply voltage
VVIN
48 V
MOSFET drain voltage
VVDRAIN
48 V
MOSFET part number
MOSFET
CSD19535KCS
MOSFET total gate charge
Qg
78 nC
PWM frequency
fPWM
20 kHz
Buck regulator output voltage
VVCC
12 V
Buck regulator output current
IVCC
150 mA
ADC reference voltage
VVREF
3.3 V
Winding sense current range
ISENSE
0 to 40 A
IRMS
28.3 A
PSENSE
3W
TA
–20°C to +105°C
Motor RMS current
Sense-resistor power rating
System ambient temperature
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Sense Amplifier Unidirectional Configuration
The sense amplifiers are configured to be unidirectional through the registers on SPI devices by writing a 0 to the
VREF_DIV bit.
The sense-amplifier gain and sense resistor values are selected based on the target current range, VREF,
sense-resistor power rating, and operating temperature range. In unidirectional operation of the sense amplifier,
use Equation 40 to calculate the approximate value of the dynamic range at the output.
VO
VVREF 0.25 V 0.25 V VVREF 0.5 V
(40)
Use Equation 41 to calculate the approximate value of the selected sense resistor.
VO
R
PSENSE ! IRMS2 u R
AV u I
where
•
VO
VVREF
0.5 V
(41)
From Equation 40 and Equation 41, select a target gain setting based on the power rating of a target sense
resistor.
9.2.2.2.1.1 Sense-Amplifier Example
In this system example, the value of VVREF is 3.3 V with a sense current from 0 to 40 A. The linear range of the
SOx output for the DRV8353x device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential
range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).
VO 3.3 V 0.5 V 2.8 V
(42)
R
2.8 V
A V u 40 A
3.75 m: !
3 W ! 28.32 u R o R
3.75 m:
(43)
2.8 V
o A V ! 18.7
A V u 40 A
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Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 3.75 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 3.75 mΩ and Imax =
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
9.2.2.2.1.2 Dual Supply Power Dissipation
Design care must be taken to make sure that the thermal ratings of the DRV835x are not violated during normal
operation of the device. The is especially critical in higher voltage and higher ambient operation applications
where power dissipation or the device ambient temperature are increased.
To determine the temperature of the device in dual supply operation, first the internal power dissipation must be
calculated. The internal power dissipation has four primary components:
• VCP Charge pump power dissipation (PVCP)
• VGLS low-side regulator power dissipation (PVGLS)
• VM device nominal power dissipation (PVM)
• VIN buck regulator power dissipation (PBUCK)
The value of PVCP and PVGLS can be approximated by referring to External MOSFET Support to first determine
IVCP and IVGLS and then referring to Equation 45 and Equation 46.
PVCP = IVCP × (VVM + VVDRAIN)
(45)
PVGLS = IVGLS × VVM
(46)
The value of PVM can be calculated by referring to the datasheet parameter for IVM current and Equation 47.
PVM = IVM × VVM
(47)
PBUCK = (PO / η) – PO
where
PO = VVCC × IVCC
(49)
(49)
The value of PBUCK can be calculated with the buck output voltage (VVCC), buck output current (IVCC), and by
referring to the typical characteristic curve for efficiency (η) in the LM5008A data sheet.
The total power dissipation is then calculated by summing the four components as shown in Equation 50.
Ptot = PVCP + PVGLS + PVM + PBUCK
(50)
Lastly, the device junction temperature can be estimate by referring to the Thermal Information and Equation 51.
TJmax = TAmax + (RθJA × Ptot)
(51)
Note that the information in the Thermal Information is based off of a standardized test metric for package and
PCB thermal dissipation. The actual values may vary based on the actual PCB design used in the application.
9.2.2.2.1.3 Dual Supply Power Dissipation Example
In this application example the device is configured for dual supply operation. dual supply operation helps to
decrease the internal power dissipation by providing the gate driver with a lower supply voltage. This can be
derived from the internal buck regulator or an external power supply. The junction temperature is estimated in the
example below.
Use Equation 11 to calculate the value of IVCP and IVGLS for a MOSFET gate charge of 78 nC, 1 high-side and 1
low-side MOSFETs switch at a time, and a switching frequency of 20 kHz.
IVCP/VGLS = 78 nC × 1 × 20 kHz = 1.56 mA
(52)
Use equation Equation 45, Equation 46, Equation 47, Equation 48, and Equation 50 to calculate the value of Ptot
for VVM = 12 V, VVDRAIN = 48 V, VVIN = 48 V, IVM = 9.5 mA, IVCP = 1.56 mA, IVGLS = 1.56 mA, VVCC = 12 V, IVCC =
150 mA, and η = 86 %.
PVCP = 1.56 mA × (12 V + 48 V) = 0.1 W
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PVGLS = 1.56 mA × 12 V = 0.02 W
(54)
PVM = 9.5 mA × 12 V = 0.1 W
(55)
PBUCK = [(12 V × 150 mA) / 0.86] – (12 V × 150 mA) = 0.29 W
(56)
Ptot = 0.1 W + 0.02 W + 0.1 W + 0.29 = 0.51 W
(57)
Lastly, to estimate the device junction temperature during operation, use Equation 51 to calculate the value of
TJmax for TAmax = 105°C, RθJA = 26.6°C/W for the RGZ package, and Ptot = 0.51 W. Again, note that the RθJA is
highly dependent on the PCB design used in the actual application and should be verified. For more information
about traditional and new thermal metrics, refer to the Semiconductor and IC Package Thermal Metrics
application report.
TJmax = 105°C + (26.6°C/W × 0.51 W) = 119°C
(58)
10 Power Supply Recommendations
The DRV835x family of devices are designed to operate from an input voltage supply (VM) range between 9 V
and 75 V. A 0.1-µF ceramic capacitor rated for VM must be placed as near to the device as possible. In addition,
a bulk capacitor must be included on the VM pin but can be shared with the bulk bypass capacitance for the
external power MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs
and should be sized according to the application requirements.
10.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is usually
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
• The highest current required by the motor system
• The power supply's type, capacitance, and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable supply voltage ripple
• Type of motor (brushed DC, brushless DC, stepper)
• The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
stays stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 74. Motor Drive Supply Parasitics Example
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11 Layout
11.1 Layout Guidelines
Bypass the VM pin to the GND pin using a low-ESR ceramic bypass capacitor with a recommended value of 0.1
µF. Place this capacitor as near to the VM pin as possible with a thick trace or ground plane connected to the
GND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for
VDRAIN, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and
VDRAIN pins and VGLS and GNDs. These capacitors should be 1 µF, rated for 16 V, and be of type X5R or
X7R.
Bypass the DVDD pin to the GND/DGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type
X5R or X7R. Place this capacitor as near to the pin as possible and minimize the path from the capacitor to the
GND/DGND pin.
The VDRAIN pin can be shorted directly to the VM pin for single supply application configurations. However, if a
significant distance is between the device and the external MOSFETs, use a dedicated trace to connect to the
common point of the drains of the high-side external MOSFETs. Do not connect the SLx pins directly to GND.
Instead, use dedicated traces to connect these pins to the sources of the low-side external MOSFETs. These
recommendations allow for more accurate VDS sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the SPx/SLx pins.
11.1.1 Buck-Regulator Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI:
• Put the feedback network resistors near the FB pin and away from the inductor to minimize coupling noise
into the feedback pin.
• Put the input bypass capacitor near the VIN pin to decrease copper trace resistance which effects input
voltage ripple of the device.
• Put the inductor near the SW pin to decrease magnetic and electrostatic noise.
• Put the output capacitor near the junction of the inductor and the diode. The inductor, diode, and COUT trace
should be as short as possible to decrease conducted and radiated noise and increase overall efficiency.
• Make the ground connection for the diode, CVIN, and COUT as small as possible and tie it to the system
ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane.
For more detail on switching power supply layout considerations refer to the AN-1149 Layout Guidelines for
Switching Power Supplies application report.
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26 VREF
S
D
S
D
G
D
D
G
D
S
D
S
D
S
D
G
D
S
D
S
D
S
S
D
S
D
S
D
G
D
S
D
S
D
S
D
G
D
D
G
D
S
D
S
D
S
OUTC
SOB
D
SOC
SOA
25 SOA
27 AGND
30 SDI
29 SDO
28 nFAULT
31 SCLK
33 ENABLE
32 nSCS
36 INHB
35 INLA
38
23 SOC
39
22 SNC
21 SPC
40
41
20 GLC
42
19 SHC
Thermal Pad
43
18 GHC
OUTA
12
10
11
9
8
13 SNB
7
48
6
14 SPB
5
47
4
15 GLB
3
16 SHB
46
2
45
OUTB
17 GHB
44
GND
VGLS
CPL
CPH
VM
VDRAIN
VCP
GHA
SHA
GLA
SPA
SNA
VOUT
S
24 SOB
37
1
INLB
INHC
INLC
DVDD
DGND
SW
VIN
VCC
BST
RCL
RT/SD
FB
34 INHA
INHB
INLA
INHA
INLC
INHC
INLB
ENABLE
nSCS
SCLK
SDI
SDO
nFAULT
VREF
11.2 Layout Example
Figure 75. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:
DRV83
Prefix
DRV83 ± Three Phase Brushless DC
Series
5 ± 100 V device
Sense amplifiers
0 ± No sense amplifiers
3 ± 3x sense amplifiers
(5)
(3)
(R)
(S)
(RGZ) (R)
Tape and Reel
R ± Tape and Reel
T ± Small Tape and Reel
Package
RTV ± 5 × 5 × 0.75 mm QFN
RTA ± 6 x 6 × 0.75 mm QFN
RGZ ± 7 × 7 × 0.9 mm QFN
Interface
S ± SPI interface
H ± Hardware interface
Buck Regulator
[blank] ± No buck regulator
R ± Buck regulator
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, refer to:
• Texas Instruments, DRV8353Rx-EVM User’s Guide user's guide
• Texas Instruments, DRV8353Rx-EVM GUI User’s Guide
• Texas Instruments, DRV8353Rx-EVM InstaSPIN™ Software Quick Start Guide
• Texas Instruments, LM5008A 100-V 350-mA Constant On-Time Buck Switching Regulator data sheet
• Texas Instruments, CSD19535KCS 100 V N-Channel NexFET™ Power MOSFET data sheet
• Texas Instruments, Understanding IDRIVE and TDRIVE In TI Motor Gate Drivers application report
• Texas Instruments, Motor Drive Protection with TI Smart Gate Drive TI TechNote
• Texas Instruments, Reduce Motor Drive BOM and PCB Area with TI Smart Gate Drive TI TechNote
• Texas Instruments, Reducing EMI Radiated Emissions with TI Smart Gate Drive TI TechNote
• Texas Instruments, Hardware Design Considerations for an Efficient Vacuum Cleaner using BLDC Motor
• Texas Instruments, Hardware Design Considerations for an Electric Bicycle using BLDC Motor
• Texas Instruments, Industrial Motor Drive Solution Guide
• Texas Instruments, Layout Guidelines for Switching Power Supplies application report
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, Sensored 3-Phase BLDC Motor Control Using MSP430™ application report
• Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application report
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12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 24. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DRV8350
Click here
Click here
Click here
Click here
Click here
DRV8350R
Click here
Click here
Click here
Click here
Click here
DRV8353
Click here
Click here
Click here
Click here
Click here
DRV8353R
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
NexFET, InstaSPIN, MSP430, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2018–2019, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8350HRTVR
ACTIVE
WQFN
RTV
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8350H
DRV8350HRTVT
ACTIVE
WQFN
RTV
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8350H
DRV8350RHRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRV8350RH
DRV8350RHRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRV8350RH
DRV8350RSRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRV8350RS
DRV8350RSRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRV8350RS
DRV8350SRTVR
ACTIVE
WQFN
RTV
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8350S
DRV8350SRTVT
ACTIVE
WQFN
RTV
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8350S
DRV8353HRTAR
ACTIVE
WQFN
RTA
40
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8353H
DRV8353HRTAT
ACTIVE
WQFN
RTA
40
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8353H
DRV8353RHRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRV8353RH
DRV8353RHRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRV8353RH
DRV8353RSRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRV8353RS
DRV8353RSRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
DRV8353RS
DRV8353SRTAR
ACTIVE
WQFN
RTA
40
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8353S
DRV8353SRTAT
ACTIVE
WQFN
RTA
40
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8353S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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