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DRV8428RTER

DRV8428RTER

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    WQFN-16_3X3MM-EP

  • 描述:

    35V, 1A BIPOLAR STEPPER MOTOR DR

  • 详情介绍
  • 数据手册
  • 价格&库存
DRV8428RTER 数据手册
DRV8428 SLOSE54B – JUNE 2020 – REVISED MAY 2021 DRV8428 Stepper Driver With Integrated Current Sense, 1/256 Microstepping, STEP/DIR Interface and smart tune Technology 1 Features • • • • • • • • • • • • PWM Microstepping Stepper Motor Driver – Simple STEP/DIR Interface – Up to 1/256 Microstepping Indexer Integrated Current Sense Functionality – No Sense Resistors Required – ±6% Full-Scale Current Accuracy Smart tune decay technology and mixed decay options 4.2-V to 33-V Operating Supply Voltage Range RDS(ON): 1500 mΩ HS + LS at 24 V, 25°C Current Capacity Per Bridge: 1.7-A peak, 1-A FullScale, 0.7-A rms Configurable Off-Time PWM Chopping – 7-μs, 16-μs, or 32-μs. Supports 1.8-V, 3.3-V, 5.0-V Logic Inputs Low-Current Sleep Mode (2 μA) Spread spectrum clocking for low electromagnetic interference (EMI) Small Package and Footprint Protection Features – VM Undervoltage Lockout (UVLO) – Overcurrent Protection (OCP) – Thermal Shutdown (OTSD) – Fault Condition Output (EN/nFAULT) adjusts for optimal current regulation, compensates for motor variation and aging effects and reduces audible noise from the motor. A simple STEP/DIR interface allows an external controller to manage the direction and step rate of the stepper motor. The device can be configured in different step modes ranging from full-step to 1/256 microstepping. A low-power sleep mode is provided for very low standby quiescent standby current using a dedicated nSLEEP pin. Protection features are provided for supply undervoltage, overcurrent, short circuits, and overtemperature. Fault conditions are indicated by the EN/nFAULT pin. Device Information(1) (1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV8428PWPR HTSSOP (16) 5mm x 4.4mm DRV8428RTER WQFN (16) 3.0mm x 3.0mm For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • • • • Printers and scanners Stage lighting equipment Sewing machines Security and dome cameras Office and home zutomation Factory automation and robotics Medical applications Simplified Schematic 3 Description The DRV8428 is a stepper motor driver for industrial and consumer applications. The device is fully integrated with two N-channel power MOSFET H-bridge drivers, a microstepping indexer, and integrated current sensing. The DRV8428 is capable of driving up to 1-A full-scale output current (dependent on PCB design). The DRV8428 uses an internal current sense architecture to eliminate the need for two external power sense resistors, saving PCB area and system cost. The device uses an internal PWM current regulation scheme selectable between smart tune, and mixed decay options. Smart tune automatically An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 5.1 Pin Functions.............................................................. 3 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................6 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................7 6.6 Indexer Timing Requirements..................................... 8 6.7 Typical Characteristics................................................ 9 7 Detailed Description...................................................... 11 7.1 Overview................................................................... 11 7.2 Functional Block Diagram......................................... 12 7.3 Feature Description...................................................12 7.4 Device Functional Modes..........................................26 8 Application and Implementation.................................. 27 8.1 Application Information............................................. 27 8.2 Typical Application.................................................... 27 9 Power Supply Recommendations................................34 9.1 Bulk Capacitance...................................................... 34 10 Layout...........................................................................35 10.1 Layout Guidelines................................................... 35 11 Device and Documentation Support..........................37 11.1 Receiving Notification of Documentation Updates.. 37 11.2 Community Resources............................................37 11.3 Trademarks............................................................. 37 12 Mechanical, Packaging, and Orderable Information.................................................................... 38 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (November 2020) to Revision B (May 2021) Page • Corrected typo in Table 7-4 ..............................................................................................................................14 • Removed duplicate package drawings............................................................................................................. 38 Changes from Revision * (June 2020) to Revision A (November 2020) Page • Changed device status to production data......................................................................................................... 1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 5 Pin Configuration and Functions Figure 5-1. PWP PowerPAD™ Package 16-Pin HTSSOP Top View Figure 5-2. RTE Package 16-Pin WQFN with Exposed Thermal PAD Top View 5.1 Pin Functions PIN NAME NO. I/O TYPE DESCRIPTION O Output Winding A output. Connect to stepper motor winding. HTSSOP WQFN AOUT1 3 1 AOUT2 4 2 O Output Winding A output. Connect to stepper motor winding. PGND 2 16 PWR Power Power ground. Connect to system ground. BOUT2 5 3 O Output Winding B output. Connect to stepper motor winding BOUT1 6 4 O Output Winding B output. Connect to stepper motor winding DIR 14 12 I Input EN/ nFAULT 15 13 I/O Input/Output Logic low to disable device outputs; logic high to enable. Also used for fault indication. Pulled logic low in fault condition. DVDD 8 6 PWR Power Logic supply voltage. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND. GND 7 5 PWR Power Device ground. Connect to system ground. VREF 9 7 I Input Current set reference input. Maximum value 3 V. DVDD can be used to provide VREF through a resistor divider. M0 10 8 M1 12 10 I Input Microstepping mode-setting pins. Sets the step mode; internal pulldown resistor. DECAY/ TOFF 11 9 I Input Decay-mode and off-time setting pin. See the Section 7.3.5 section for details. Direction input. Logic level sets the direction of stepping; internal pulldown resistor. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 3 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 PIN NAME I/O TYPE HTSSOP WQFN STEP 13 11 I Input VM 1 15 PWR Power nSLEEP 16 14 I Input - - - - PAD 4 NO. DESCRIPTION Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor. Power supply. Connect to motor supply voltage and bypass to PGND with a 0.01-µF ceramic capacitor plus a bulk capacitor rated for VM. Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor. An nSLEEP low pulse clears faults. Thermal pad. Connect to system ground. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Power supply voltage (VM) MIN MAX UNIT –0.3 35 V nSLEEP pin voltage (nSLEEP) –0.3 VVM V Internal regulator voltage (DVDD) –0.3 5.75 V Control pin voltage (STEP, DIR, EN/nFAULT, DECAY/TOFF, M0, M1) –0.3 5.75 V 0 10 mA Open drain output current (EN/nFAULT) Reference input pin voltage (VREF) –0.3 5.75 V –1 VVM + 1 V Transient 100 ns phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) –3 VVM + 3 V Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2) Internally Limited A Operating ambient temperature, TA –40 125 °C Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22C101 UNIT ±2000 Corner pins for PWP (1, 8, 9, and 16) ±750 Other pins ±500 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 V 5 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VVM Supply voltage range for normal (DC) operation VI Logic level input voltage MAX UNIT 4.2 33 V 0 5.5 V VVREF VREF voltage 0.05 3 V ƒPWM Applied STEP signal (STEP) 0 500(1) kHz IFS Motor full-scale current (xOUTx) 0 1(2) A Irms Motor RMS current (xOUTx) 0 0.7(2) A TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C (1) (2) STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load Power dissipation and thermal limits must be observed 6.4 Thermal Information DRV8428 THERMAL METRIC(1) PWP (HTSSOP) RTE (WQFN) 16 PINS 16 PINS 46.4 47 °C/W RθJC(top) Junction-to-case (top) thermal resistance 39.8 46.1 °C/W RθJB Junction-to-board thermal resistance 19.9 19.9 °C/W ψJT Junction-to-top characterization parameter 1.3 1.1 °C/W ψJB Junction-to-board characterization parameter 19.9 19.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.3 8.5 °C/W RθJA (1) 6 Junction-to-ambient thermal resistance UNIT For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 6.5 Electrical Characteristics Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.8 5.6 mA 2 4 μA POWER SUPPLIES (VM, DVDD) EN/nFAULT = 1, nSLEEP = 1, No motor load IVM VM operating supply current IVMQ VM sleep mode supply current nSLEEP = 0 tSLEEP Sleep time nSLEEP = 0 to sleep-mode 120 μs tWAKE Wake-up time nSLEEP = 1 to output transition 0.8 1.2 ms tON Turn-on time VM > UVLO to output transition 0.8 1.2 ms VDVDD Internal regulator voltage 4.75 5 5.25 V 3.9 4.05 No external load, 6 V < VVM < 33 V No external load, VVM = 4.2 V V LOGIC-LEVEL INPUTS (STEP, DIR, nSLEEP) VIL Input logic-low voltage VIH Input logic-high voltage VHYS Input logic hysteresis IIL Input logic-low current VIN = 0 V IIH Input logic-high current VIN = 5 V 0 0.6 V 1.5 5.5 V 150 –1 mV 1 μA 100 μA TRI-LEVEL INPUT (M0) VI1 Input logic-low voltage Tied to GND VI2 Input Hi-Z voltage Hi-Z 1.8 0 VI3 Input logic-high voltage Tied to DVDD 2.7 IO Output pull-up current 2 0.6 V 2.2 V 5.5 10 V μA QUAD-LEVEL INPUT (M1) VI1 Input logic-low voltage Tied to GND 1 1.25 1.4 V Input Hi-Z voltage Hi-Z 1.8 2 2.2 V VI4 Input logic-high voltage Tied to DVDD 2.7 IIL Output pull-up current VI2 VI3 330kΩ ± 5% to GND 0 0.6 5.5 10 V V μA SEVEN-LEVEL INPUT (DECAY/TOFF) VI1 Voltage level 1 Tied to GND 0 0.1 V VI2 Voltage level 2 14.7kΩ ± 1% to GND 0.2 0.35 V VI3 Voltage level 3 44.2kΩ ± 1% to GND 0.55 0.8 V VI4 Voltage level 4 100kΩ ± 1% to GND 1 1.25 V VI5 Voltage level 5 249kΩ ± 1% to GND 1.5 1.75 V VI6 Voltage level 6 Hi-Z 2.1 2.4 V VI7 Voltage level 7 Tied to DVDD IIL Output pull-up current 3 5.5 22.5 V μA CONTROL INPUT/OUTPUT (EN/nFAULT) VOL Output Logic-low voltage RPD2 Internal Pull-down Resistance IL Leakage current 0 0.6 2 VEN/nFAULT = 5 V, FAULT condition V MΩ 375 μA 750 875 mΩ VVM = 24 V, TJ = 125 °C, IO = -0.5 A 1130 1350 mΩ VVM = 24 V, TJ = 150 °C, IO = -0.5 A 1250 1450 mΩ MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) VVM = 24 V, TJ = 25 °C, IO = -0.5 A RDS(ONH) High-side FET on resistance Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 7 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted. PARAMETER RDS(ONL) tSR TEST CONDITIONS MIN TYP MAX UNIT VVM = 24 V, TJ = 25 °C, IO = 0.5 A 750 875 mΩ Low-side FET on resistance VVM = 24 V, TJ = 125 °C, IO = 0.5 A 1130 1350 mΩ VVM = 24 V, TJ = 150 °C, IO = 0.5 A 1250 1450 mΩ Output slew rate VVM = 24 V, IO = 0.5 A, Between 10% and 90% 240 V/µs PWM CURRENT CONTROL (VREF) KV Transimpedance gain PWM off-time, mixed 30% decay tOFF PWM off-time, Smart tune dynamic decay VREF = 3 V 2.805 3 DECAY/TOFF = 14.7 kΩ to GND 7 DECAY/TOFF = 44.2 kΩ to GND 16 DECAY/TOFF = 100 kΩ to GND 32 DECAY/TOFF = 249 kΩ to GND 7 DECAY/TOFF = Hi-Z Current trip accuracy AOUT and BOUT current matching IO,CH μs 32 IO = 1 A, 10% to 20% current setting –15 15 IO = 1 A, 20% to 67% current setting –10 10 IO = 1 A, 68% to 100% current setting –6 6 –2.5 2.5 IO = 1 A V/A 16 DECAY/TOFF = Tied to DVDD ΔITRIP 3.195 % % PROTECTION CIRCUITS VM falling, UVLO falling 3.8 3.95 4.05 VM rising, UVLO rising 3.9 4.05 4.15 VUVLO VM UVLO lockout VUVLO,HYS Undervoltage hysteresis Rising to falling threshold IOCP Overcurrent protection Current through any FET tOCP Overcurrent deglitch time tRETRY Overcurrent retry time TOTSD Thermal shutdown Die temperature TJ THYS_OTSD Thermal shutdown hysteresis Die temperature TJ 100 V mV 1.7 A 150 1.8 μs 4 ms 165 180 20 °C °C 6.6 Indexer Timing Requirements Typical limits are at TJ = 25°C and VVM = 24 V. Over recommended operating conditions unless otherwise noted. NO. (1) 8 MIN 1 ƒSTEP Step frequency 2 tWH(STEP) Pulse duration, STEP high 970 MAX UNIT 500(1) kHz ns 3 tWL(STEP) Pulse duration, STEP low 970 ns 4 tSU(DIR, Mx) Setup time, DIR or MODEx to STEP rising 200 ns 5 tH(DIR, Mx) Hold time, DIR or MODEx to STEP rising 200 ns STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Figure 6-1. STEP and DIR Timing Diagram 6.7 Typical Characteristics Figure 6-2. Sleep Current over Supply Voltage Figure 6-3. Sleep Current over Temperature Figure 6-4. Operating Current over Supply Voltage Figure 6-5. Operating Current over Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 9 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 10 Figure 6-6. Low-Side RDS(ON) over Supply Voltage Figure 6-7. Low-Side RDS(ON) over Temperature Figure 6-8. High-Side RDS(ON) over Supply Voltage Figure 6-9. High-Side RDS(ON) over Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 7 Detailed Description 7.1 Overview The DRV8428 device is an integrated motor-driver solution for bipolar stepper motors. The device provides the maximum integration by integrating two N-channel power MOSFET H-bridges, current sense resistors and regulation circuitry, and a microstepping indexer. The DRV8428 is capable of supporting wide supply voltage range of 4.2 V to 33 V. DRV8428 provides an output current up to 1.7-A peak, 1-A full-scale, or 0.7-A root mean square (rms). The actual full-scale and rms current depends on the ambient temperature, supply voltage, and PCB thermal capability. The DRV8428 uses an integrated current-sense architecture which eliminates the need for two external power sense resistors, hence saving significant board space, BOM cost, design efforts and reduces significant power consumption. This architecture removes the power dissipated in the sense resistors by using a current mirror approach and using the internal power MOSFETs for current sensing. The current regulation set point is adjusted by the voltage at the VREF pin. A simple STEP/DIR interface allows for an external controller to manage the direction and step rate of the stepper motor. The internal microstepping indexer can execute high-accuracy micro-stepping without requiring the external controller to manage the winding current level. The indexer is capable of full step, half step, and 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, and 1/256 microstepping. High microstepping contributes to significant audible noise reduction and smooth motion. In addition to a standard half stepping mode, a noncircular half stepping mode is available for increased torque output at higher motor RPM. Stepper motor drivers need to re-circulate the winding current by implementing several types of decay modes. The DRV8428 comes with smart tune decay modes. The smart tune is an innovative decay mechanism that automatically adjusts for optimal current regulation performance agnostic of voltage, motor speed, variation and aging effects. Smart tune Ripple Control uses a variable off-time, ripple current control scheme to minimize distortion of the motor winding current. Smart tune Dynamic Decay uses a fixed off-time, dynamic fast decay percentage scheme to minimize distortion of the motor winding current while minimizing frequency content and significantly reducing design efforts. Along with this seamless, effortless automatic smart tune, DRV8428 also provides the traditional mixed decay mode. A low-power sleep mode is included which allows the system to save power when not actively driving the motor. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 11 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 7.2 Functional Block Diagram 7.3 Feature Description Table 7-1 lists the recommended external components for the DRV8428. 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Table 7-1. DRV8428 External Components COMPONENT PIN 1 PIN 2 CVM1 VM PGND RECOMMENDED One X7R, 0.01-µF, VM-rated ceramic capacitor CVM2 VM PGND CDVDD DVDD GND X7R, 0.47-µF to 1-µF, 6.3-V ceramic capacitor Bulk, VM-rated capacitor RREF1 VREF VCC RREF2 (Optional) VREF GND Resistor to limit chopping current. It is recommended that the value of parallel combination of RREF1 and RREF2 should be less than 50-kΩ. 7.3.1 Stepper Motor Driver Current Ratings Stepper motor drivers can be classified using three different numbers to describe the output current: peak, RMS, and full-scale. 7.3.1.1 Peak Current Rating The peak current in a stepper driver is limited by the overcurrent protection trip threshold IOCP. The peak current describes any transient duration current pulse, for example when charging capacitance, when the overall duty cycle is very low. In general the minimum value of IOCP specifies the peak current rating of the stepper motor driver. For the DRV8428, the peak current rating is 1.7A per bridge. 7.3.1.2 RMS Current Rating The RMS (average) current is determined by the thermal considerations of the IC. The RMS current is calculated based on the RDS(ON), rise and fall time, PWM frequency, device quiescent current, and package thermal performance in a typical system at 25°C. The actual operating RMS current may be higher or lower depending on heatsinking and ambient temperature. For the DRV8428, the RMS current rating is 0.7 A per bridge. 7.3.1.3 Full-Scale Current Rating The full-scale current describes the top of the sinusoid current waveform while microstepping. Because the sinusoid amplitude is related to the RMS current, the full-scale current is also determined by the thermal considerations of the device. The full-scale current rating is approximately √2 × IRMS for a sinusoidal current waveform, and IRMS for a square wave current waveform (full step). Full-scale current Output Current RMS current AOUT BOUT Step Input Figure 7-1. Full-Scale and RMS Current Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 13 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 7.3.2 PWM Motor Drivers The DRV8428 device has drivers for two full H-bridges to drive the two windings of a bipolar stepper motor. Figure 7-2 shows a block diagram of the circuitry. Figure 7-2. PWM Motor Driver Block Diagram 7.3.3 Microstepping Indexer Built-in indexer logic in the DRV8428 allows a number of different step modes. The M0 and M1 pins are used to configure the step mode as shown in Table 7-2. The settings can be changed on the fly. Table 7-2. Microstepping Settings 14 M0 M1 STEP MODE 0 0 Full step (2-phase excitation) with 100% current 0 330kΩ to GND Full step (2-phase excitation) with 71% current 1 0 Non-circular 1/2 step Hi-Z 0 1/2 step 0 1 1/4 step 1 1 1/8 step Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Table 7-2. Microstepping Settings (continued) M0 M1 Hi-Z 1 1/16 step STEP MODE 0 Hi-Z 1/32 step Hi-Z 330kΩ to GND 1/64 step Hi-Z Hi-Z 1/128 step 1 Hi-Z 1/256 step Table 7-3 shows the relative current and step directions for full-step (71% current), 1/2 step, 1/4 step and 1/8 step operation. Higher microstepping resolutions follow the same pattern. The AOUT current is the sine of the electrical angle and the BOUT current is the cosine of the electrical angle. Positive current is defined as current flowing from the xOUT1 pin to the xOUT2 pin while driving. At each rising edge of the STEP input the indexer travels to the next state in the table. The direction is shown with the DIR pin logic high. If the DIR pin is logic low, the sequence is reversed. Note If the step mode is changed on the fly while stepping, the indexer advances to the next valid state for the new step mode setting at the rising edge of STEP. The initial excitation state is an electrical angle of 45°, corresponding to 71% of full-scale current in both coils. This state is entered after power-up, after exiting logic undervoltage lockout, or after exiting sleep mode. Table 7-3. Relative Current and Step Directions 1/8 STEP 1/4 STEP 1/2 STEP 1 1 1 FULL STEP 71% 2 3 2 4 5 3 2 1 6 7 4 8 9 5 3 10 11 6 12 13 7 4 2 14 15 8 16 17 9 5 18 19 10 20 21 11 6 22 23 12 3 AOUT CURRENT (% FULL-SCALE) BOUT CURRENT (% FULL-SCALE) ELECTRICAL ANGLE (DEGREES) 0% 100% 0.00 20% 98% 11.25 38% 92% 22.50 56% 83% 33.75 71% 71% 45.00 83% 56% 56.25 92% 38% 67.50 98% 20% 78.75 100% 0% 90.00 98% -20% 101.25 92% -38% 112.50 83% -56% 123.75 71% -71% 135.00 56% -83% 146.25 38% -92% 157.50 20% -98% 168.75 0% -100% 180.00 -20% -98% 191.25 -38% -92% 202.50 -56% -83% 213.75 -71% -71% 225.00 -83% -56% 236.25 -92% -38% 247.50 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 15 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Table 7-3. Relative Current and Step Directions (continued) 1/8 STEP 1/4 STEP FULL STEP 71% 1/2 STEP 24 AOUT CURRENT (% FULL-SCALE) BOUT CURRENT (% FULL-SCALE) -98% 25 13 7 26 27 14 28 29 15 8 4 30 31 16 32 ELECTRICAL ANGLE (DEGREES) -20% 258.75 -100% 0% 270.00 -98% 20% 281.25 -92% 38% 292.50 -83% 56% 303.75 -71% 71% 315.00 -56% 83% 326.25 -38% 92% 337.50 -20% 98% 348.75 Table 7-4 shows the full step operation with 100% full-scale current. This stepping mode consumes more power than full-step mode with 71% current, but provides a higher torque at high motor RPM. Table 7-4. Full Step with 100% Current FULL STEP 100% 1 AOUT CURRENT (% FULL-SCALE) BOUT CURRENT (% FULL-SCALE) 100 100 ELECTRICAL ANGLE (DEGREES) 45 2 100 -100 135 3 -100 -100 225 4 -100 100 315 Table 7-5 shows the noncircular 1/2–step operation. This stepping mode consumes more power than circular 1/2-step operation, but provides a higher torque at high motor RPM. Table 7-5. Non-Circular 1/2-Stepping Current NON-CIRCULAR 1/2-STEP AOUT CURRENT (% FULL-SCALE) BOUT CURRENT (% FULL-SCALE) 1 0 100 ELECTRICAL ANGLE (DEGREES) 0 2 100 100 45 3 100 0 90 4 100 –100 135 5 0 –100 180 6 –100 –100 225 7 –100 0 270 8 –100 100 315 7.3.4 Controlling VREF with an MCU DAC In some cases, the full-scale output current may need to be changed between many different values, depending on motor speed and loading. The voltage of the VREF pin can be adjusted in the system to change the full-scale current. In this mode of operation, as the DAC voltage increases, the full-scale regulation current increases as well. For proper operation, the output of the DAC should not rise above 3V. 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Figure 7-3. Controlling VREF with a DAC Resource The VREF pin can also be adjusted using a PWM signal and low-pass filter. Figure 7-4. Controlling VREF With a PWM Resource 7.3.5 Current Regulation, Off-time and Decay Modes During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 7-6, Item 1. The current through the motor windings is regulated by an adjustable, off-time PWM current-regulation circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage, inductance of the winding, and the magnitude of the back EMF present. When the current hits the current regulation threshold, the bridge enters a decay mode for a period of time determined by the seven-level DECAY/ TOFF pin setting to decrease the current. After the off-time expires, the bridge is re-enabled, starting another PWM cycle. Figure 7-5. Current Chopping Waveform Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 17 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. The opposite FETs are turned on; as the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 7-6, item 2. In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 7-6, Item 3. The PWM chopping current is set by a comparator which monitors the voltage across the current sense MOSFETs in parallel with the low-side power MOSFETs. The current sense MOSFETs are biased with a reference current that is the output of a current-mode sine-weighted DAC whose full-scale reference current is set by the voltage at the VREF pin. The chopping current (IFS) can be calculated as IFS (A) = VREF (V) / KV (V/A) = VREF (V) / 3 (V/A). Figure 7-6. Decay Modes The decay mode and off time for each bridge is selected by setting the seven-level DECAY/TOFF pin as shown in Table 7-6. Table 7-6. Decay Mode Settings DECAY/TOFF DECAY MODE OFF TIME 0 Smart tune Ripple Control - 14.7kΩ to GND Mixed 30% Decay 7µs 44.2kΩ to GND 16µs 100kΩ to GND 32µs 249kΩ to GND Hi-Z Smart tune Dynamic Decay DVDD 18 7µs 16µs 32µs Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 7.3.5.1 Mixed Decay Increasing Phase Current (A) ITRIP tOFF tBLANK tOFF tBLANK tDRIVE Decreasing Phase Current (A) tDRIVE tDRIVE ITRIP tBLANK tDRIVE tFAST tBLANK tOFF tFAST tDRIVE tOFF Figure 7-7. Mixed Decay Mode Mixed decay begins as fast decay for 30% of tOFF, followed by slow decay for the remainder of tOFF. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 19 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 7.3.5.2 Smart tune Dynamic Decay The smart tune current regulation scheme is an advanced current-regulation control method compared to traditional fixed off-time current regulation schemes. Smart tune current regulation scheme helps the stepper motor driver adjust the decay scheme based on operating factors such as the ones listed as follows: • • • • • Motor winding resistance and inductance Motor aging effects Motor dynamic speed and load Motor supply voltage variation Low-current versus high-current dI/dt Increasing Phase Current (A) ITRIP tBLANK tBLANK tOFF tBLANK tOFF tDRIVE tDRIVE tDRIVE Decreasing Phase Current (A) ITRIP tBLANK tOFF tDRIVE tBLANK tDRIVE tBLANK tOFF tFAST tDRIVE tFAST Figure 7-8. Smart tune Dynamic Decay Mode Smart tune Dynamic Decay greatly simplifies the decay mode selection by automatically configuring the decay mode between slow, mixed, and fast decay. In mixed decay, smart tune dynamically adjusts the fast decay percentage of the total mixed decay time. This feature eliminates motor tuning by automatically determining the best decay setting that results in the lowest ripple for the motor. The decay mode setting is optimized iteratively each PWM cycle. If the motor current overshoots the target trip level, then the decay mode becomes more aggressive (add fast decay percentage) on the next cycle to prevent regulation loss. If a long drive time must occur to reach the target trip level, the decay mode becomes less aggressive (remove fast decay percentage) on the next cycle to operate with less ripple and more efficiently. On falling steps, smart tune Dynamic Decay automatically switches to fast decay to reach the next step quickly. Smart tune Dynamic Decay is optimal for applications that require minimal current ripple but want to maintain a fixed frequency in the current regulation scheme. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 7.3.5.3 Smart tune Ripple Control Increasing Phase Current (A) ITRIP IVALLEY tBLANK tBLANK tOFF tBLANK tOFF tDRIVE Decreasing Phase Current (A) tDRIVE tBLANK tOFF tDRIVE tDRIVE ITRIP IVALLEY tBLANK tOFF tBLANK tOFF tDRIVE tDRIVE tBLANK tOFF tDRIVE Figure 7-9. Smart tune Ripple Control Decay Mode Smart tune Ripple Control operates by setting an IVALLEY level alongside the ITRIP level. When the current level reaches ITRIP, instead of entering slow decay until the t OFF time expires, the driver enters slow decay until I VALLEY is reached. Slow decay operates similar to mode 1 in which both low-side MOSFETs are turned on allowing the current to recirculate. In this mode, tOFF varies depending on the current level and operating conditions. This method allows much tighter regulation of the current level increasing motor efficiency and system performance. Smart tune Ripple Control can be used in systems that can tolerate a variable off-time regulation scheme to achieve small current ripple in the current regulation. The ripple current in this decay mode is 7.5mA + 1% of the ITRIP at a specific microstep level. 7.3.5.4 Blanking time After the current is enabled (start of drive phase) in an H-bridge, the current sense comparator is ignored for a period of time (tBLANK) before enabling the current-sense circuitry. The blanking time also sets the minimum drive time of the PWM. The blanking time is approximately 1 µs. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 21 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 7.3.6 Linear Voltage Regulators A linear voltage regulator is integrated in the DRV8428. The DVDD regulator can be used to provide a reference voltage. DVDD can supply a maximum of 2mA load. For proper operation, bypass the DVDD pin to GND using a ceramic capacitor. The DVDD output is nominally 5-V. When the DVDD LDO current load exceeds 2mA, the output voltage drops significantly. Figure 7-10. Linear Voltage Regulator Block Diagram If a digital input must be tied permanently high (that is, M0, M1 or DECAY/TOFF), tying the input to the DVDD pin instead of an external regulator is preferred. This method saves power when the VM pin is not applied or in sleep mode: the DVDD regulator is disabled and current does not flow through the input pulldown resistors. For reference, logic level inputs have a typical pulldown of 200 kΩ. The nSLEEP pin cannot be tied to DVDD, else the device will never exit sleep mode. 7.3.7 Logic Level, tri-level, quad-level and seven-level Pin Diagrams Figure 7-11 shows the input structure for M0 pin. Figure 7-11. Tri-Level Input Pin Diagram Figure 7-12 shows the input structure for M1 pin. 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Figure 7-12. Quad-Level Input Pin Diagram Figure 7-13 shows the input structure for STEP, DIR and nSLEEP pins. Figure 7-13. Logic-Level Input Pin Diagram Figure 7-14 shows the input structure for DECAY/TOFF pin. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 23 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Figure 7-14. Seven-Level Input Pin Diagram 7.3.7.1 EN/nFAULT Pin The EN/nFAULT pin is used to enable the driver and also used for fault reporting. Figure 7-15 shows the internal circuitry connected to the EN/nFAULT pin. When the pin is intended to be used for both enabling the driver and fault reporting, the external R-C has to be connected. When the pin is only intended for enabling and disabling the driver, the R-C is not required. To enable the H-bridges, the pin must be driven high. Floating the pin or connecting the pin to ground forces the bridge to become high-Z. When a fault is detected, EN/nFAULT pin is forced low by turning on Q1 - which discharges the capacitor C1. The H-bridges are disabled when the voltage on the EN/nFAULT pin falls below the VIL threshold. The bridges stay disabled till the fault condition is removed or a second MCU pin directly applies a voltage higher than VIH to the EN/nFAULT pin. Thereafter, Q1 is turned off and C1 charges back through the resistor R1. The typical delay from EN/nFAULT rising edge to the enabling the H-bridges is 100µs. The time constant of R1 * C1 must be less than 20µs. Typical values of the resistors R2 and R3 are 16 kΩ and 2 MΩ respectively. When the EN/nFAULT pin is permanently tied high, a fault will cause additional leakage current due to Q1 being ON. 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Figure 7-15. EN/nFAULT Pin 7.3.8 Protection Circuits The DRV8428 is fully protected against supply undervoltage, output overcurrent, and device overtemperature events. 7.3.8.1 VM Undervoltage Lockout (UVLO) If at any time the voltage on the VM pin falls below the UVLO-threshold voltage for the voltage supply, all the outputs are disabled, and the EN/nFAULT pin is driven low. Normal operation resumes (motor-driver operation and EN/nFAULT released) when the VM undervoltage condition is removed. 7.3.8.2 Overcurrent Protection (OCP) An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this current limit persists for longer than the tOCP time, the FETs in both H-bridges are disabled and the EN/nFAULT pin is driven low. Normal operation resumes automatically (motor-driver operation and EN/nFAULT released) after the tRETRY time has elapsed and the fault condition is removed. 7.3.8.3 Thermal Shutdown (OTSD) If the die temperature exceeds the thermal shutdown limit (TOTSD) all MOSFETs in the H-bridge are disabled, and the EN/nFAULT pin is driven low. Normal operation resumes (motor-driver operation and the EN/nFAULT line released) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TOTSD – THYS_OTSD). 7.3.8.4 Fault Condition Summary Table 7-7. Fault Condition Summary FAULT CONDITION ERROR REPORT H-BRIDGE INDEXER LOGIC RECOVERY VM undervoltage (UVLO) VM < VUVLO EN/nFAULT Disabled Disabled Reset (VDVDD < 3.6 V) Automatic: VM > VUVLO Overcurrent (OCP) IOUT > IOCP EN/nFAULT Disabled Operating Operating Automatic retry: tRETRY Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 25 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Table 7-7. Fault Condition Summary (continued) FAULT CONDITION Thermal Shutdown (OTSD) TJ > TTSD ERROR REPORT H-BRIDGE EN/nFAULT Disabled INDEXER Operating LOGIC RECOVERY Operating Automatic: TJ < TOTSD THYS_OTSD 7.4 Device Functional Modes 7.4.1 Sleep Mode (nSLEEP = 0) The DRV8428 state is managed by the nSLEEP pin. When the nSLEEP pin is low, the DRV8428 enters a low-power sleep mode. In sleep mode, all the internal MOSFETs are disabled. The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device enters sleep mode. The device is brought out of sleep automatically if the nSLEEP pin is brought high. The tWAKE time must elapse before the device is ready for inputs. 7.4.2 Disable Mode (nSLEEP = 1, EN/nFAULT = 0/Hi-Z) The EN/nFAULT pin is used to enable or disable the DRV8428. When the EN/nFAULT pin is low or floating, the output drivers are disabled in the Hi-Z state. 7.4.3 Operating Mode (nSLEEP = 1, EN/nFAULT = 1) When the nSLEEP pin is high, the EN/nFAULT pin is 1, and VM > UVLO, the device enters the active mode. The tWAKE time must elapse before the device is ready for inputs. 7.4.4 Functional Modes Summary Table 7-8 lists a summary of the functional modes. Table 7-8. Functional Modes Summary CONDITION Sleep mode CONFIGURATIO H-BRIDGE N DVDD Regulator INDEXER Logic 4.2 V < VM < 33 V nSLEEP pin = 0 Disabled Disbaled Disabled Disabled Operating 4.2 V < VM < 33 V nSLEEP pin = 1 EN/nFAULT pin =1 Operating Operating Operating Operating Disabled 4.2 V < VM < 33 V nSLEEP pin = 1 EN/nFAULT pin = 0 or Hi-Z Disabled Operating Operating Operating 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV8428 is used in bipolar stepper motor control. 8.2 Typical Application The following design procedure can be used to configure the DRV8428. Figure 8-1. Typical Application Schematic (1/8 microstepping, smart tune Ripple Control Decay, HTSSOP package) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 27 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Figure 8-2. Typical Application Schematic (1/8 microstepping, smart tune Ripple Control Decay, WQFN package) 8.2.1 Design Requirements Table 8-1 lists the design input parameters for a typical application. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Supply voltage VM 24 V Motor winding resistance RL 5.6 Ω/phase Motor winding inductance Motor full step angle Target microstepping level 28 REFERENCE LL 3.4 mH/phase θstep 1.8°/step nm 1/8 step Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Table 8-1. Design Parameters (continued) DESIGN PARAMETER Target motor speed Target full-scale current REFERENCE EXAMPLE VALUE v 18.75 rpm IFS 500 mA 8.2.2 Detailed Design Procedure 8.2.2.1 Stepper Motor Speed The first step in configuring the DRV8428 requires the desired motor speed and microstepping level. If the target application requires a constant speed, then a square wave with frequency ƒstep must be applied to the STEP pin. If the target motor speed is too high, the motor does not spin. Make sure that the motor can support the target speed. Use Equation 1 to calculate ƒstep for a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep) ¦step VWHSV V v (rpm) u 360 (q / rot) Tstep (q / step) u nm (steps / microstep) u 60 (s / min) (1) The value of θstep can be found in the stepper motor data sheet, or written on the motor. For example, the motor in this application is required to rotate at 1.8°/step for a target of 18.75 rpm at 1/8 microstep mode. Using Equation 1, ƒstep can be calculated as 500 Hz. The microstepping level is set by the M0 and M1 pins and can be any of the settings listed in Table 8-2. Higher microstepping results in a smoother motor motion and less audible noise, but requires a higher ƒstep to achieve the same motor speed. Table 8-2. Microstepping Indexer Settings M0 M1 STEP MODE 0 0 Full step (2-phase excitation) with 100% current 0 330kΩ to GND Full step (2-phase excitation) with 71% current 1 0 Non-circular 1/2 step Hi-Z 0 1/2 step 0 1 1/4 step 1 1 1/8 step Hi-Z 1 1/16 step 0 Hi-Z 1/32 step Hi-Z 330kΩ to GND 1/64 step Hi-Z Hi-Z 1/128 step 1 Hi-Z 1/256 step 8.2.2.2 Current Regulation In a stepper motor, the full-scale current (IFS) is the maximum current driven through either winding. This quantity depends on the VREF voltage. The maximum allowable voltage on the VREF pin is 3 V for DRV8428. DVDD can be used to provide VREF through a resistor divider. During stepping, IFS defines the current chopping threshold (ITRIP) for the maximum current step. IFS (A) = VREF (V) / 3 (V/A) 8.2.2.3 Decay Modes The DRV8428 device supports three different decay modes, as shown inTable 7-6. When a motor winding current has hit the current chopping threshold (ITRIP), the DRV8428 places the winding in one of the three decay modes for tOFF. After tOFF, a new drive phase starts. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 29 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 8.2.2.4 Application Curves Figure 8-3. 1/8 Microstepping With smart tune Ripple Control Decay Figure 8-4. 1/8 Microstepping With smart tune Dynamic Decay Figure 8-5. 1/32 Microstepping With smart tune Ripple Control Decay 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Figure 8-6. 1/32 Microstepping With smart tune Dynamic Decay Figure 8-7. 1/256 Microstepping With smart tune Ripple Control Decay Figure 8-8. 1/256 Microstepping With smart tune Dynamic Decay Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 31 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 8.2.3 Thermal Application This section presents the power dissipation calculation and junction temperature estimation of the device. 8.2.3.1 Power Dissipation The total power dissipation constitutes of three main components - conduction loss (PCOND), switching loss (PSW) and power loss due to quiescent current consumption (PQ). 8.2.3.1.1 Conduction Loss The current path for a motor connected in full-bridge is through the high-side FET of one half-bridge and low-side FET of the other half-bridge. The conduction loss (PCOND) depends on the motor rms current (IRMS) and high-side (RDS(ONH)) and low-side (RDS(ONL)) on-state resistances as shown in Equation 2. PCOND = 2 x (IRMS)2 x (RDS(ONH) + RDS(ONL)) (2) The conduction loss for the typical application shown in Table 8-2 is calculated in Equation 3. PCOND = 2 x (IRMS)2 x (RDS(ONH) + RDS(ONL)) = 2 x (0.5-A / √2)2 x (0.75-Ω + 0.75-Ω) = 0.375-W (3) Note This power calculation is highly dependent on the device temperature which significantly effects the high-side and low-side on-resistance of the FETs. For more accurate calculation, consider the dependency of on-resistance of FETs with device temperature. 8.2.3.1.2 Switching Loss The power loss due to the PWM switching frequency depends on the slew rate (tSR), supply voltage, motor RMS current and the PWM switching frequency. The switching losses in each H-bridge during rise-time and fall-time are calculated as shown in Equation 4 and Equation 5. PSW_RISE = 0.5 x VVM x IRMS x tRISE_PWM x fPWM (4) PSW_FALL = 0.5 x VVM x IRMS x tFALL_PWM x fPWM (5) Both tRISE_PWM and tFALL_PWM can be approximated as VVM/ tSR. After substituting the values of various parameters, and assuming 30-kHz PWM frequency, the switching losses in each H-bridge are calculated as shown below PSW_RISE = 0.5 x 24-V x (0.5-A / √2) x (24-V / 240 V/µs) x 30-kHz = 0.013-W (6) PSW_FALL = 0.5 x 24-V x (2-A / √2) x (24-V / 240 V/µs) x 30-kHz = 0.013-W (7) The total switching loss for the stepper motor driver (PSW) is calculated as twice the sum of rise-time (PSW_RISE) switching loss and fall-time (PSW_FALL) switching loss as shown below PSW = 2 x (PSW_RISE + PSW_FALL) = 2 x (0.013-W + 0.013-W) = 0.052-W (8) Note The rise-time (tRISE) and the fall-time (tFALL) are calculated based on typical values of the slew rate (tSR). This parameter is expected to change based on the supply-voltage, temperature and device to device variation. The switching loss is directly proportional to the PWM switching frequency. The PWM frequency in an application will depend on the supply voltage, inductance of the motor coil, back emf voltage and OFF time or the ripple current (for smart tune ripple control decay mode). 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 8.2.3.1.3 Power Dissipation Due to Quiescent Current The power dissipation due to the quiescent current consumed by the power supply is calculated as shown below PQ = VVM x IVM (9) Substituting the values, quiescent power loss can be calculated as shown below PQ = 24-V x 3.8-mA = 0.0912-W (10) Note The quiescent power loss is calculated using the typical operating supply current (IVM) which is dependent on supply-voltage, temperature and device to device variation. 8.2.3.1.4 Total Power Dissipation The total power dissipation (PTOT) is calculated as the sum of conduction loss, switching loss and the quiescent power loss as shown in Equation 11. PTOT = PCOND + PSW + PQ = 0.375-W + 0.052-W + 0.0912-W = 0.5182-W (11) 8.2.3.2 Device Junction Temperature Estimation For an ambient temperature of TA and total power dissipation (PTOT), the junction temperature (TJ) is calculated as TJ = TA + (PTOT x RθJA) Considering a JEDEC standard 4-layer PCB, the junction-to-ambient thermal resistance (RθJA) is 46.4 °C/W for the HTSSOP package and 47 °C/W for the WQFN package. Assuming 25°C ambient temperature, the junction temperature for the HTSSOP package is calculated as shown below TJ = 25°C + (0.5182-W x 46.4°C/W) = 49.04 °C (12) The junction temperature for the WQFN package is calculated as shown below TJ = 25°C + (0.5182-W x 47°C/W) = 49.35 °C (13) Therefore, the HTSSOP and the WQFN packages result in almost identical junction temperature. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 33 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 9 Power Supply Recommendations The DRV8428 is designed to operate from an input voltage supply (VM) range from 4.2 V to 33 V. A 0.01-µF ceramic capacitor rated for VM must be placed at each VM pin as close to the DRV8428 as possible. In addition, a bulk capacitor must be included on VM. 9.1 Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: • • • • • • The highest current required by the motor system The power supply’s capacitance and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system will limit the rate current can change from the power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Parasitic Wire Inductance Motor Drive System VM + ± + Motor Driver GND Local Bulk Capacitor IC Bypass Capacitor Copyright © 2016, Texas Instruments Incorporated Figure 9-1. Example Setup of Motor Drive System With External Power Supply 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 10 Layout 10.1 Layout Guidelines The VM pin should be bypassed to PGND using a low-ESR ceramic bypass capacitor with a recommended value of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace or ground plane connection to the device PGND pin. The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an electrolytic capacitor. Bypass the DVDD pin to ground with a low-ESR ceramic capacitor. A value of 0.47 µF rated for 6.3 V is recommended. Place this bypassing capacitor as close to the pin as possible. The thermal PAD must be connected to system ground. 10.1.1 Layout Example Figure 10-1. HTSSOP Layout Example Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 35 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 Figure 10-2. WQFN Layout Example 36 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources 11.3 Trademarks All trademarks are the property of their respective owners. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 37 DRV8428 www.ti.com SLOSE54B – JUNE 2020 – REVISED MAY 2021 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DRV8428 PACKAGE OPTION ADDENDUM www.ti.com 27-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DRV8428PWPR ACTIVE HTSSOP PWP 16 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 8428 DRV8428RTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 8428 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
DRV8428RTER
物料型号:DRV8428 器件简介:DRV8428是一款集成电流感测功能的步进电机驱动器,具有1/256微步进功能、STEP/DIR接口和smart tune技术。 引脚分配:文档提供了详细的引脚分配表,包括HTSSOP和WQFN两种封装的引脚功能和类型。 参数特性:包括工作电压范围4.2V至33V,电流容量每桥可达1.7A峰值、1A全规模、0.7A有效值,以及多种保护特性,如欠压锁定、过流保护、热关断和故障条件输出。 功能详解:DRV8428具备PWM微步进、集成电流感测、smart tune衰减技术和混合衰减选项、可配置的PWM斩波截止时间、支持1.8V、3.3V、5.0V逻辑输入、低电流睡眠模式、展频时钟降低电磁干扰、小尺寸封装等特性。 应用信息:适用于打印机、扫描仪、舞台灯光设备、缝纫机、安防和监控摄像头、办公和家庭自动化、工厂自动化和机器人技术、医疗应用等。 封装信息:提供HTSSOP(16)和WQFN(16)两种封装选项,具体尺寸和信息见文档中的详细描述。
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DRV8428RTER
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  • 10+17.5507010+2.17720
  • 100+14.11050100+1.75040
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DRV8428RTER
  •  国内价格 香港价格
  • 3000+8.252513000+1.02372

库存:3393