DRV8702-Q1, DRV8703-Q1
DRV8702-Q1,
SLVSDR9E – OCTOBER
2016 – REVISEDDRV8703-Q1
JANUARY 2021
SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
www.ti.com
DRV870x-Q1 Automotive H-Bridge Gate Driver
1 Features
3 Description
•
The DRV870x-Q1 devices are small single H-bridge
gate drivers that use four external N-channel
MOSFETs targeted to drive a bidirectional brushedDC motor.
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature Grade 1: –40°C to +125°C
Ambient Operating Temperature
Functional Safety-Capable
– Documentation available to aid DRV8702-Q1
DRV8703-Q1 functional safety system design
Single H-Bridge Gate Driver
– Drives Four External N-Channel MOSFETs
– Supports 100% PWM Duty Cycle
5.5 to 45-V Operating Supply-Voltage Range
Three Control-Interface Options
– PH/EN, Independent H-Bridge, and PWM
Serial Interface for Configuration (DRV8703-Q1)
Smart Gate Drive Architecture
– Adjustable Slew-Rate Control
Independent Control of Each H-Bridge
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Current-Shunt Amplifier
Integrated PWM Current Regulation
Low-Power Sleep Mode
Protection Features
– Supply Undervoltage Lockout (UVLO)
– Charge-Pump Undervoltage (CPUV) Lockout
– Overcurrent Protection (OCP)
– Gate-Driver Fault (GDF)
– Thermal Shutdown (TSD)
– Watchdog Timer (DRV8703-Q1)
– Fault-Condition Output (nFAULT)
A PH/EN, independent H-Bridge, or PWM interface
allows simple interfacing to controller circuits. An
internal sense amplifier provides adjustable current
control. Integrated Charge-Pump allows for 100%
duty cycle support and can be used to drive external
reverse battery switch.
Independent Half Bridge mode allows sharing of half
bridges to control multiple DC motors sequentially in a
cost-efficient way. The gate driver includes circuitry to
regulate the winding current using fixed off-time PWM
current chopping.
The DRV870x-Q1 devices include Smart Gate Drive
technology to remove the need for any external gate
components (resistors and Zener diodes) while
protecting the external FETs. The Smart Gate Drive
architecture optimizes dead time to avoid any shootthrough conditions, provides flexibility in reducing
electromagnetic
interference
(EMI)
with
programmable slew-rate control and protects against
any gate-short conditions. Additionally, active and
passive pulldowns are included to prevent any dv/dt
gate turn on.
Device Information (1)
PART NUMBER
DRV8702-Q1
2 Applications
DRV8703-Q1
•
(1)
•
VQFN (32)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
5.5 to 45 V
DRV870x-Q1
PH/EN or PWM
nSLEEP
Controller
•
Power Window Lift, Sunroof, Seats, Sliding Door,
Trunk and Tailgate
Relay Replacement
– Application Report: SLVA837
– TI Design: TIDUCQ9
Brushed-DC Pumps
PACKAGE
H-Bridge Gate Driver
Gate
Drive
VREF
Sense Output
nFAULT
Shunt Amplifier
FETs
M
Current
Sense
Current Regulation
Protection
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 5
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................8
6.4 Thermal Information....................................................8
6.5 Electrical Characteristics.............................................8
6.6 SPI Timing Requirements......................................... 13
6.7 Switching Characteristics..........................................13
........................................................................................ 14
6.8 Typical Characteristics.............................................. 15
7 Detailed Description......................................................20
7.1 Overview................................................................... 20
7.2 Functional Block Diagram......................................... 21
7.3 Feature Description...................................................23
7.4 Device Functional Modes..........................................41
7.5 Programming............................................................ 41
7.6 Register Maps...........................................................43
8 Application and Implementation.................................. 49
8.1 Application Information............................................. 49
8.2 Typical Application.................................................... 49
9 Power Supply Recommendations................................53
9.1 Bulk Capacitance Sizing........................................... 53
10 Layout...........................................................................54
10.1 Layout Guidelines................................................... 54
10.2 Layout Example...................................................... 54
11 Device and Documentation Support..........................55
11.1 Documentation Support.......................................... 55
11.2 Related Links.......................................................... 55
11.3 Receiving Notification of Documentation Updates.. 55
11.4 Support Resources................................................. 55
11.5 Trademarks............................................................. 55
11.6 Electrostatic Discharge Caution.............................. 55
11.7 Glossary.................................................................. 55
12 Mechanical, Packaging, and Orderable
Information.................................................................... 55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2018) to Revision E (January 2021)
Page
• Added Functional Safety bullet........................................................................................................................... 1
Changes from Revision C (August 2018) to Revision D (December 2018)
Page
• Changed front page to remove second description............................................................................................ 1
• Deleted Gate-Drive Current figure ..................................................................................................................... 1
• Added SL2 pin to the continous shunt amplifier input pin voltage...................................................................... 7
• Added SL2 pin to the continous shunt amplifier input pin voltage...................................................................... 7
• Changed IN1 to IN1/PH and IN2 to IN2/EN .......................................................................................................8
• Changed MODE typical pulldown resistance .....................................................................................................8
• Added MODE typical pullup resistance.............................................................................................................. 8
• Changed Wording in VDS Configuration section .............................................................................................51
Changes from Revision B (March 2017) to Revision C (August 2018)
Page
• Changed the Features and Descriptions sections.............................................................................................. 1
• Changed the type of the SL2 pin from O to I in the Pin Functions table.............................................................5
• Changed SPI parameter name conventions.....................................................................................................13
• Changed the VDS(OCP) from 0.86 V to 0.96 V in the OCP Threshold Voltage graph.........................................15
• Changed the I(CHOP) equation in the Current Regulation and Current Chopping Configuration sections.........25
• Changed the current equation in the Amplifier Output (SO) section.................................................................26
• Changed the description of the WD_EN bit in the IDRIVE and WD Field Descriptions table...........................43
Changes from Revision A (November 2016) to Revision B (March 2017)
Page
• Changed the maximum voltage for AVDD from 5.7 to 5.75 in the Absolute Maximum Ratings table.............. 14
• Changed maximum VSP value for GAIN_CS = 00 and GAIN_CS = 10 for the DRV8703-Q1 amplifier gain
parameter in the Electrical Characteristics table.............................................................................................. 14
2
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•
•
•
•
DRV8702-Q1, DRV8703-Q1
SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
Added the R(VDRAIN) note to the External Components table........................................................................... 23
Changed one resistor value from 32 kΩ to 65 kΩ in the MODE Pin Block Diagram ....................................... 24
Changed what happens when a fault condition is no longer present in the Overcurrent Protection (OCP)
section.............................................................................................................................................................. 37
Deleted AV × from tthe I(CHOP) equation in the Current Chopping Configuration section.............................. 51
Changes from Revision * (October 2016) to Revision A (November 2016)
Page
• Released the full version of the data sheet ........................................................................................................1
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
NC
CPL
CPH
VCP
VM
VDRAIN
GH2
SH2
32
31
30
29
28
27
26
25
5 Pin Configuration and Functions
GND
1
24
GL2
IN1/PH
2
23
SL2
IN2/EN
3
22
SN
GND
4
21
SP
20
GL1
Thermal
Pad
16
GND
SO
GND
15
17
VREF
8
14
nSLEEP
AVDD
GH1
13
18
GND
7
12
GND
DVDD
SH1
11
19
MODE
6
10
VDS
nFAULT
5
9
IDRIVE
Not to scale
Figure 5-1. DRV8702-Q1 RHB Package With Wettable Flanks 32-Pin VQFN Top View
4
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NC
CPL
CPH
VCP
VM
VDRAIN
GH2
SH2
32
31
30
29
28
27
26
25
SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
GND
1
24
GL2
IN1/PH
2
23
SL2
IN2/EN
3
22
SN
SDO
4
21
SP
20
GL1
Thermal
Pad
15
16
SO
GND
VREF
17
14
8
AVDD
nSLEEP
13
GH1
GND
18
12
7
DVDD
SCLK
11
SH1
MODE
19
10
6
nFAULT
SDI
9
5
nWDFLT
nSCS
Not to scale
Figure 5-2. DRV8703-Q1 RHB Package With Wettable Flanks 32-Pin VQFN Top View
Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
DRV8702-Q1
DRV8703-Q1
AVDD
14
14
PWR
Analog regulator. This pin is the 5-V analog supply regulator. Bypass this pin to
ground with a 6.3-V, 1-µF ceramic capacitor.
CPH
30
30
PWR
Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the
supply voltage (VM) between the CPH and CPL pins.
CPL
31
31
PWR
Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the
supply voltage (VM) between the CPH and CPL pins.
DVDD
12
12
PWR
Logic regulator. This pin is the regulator for the 3.3-V logic supply. Bypass this
pin to ground with a 6.3-V, 1-µF ceramic capacitor.
GH1
18
18
O
High-side gate. Connect this pin to the high-side FET gate.
GH2
26
26
O
High-side gate. Connect this pin to the high-side FET gate.
GL1
20
20
O
Low-side gate. Connect this pin to the low-side FET gate.
GL2
24
24
O
GND
1
1
PWR
Device ground. Connect this pin to the system ground.
GND
13
13
PWR
Device ground. Connect this pin to the system ground.
GND
17
17
PWR
Device ground. Connect this pin to the system ground.
GND
4
—
PWR
Device ground. Connect this pin to the system ground.
GND
7
—
PWR
Device ground. Connect this pin to the system ground.
GND
9
—
PWR
Device ground. Connect this pin to the system ground.
IDRIVE
5
—
I
Current setting pin for the gate drive. The resistor value or voltage forced on
this pin sets the gate-drive current. For more information see the Section
8.2.2.2 section.
IN1/PH
2
2
I
Input control pins. The logic of this pin is dependent on the MODE pin. This pin
is connected to an internal pulldown resistor.
Low-side gate. Connect this pin to the low-side FET gate.
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
PIN
NAME
IN2/EN
DRV8702-Q1
DRV8703-Q1
3
3
TYPE(1)
DESCRIPTION
I
Input control pins. The logic of this pin is dependent on the MODE pin. This pin
is connected to an internal pulldown resistor.
Mode control pin. Pull this pin to logic low to use H-bridge operation. Pull this
pin to logic high for independent half-bridge operation. This pin is connected to
an internal resistor divider. Operation of this pin is latched on power up or when
exiting sleep mode. This pin is connected to an internal pullup and pulldown
resistors.
MODE
11
11
I
NC
32
32
NC
SCLK
—
7
I
SPI clock. This pin is for the SPI clock signal. This pin is connected to an
internal pulldown resistor.
SDI
—
6
I
SPI input. This pin is for the SPI input signal. This pin is connected to an
internal pulldown resistor.
SDO
—
4
OD
SPI output. This pin is for the SPI output signal. This pin is an open-drain
output that requires an external pullup resistor.
SH1
19
19
I
High-side source. Connect this pin to the high-side FET source.
SH2
25
25
I
High-side source. Connect this pin to the high-side FET source
SL2
23
23
I
Low-side source. Connect this pin to the low-side FET source.
SN
22
22
I
Shunt-amplifier negative input. Connect this pin to the current-sense resistor.
No connect. No internal connection.
SO
16
16
O
Shunt-amplifier output. The voltage on this pin is equal to the SP voltage times
AV plus an offset. Place no more than 1 nF of capacitance on this pin.
SP
21
21
I
Shunt-amplifier positive input. Connect this pin to the current-sense resistor.
VCP
29
29
PWR
VDRAIN
27
27
I
High-side FET drain connection. This pin is common for the two H-bridges.
VDS
6
—
I
VDS monitor setting pin. The resistor value or voltage forced on this pin sets
the VDS monitor threshold. For more information see the Section 8.2.2.3
section.
VM
28
28
PWR
VREF
15
15
I
nWDFLT
—
9
OD
Watchdog fault indication pin. This pin is pulled logic low when a watchdog fault
condition occurs. This pin is an open-drain output that requires an external
pullup resistor.
nFAULT
10
10
OD
Fault indication pin. This pin is pulled logic low when a fault condition occurs.
This pin is an open-drain output that requires an external pullup resistor.
nSCS
—
5
I
SPI chip select. This pin is the select and enable for SPI. This pin is active low.
nSLEEP
8
8
I
Device sleep mode. Pull this pin to logic low to put device into a low-power
sleep mode with the FETs in high impedance (Hi-Z). This pin is connected to an
internal pulldown resistor.
(1)
6
NO.
Charge-pump output. Connect a 16-V, 1-µF ceramic capacitor between this pin
and the VM pin.
Power supply. Connect this pin to the motor supply voltage. Bypass this pin to
ground with a 0.1-µF ceramic plus a 10-µF (minimum) capacitor.
Current set reference input. The voltage on this pin sets the driver chopping
current.
I = input, O = output, PWR = power, NC = no connect, OD = open-drain output
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
Power supply voltage
VM
–0.3
47
V
Charge pump voltage
VCP, CPH
–0.3
VVM + 12
V
Charge pump negative switching pin
CPL
–0.3
VVM
V
Internal logic regulator voltage
DVDD
–0.3
3.8
V
Internal analog regulator voltage
AVDD
–0.3
5.75
V
Drain pin voltage
VDRAIN
–0.3
47
V
–10
10
V
Voltage difference between supply and VDRAIN VM – VDRAIN
UNIT
Control pin voltage
IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE,
VDS, MODE, nSCS, SCLK, SDI, SDO,
nWDFLT
–0.3
5.75
V
High-side gate pin voltage
GH1, GH2
–0.3
VVM + 12
V
Low-side gate pin voltage
GL1, GL2
–0.3
12
V
Continuous phase-node pin voltage
SH1, SH2
–1.2
VVM + 1.2
V
Pulsed 10-µs phase-node pin voltage
SH1, SH2
–2
VVM + 2
V
SP, SL2
–0.5
1.2
V
SN
–0.3
0.3
V
Continuous shunt amplifier input pin voltage
Pulsed 10-µs shunt amplifier input pin voltage
SP, SL2
–1
1.2
V
Shunt amplifier output pin voltage
SO
–0.3
5.75
V
Shunt amplifier output pin current
SO
0
5
mA
Maximum current, limit current with external
series resistor
VDRAIN
–2
2
mA
Open-drain output current
nFAULT, SDO, nWDFLT
0
10
mA
Gate pin source current
GH1, GL1, GH2, GL2
0
250
mA
Gate pin sink current
GH1, GL1, GH2, GL2
0
500
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC
HBM ESD Classification Level 2
V(ESD)
(1)
Electrostatic
discharge
Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
UNIT
±2000
All pins
±500
Corner pins (1, 8, 9, 16, 17, 24, 25,
and 32)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
6.3 Recommended Operating Conditions
MIN
VVM
Power supply voltage
VCC
Logic-level input voltage
VM
VVREF
Current Shunt Amplifier Reference Voltage
VREF
f(PWM)
Applied PWM signal (IN1/IN2)
IN1, IN2
IAVDD
MAX
UNIT
5.5
45
V
0
5.25
V
0.3(1)
3.6
V
100
kHz
AVDD external load current
30(2)
mA
IDVDD
DVDD external load current
30(2)
mA
ISO
Shunt-amplifier output-current loading
5
mA
TA
Operating ambient temperature
125
°C
(1)
(2)
SO
–40
Operational at VVREF = 0 to approximately 0.3 V, but accuracy is degraded.
Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV870x-Q1
THERMAL METRIC(1)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
32.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
19.6
°C/W
RθJB
Junction-to-board thermal resistance
6.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
6.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
VVM
VM operating voltage
IVM
VM operating supply current
I(SLEEP)
VM sleep mode supply current
VDVDD
Internal logic regulator voltage
VAVDD
Internal logic regulator voltage
Gate drivers functional
5.5
45
Logic functional
4.5
45
VVM = 13.5 V; nSLEEP=1
5.5
7.5
12
nSLEEP = 0, VVM = 13.5 V, TA = 25°C
14
nSLEEP = 0, VVM = 13.5 V, TA = 125°C(1)
25
2-mA load
3
3.3
3.5
30-mA load, VVM = 13.5 V
2.9
3.2
3.5
2-mA load
4.7
5
5.3
30-mA load, VVM = 13.5 V
4.6
5
5.3
VVM = 13.5 V; IVCP = 0 to 12 mA
22.5
23.5
24.5
VVM = 8 V; IVCP = 0 to 10 mA
13.7
14
14.8
9.1
9.5
V
mA
µA
V
V
CHARGE PUMP (VCP, CPH, CPL)
VVCP
IVCP
VCP operating voltage
Charge-pump current capacity
VVM = 5.5 V; IVCP = 0 to 8 mA
8.9
VVM > 13.5 V
12
8 V < VVM < 13.5 V
10
5.5 V < VVM < 8 V
8
V
mA
CONTROL INPUTS (IN1/PH, IN2/EN, nSLEEP, MODE, nSCS, SCLK, SDI)
8
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
VIL
Input logic-low voltage
VIH
Vhys
TEST CONDITIONS
MIN
TYP
MAX
0
0.8
Input logic-high voltage
1.5
5.25
Input logic hysteresis
100
UNIT
V
V
mV
IIL
Input logic-low current
VIN = 0 V
IIH
Input logic-high current
VIN = 5 V
–5
RPD
Pulldown resistance
IN1/PH, IN2/EN, nSLEEP, nSCS, SCLK,
SDI
RPD
Pulldown resistance
MODE
65
kΩ
RPU
Pullup Resistance
MODE
26
kΩ
64
100
5
µA
70
µA
173
kΩ
CONTROL OUTPUTS (nFAULT, WDFAULT, SDO)
VOL
Output logic-low voltage
IO = 2 mA
IOZ
Output high-impedance leakage
5V pullup voltage
-2
0.1
V
2
µA
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
VGSH
VGSL
High-side VGS gate drive (gate-tosource)
Low-side VGS gate drive (gate-tosource)
IDRIVE(SRC_ High-side peak source current
(VVM = 5.5V)
HS)
IDRIVE(SNK_ High-side peak sink current
(VVM = 5.5V)
HS)
VVM > 13.5 V; VGSH with respect to SHx
10.5
11.5
VVM = 8 V; VGSH with respect to SHx
5.7
6.8
VVM = 5.5 V; VGSH with respect to SHx
3.4
4
VVM > 10.5 V
VVM < 10.5 V
10.5
VVM – 2
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
10
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
20
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
50
IDRIVE = 3’b011 (DRV8703)
70
IDRIVE = 3’b100 (DRV8703)
100
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
145
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
190
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
240
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
20
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
40
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
90
IDRIVE = 3’b011 (DRV8703)
120
IDRIVE = 3’b100 (DRV8703)
170
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
250
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
330
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
420
V
V
mA
mA
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
IDRIVE(SRC_ Low-side peak source current
(VVM = 5.5V)
LS)
IDRIVE(SNK_ Low-side peak sink current
(VVM = 5.5V)
LS)
IDRIVE(SRC_ High-side peak source current
(VVM = 13.5V)
HS)
10
TEST CONDITIONS
MIN
TYP
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
10
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
20
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
40
IDRIVE = 3’b011 (DRV8703)
55
IDRIVE = 3’b100 (DRV8703)
75
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
115
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
145
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
190
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
20
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
40
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
85
IDRIVE = 3’b011 (DRV8703)
115
IDRIVE = 3’b100 (DRV8703)
160
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
235
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
300
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
360
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
10
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
20
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
50
IDRIVE = 3’b011 (DRV8703)
70
IDRIVE = 3’b100 (DRV8703)
105
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
155
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
210
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
260
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MAX
UNIT
mA
mA
mA
Copyright © 2021 Texas Instruments Incorporated
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DRV8702-Q1, DRV8703-Q1
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
IDRIVE(SNK_ High-side peak sink current
(VVM = 13.5V)
HS)
IDRIVE(SRC_ Low-side peak source current
(VVM = 13.5V)
LS)
IDRIVE(SNK_ Low-side peak sink current
(VVM = 13.5V)
LS)
IHOLD
FET holding current
ISTRONG
FET holdoff strong pulldown
R(OFF)
FET gate holdoff resistor
TEST CONDITIONS
MIN
TYP
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
20
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
40
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
95
IDRIVE = 3’b011 (DRV8703)
130
IDRIVE = 3’b100 (DRV8703)
185
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
265
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
350
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
440
R(IDRIVE) < 1kΩ to GND (DRV8702) or
IDRIVE = 3’b000 (DRV8703)
10
R(IDRIVE) = 33kΩ to GND (DRV8702) or
IDRIVE = 3’b001 (DRV8703)
20
R(IDRIVE) = 200kΩ to GND (DRV8702) or
IDRIVE = 3’b010 (DRV8703)
45
IDRIVE = 3’b011 (DRV8703)
60
IDRIVE = 3’b100 (DRV8703)
90
R(IDRIVE) > 2MΩ to GND (DRV8702) or
IDRIVE = 3’b101 (DRV8703)
130
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or
IDRIVE = 3’b110 (DRV8703)
180
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or
IDRIVE = 3’b111 (DRV8703)
225
R(IDRIVE) < 1kΩ to GND (DRV8702-Q1) or
IDRIVE = 3’b000 (DRV8703-Q1)
20
R(IDRIVE) = 33 kΩ to GND (DRV8702-Q1)
or IDRIVE = 3’b001 (DRV8703-Q1)
40
R(IDRIVE) = 200 kΩ to GND (DRV8702-Q1)
or IDRIVE = 3’b010 (DRV8703-Q1)
95
IDRIVE = 3’b011 (DRV8703-Q1)
125
IDRIVE = 3’b100 (DRV8703-Q1)
180
R(IDRIVE) > 2 MΩ to GND (DRV8702-Q1)
or IDRIVE = 3’b101 (DRV8703-Q1)
260
R(IDRIVE) = 68 kΩ to AVDD (DRV8702-Q1)
or IDRIVE = 3’b110 (DRV8703-Q1)
350
R(IDRIVE) = 1 kΩ to AVDD (DRV8702-Q1)
or IDRIVE = 3’b111 (DRV8703-Q1)
430
Source current after tDRIVE
10
Sink current after tDRIVE
40
GHx
750
GLx
1000
Pulldown GHx to SHx
150
Pulldown GLx to GND
150
MAX
UNIT
mA
mA
mA
mA
mA
kΩ
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
VVREF
VREF input rms voltage
For current internal chopping
0.3(2)
3.6
V
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
RVREF
AV
VREF input impedance
MIN
1
DRV8703-Q1 VREF_SCL = 2’b01, 2’b10
or 2’b11
Amplifier gain (DRV8702-Q1)
AV
TEST CONDITIONS
DRV8702-Q1 and DRV8703-Q1
VREF_SCL = 00 (100%)
Amplifier gain (DRV8703-Q1)
TYP
MAX
MΩ
175
kΩ
60 < VSP < 225 mV; VSN = GND
19.3
19.8
20.3
GAIN_CS = 00; 10 < VSP < 450 mV; VSN
= GND
9.75
10
10.25
GAIN_CS = 01; 60 < VSP < 225 mV; VSN
= GND
19.3
19.8
20.3
GAIN_CS = 10; 10 < VSP < 112 mV; VSN =
GND
38.4
39.4
40.4
73
78
81
10
GAIN_CS = 11; 10 < VSP < 56 mV; VSN =
GND
UNIT
V/V
V/V
VIO
Input-referred offset
VSP = VSN = GND
5
VIO(DRIFT)
Drift offset(2)
VSP = VSN = GND
10
ISP
SP input current
VSP = 100 mV; VSN = GND
VSO
SO pin output voltage range
C(SO)
Allowable SO pin capacitance
–20
AV × Vio
mV
µV/°C
µA
4.5
V
1
nF
PROTECTION CIRCUITS
V(UVLO2)
VM undervoltage lockout
V(UVLO1)
Logic undervoltage lockout
Vhys(UVLO)
VM undervoltage hysteresis
V(CP_UV)
Charge pump undervoltage
VM falling; UVLO2 report
VM rising; UVLO2 recovery
5.65
100
V
V
mV
VVM + 1.5
V
VVM +
1.55
VCP rising; CPUV recovery
Vhys(CP_UV) CP undervoltage hysteresis
Rising to falling threshold
50
R(VDS) < 1 kΩ to GND
0.06
R(VDS) = 33 kΩ to GND
0.12
Overcurrent protection trip level, VDS
of each external FET (DRV8702-Q1) R(VDS) = 200 kΩ to GND
High side FETs: VDRAIN – SHx
R(VDS) > 2 MΩ to GND
Low side FETs: SHx – SP/SL2
R(VDS) = 68 kΩ to AVDD
mV
0.24
V
0.48
0.96
R(VDS) < 1 kΩ to AVDD
VDS(OCP)
5.45
5.4
4.5
Rising to falling threshold
VCP falling; CPUV report
VDS(OCP)
5.25
Disabled
VDS_LEVEL = 3’b000
0.06
VDS_LEVEL = 3’b001
0.145
VDS_LEVEL = 3’b010
Overcurrent protection trip level, VDS
VDS_LEVEL
= 3’b011
of each external FET (DRV8703-Q1)
High-side FETs: VDRAIN – SHx
VDS_LEVEL = 3’b100
Low-side FETs: SHx – SP/SL2
VDS_LEVEL = 3’b101
0.17
0.2
V
0.12
0.24
VDS_LEVEL = 3’b110
0.48
VDS_LEVEL = 3’b111
0.96
VSP(OCP)
Overcurrent protection trip level,
measured by sense amplifier
VSP with respect to GND
0.8
1
1.2
V
T(OTW)
Thermal warning temperature(1)
Die temperature TJ
120
135
145
°C
Die temperature TJ
150
temperature(1)
TSD
Thermal shutdown
Thys
Thermal shutdown hysteresis(1)
12
Die temperature TJ
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°C
20
°C
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER
VC(GS)
(1)
(2)
TEST CONDITIONS
Positive clamping voltage
Gate-drive clamping voltage
Negative clamping voltage
MIN
TYP
MAX
16.3
17
17.8
–1
–0.7
–0.5
UNIT
V
Ensured by design and characterization data.
Operational at VVREF = 0 to approximately 0.3 V, but accuracy is degraded.
6.6 SPI Timing Requirements
MIN
t(CLK)
Minimum SPI clock period
t(CLKH)
Clock high time
NOM
MAX
UNIT
100
ns
50
ns
t(CLKL)
Clock low time
50
ns
t(SU_SDI)
SDI input data setup time
20
ns
t(HD_SDI)
SDI input data hold time
30
ns
t(HD_SDO)
SDO output hold time
40
ns
t(SU_SCS)
SCS setup time
50
ns
t(HD_SCS)
SCS hold time
50
ns
t(HI_SCS)
SCS minimum high time before SCS active low
400
ns
6.7 Switching Characteristics
Over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
t(SLEEP)
Sleep time
nSLEEP = low to sleep mode
100
µs
t(wu)
Wake-up time
nSLEEP = high to output change
1
ms
ton
Turn on time
VM > UVLO2 to output transition
1
ms
700
kHz
CHARGE PUMP (VCP, CPH, CPL)
fS(VCP)
Charge-pump switching frequency
VM > UVLO2
200
400
CONTROL INPUTS (IN1, IN2, nSLEEP, MODE, nSCS, SCLK, SDI, PH, EN)
tpd
Propagation delay
IN1, IN2 to GHx or GLx
500
ns
Observed t(DEAD) depends on
IDRIVE setting
240
ns
TDEAD = 2’b00; Observed t(DEAD)
depends on IDRIVE setting
120
TDEAD = 2’b01; Observed t(DEAD)
depends on IDRIVE setting
240
TDEAD = 2’b10; Observed t(DEAD)
depends on IDRIVE setting
480
TDEAD = 2’b11; Observed t(DEAD)
depends on IDRIVE setting
960
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
t(DEAD)
t(DEAD)
t(DRIVE)
Output dead time (DRV8702-Q1)
Output dead time (DRV8703-Q1)
Gate drive time
ns
2.5
µs
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
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13
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
Over recommended operating conditions unless otherwise noted
PARAMETER
tS
Settling time to
toff
TEST CONDITIONS
±1%(1)
MIN
VSP = VSN = GND to VSP = 120 mV,
VSN = GND, AV= 20; C(SO) = 200 pF
1
VSP = VSN = GND to VSP = 60 mV,
VSN = GND, AV= 40; C(SO) = 200 pF
2
VSP = VSN = GND to VSP = 30 mV,
VSN = GND, AV= 80; C(SO) = 200 pF
4
t(BLANK)
PWM blanking time
UNIT
µs
25
TOFF = 00
PWM off-time (DRV8703-Q1)
MAX
0.5
PWM off-time (DRV8702-Q1)
toff
TYP
VSP = VSN = GND to VSP = 240 mV,
VSN = GND, AV= 10; C(SO) = 200 pF
µs
25
TOFF = 01
50
TOFF = 10
100
TOFF = 11
200
µs
2
µs
10
µs
PROTECTION CIRCUITS
t(UVLO)
VM UVLO falling deglitch time
VM falling; UVLO report
t(OCP)
Overcurrent deglitch time
3.7
4
4.3
µs
t(RETRY)
Overcurrent retry time
2.8
3
3.2
ms
WD_DLY = 2’b00
t(WD)
Watchdog time out (DRV8703-Q1)
t(RESET)
Watchdog timer reset period
10
WD_DLY = 2’b01
20
WD_DLY = 2’b10
50
WD_DLY = 2’b11
100
ms
64
µs
SPI
t(SPI_READY) SPI read after power on
VM > VUVLO1
5
10
ms
30
ns
td(SDO)
SDO output data delay time, CLK
high to SDO valid
ta
SCS access time, SCS low to SDO
out of high impedance
10
ns
tdis
SCS disable time, SCS high to SDO
high impedance
10
ns
(1)
14
CL = 20 pF
Ensured by design
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
8.4
8.4
8.1
8.1
7.8
7.8
Supply Current (mA)
Supply Current (mA)
6.8 Typical Characteristics
7.5
7.2
6.9
TA = 40qC
TA = 25qC
TA = 125qC
6.6
10
15
20
25
30
Supply Voltage (V)
35
40
7.2
6.9
6.3
-50
45
-25
0
D001
25
50
Temperature (qC)
75
100
125
D002
Figure 6-2. Supply Current vs Temperature
Figure 6-1. Supply Current vs Supply Voltage (VM)
21
21
TA = 40qC
TA = 25qC
TA = 125qC
19
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
19
17
Sleep Current (PA)
Sleep Current (PA)
7.5
6.6
6.3
5
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
15
13
11
9
17
15
13
11
9
7
5
10
15
20
25
30
Supply Voltage (V)
35
40
7
-50
45
-25
0
D003
Figure 6-3. Sleep Current vs Supply Voltage (VM)
25
50
Temperature (qC)
75
100
125
D004
Figure 6-4. Sleep Current vs Temperature
5.1
3.4
TA = 40qC
TA = 25qC
TA = 125qC
3.35
5.05
AVDD (V)
DVDD (V)
3.3
3.25
5
3.2
4.95
TA = 40qC
TA = 25qC
TA = 125qC
3.15
3.1
4.9
5
10
15
20
25
30
Supply Voltage (V)
35
2-mA load
40
45
5
10
15
D005
20
25
30
Supply Voltage (V)
35
40
45
D006
2-mA load
Figure 6-5. DVDD Regulator
Figure 6-6. AVDD Regulator
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
3.26
5.1
3.24
5
3.22
4.9
4.8
AVDD (V)
DVDD (V)
3.2
3.18
3.16
3.14
4.7
4.6
4.5
4.4
3.12
4.3
TA = 40qC
TA = 25qC
TA = 125qC
3.1
3.08
5
10
15
20
25
30
Supply Voltage (V)
35
40
TA = 40qC
TA = 25qC
TA = 125qC
4.2
4.1
45
5
30-mA load
40
45
50
D008
19.9
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
19.84
Amplifier Gain (V/V)
9.98
Amplifier Gain (V/V)
20
25
30
35
Supply Voltage (V)
Figure 6-8. AVDD Regulator
10
9.96
9.94
19.78
19.72
19.66
9.92
-25
0
25
50
Temperature (qC)
75
100
19.6
-50
125
-25
0
25
50
Temperature (qC)
75
100
125
D010
D009
19.8-V/V gain
10-V/V gain
Figure 6-10. Amplifier Gain
Figure 6-9. Amplifier Gain
40
79
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
78.8
78.6
Amplifier Gain (V/V)
39.8
Amplifier Gain (V/V)
15
30-mA load
Figure 6-7. DVDD Regulator
9.9
-50
10
D007
39.6
39.4
78.4
78.2
78
77.8
77.6
77.4
39.2
77.2
39
-50
-25
0
25
50
Temperature (qC)
75
125
77
-50
-25
D011
0
25
50
Temperature (qC)
75
100
125
D012
78-V/V gain
39.4-V/V gain
Figure 6-11. Amplifier Gain
16
100
Figure 6-12. Amplifier Gain
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
0.1
0.18
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.09
0.16
VDS Setting (V)
VDS Setting (V)
0.08
0.07
0.06
0.05
0.15
0.14
0.13
0.12
0.04
0.11
0.03
-50
-25
0
25
50
Temperature (qC)
75
100
0.1
-50
125
0
25
50
Temperature (qC)
75
100
125
D014
VDS(OCP) = 0.12 V
Figure 6-14. OCP Threshold Voltage
Figure 6-13. OCP Threshold Voltage
0.19
0.27
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.26
VDS Setting (V)
0.18
VDS Setting (V)
-25
D013
VDS(OCP) = 0.06 V
0.17
0.16
0.15
0.25
0.24
0.23
0.22
0.14
-50
-25
0
25
50
Temperature (qC)
75
100
0.21
-50
125
75
100
125
D016
1
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.99
0.495
0.98
VDS Setting (V)
0.49
0.485
0.48
0.475
0.47
0.97
0.96
0.95
0.465
0.46
0.94
0.455
0.45
-50
25
50
Temperature (qC)
Figure 6-16. OCP Threshold Voltage
0.51
0.5
0
VDS(OCP) = 0.24 V
Figure 6-15. OCP Threshold Voltage
0.505
-25
D015
VDS(OCP) = 0.17 V
VDS Setting (V)
VVM = 5.5 V
VVM = 13.5 V
VVM = 45 V
0.17
-25
0
25
50
Temperature (qC)
75
100
VDS(OCP) = 0.48 V
125
0.93
-50
-25
D017
0
25
50
Temperature (qC)
75
100
125
D018
VDS(OCP) = 0.96 V
Figure 6-17. OCP Threshold Voltage
Figure 6-18. OCP Threshold Voltage
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SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
300
500
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
250
3'b101
3'b100
3'b011
3'b010
400
350
IDRIVE (mA)
200
IDRIVE (mA)
3'b111
3'b110
450
150
100
300
250
200
150
100
50
50
0
-50
-25
0
25
50
Temperature (qC)
75
100
0
-50
125
-25
0
D019
VVM = 5.5 V
25
50
Temperature (qC)
75
100
125
D020
VVM = 5.5 V
Figure 6-19. High-Side Source Current
Figure 6-20. High-Side Sink Current
250
450
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
400
200
3'b101
3'b100
3'b011
3'b010
350
IDRIVE (mA)
IDRIVE (mA)
300
150
100
250
200
150
100
50
50
0
-50
-25
0
25
50
Temperature (qC)
75
100
0
-50
125
0
25
50
Temperature (qC)
75
100
125
D022
VVM = 5.5 V
VVM = 5.5 V
Figure 6-22. Low-Side Sink Current
Figure 6-21. Low-Side Source Current
350
550
3'b111
3'b110
300
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
500
3'b101
3'b100
3'b011
3'b010
450
400
IDRIVE (mA)
250
IDRIVE (mA)
-25
D021
200
150
100
350
300
250
200
150
100
50
50
0
-50
-25
0
25
50
Temperature (qC)
75
100
0
-50
-25
D023
0
25
50
Temperature (qC)
75
100
125
D024
VVM = 13.5 V
VVM = 13.5 V
Figure 6-23. High-Side Source Current
18
125
Figure 6-24. High-Side Sink Current
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300
550
3'b111
3'b110
3'b101
3'b100
3'b011
3'b010
3'b111
3'b110
500
250
3'b101
3'b100
3'b011
3'b010
450
400
IDRIVE (mA)
IDRIVE (mA)
200
150
100
350
300
250
200
150
100
50
50
0
-50
-25
0
25
50
Temperature (qC)
75
100
125
0
-50
-25
D025
VVM = 13.5 V
0
25
50
Temperature (qC)
75
100
125
D026
VVM = 13.5 V
Figure 6-25. Low-Side Source Current
Figure 6-26. Low-Side Sink Current
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7 Detailed Description
7.1 Overview
DRV87002-Q1 and DRV87003-Q1 are single H-bridge drivers, also referred to as gate controllers. The drivers
control four external NMOS FETs used to drive a bi-directional brushed-DC motors. The devices can also
operate in independent half bridge mode to drive two single directional brushed-DC motors.
The devices can support supply voltages from 5.5 V to 45 V and have a low power sleep mode enabled through
the nSLEEP pin. There are three options for the interface modes including a configurable PH/EN, independent
H-bridge control, or PWM interface. This allows easy interfacing to the controller circuit.
DRV87002-Q1 and DRV87003-Q1 include Smart Gate Drive technology which offers a combination of protection
features and gate-drive configurability to improve design simplicity and bring a new level of intelligence to motor
systems. The gate-drive strength, or gate-drive current can be adjusted through the driver itself to optimize for
different FETs and applications without the need for external resistors. Smart Gate Drive significantly reduces the
component count of discrete motor-driver systems by integrating the required FET drive circuitry into a single
device. The peak current can be adjusted through the IDRIVE pin for DRV8702-Q1 and through SPI for
DRV8703-Q1. Both the high-side and low-side FETs are driven with a gate source voltage (VGS) of 10.5 V
(nominal) when the VM voltage is more than 13.5 V. At lower VM voltages, the VGS is reduced. The high-side
gate drive voltage is generated using a doubler-architecture charge pump that regulates to the VM + 10.5 V.
The inrush or start up current and running current can be limited through a built in fixed time-off current chopping
scheme. The chopping current level is set through the sense resistor by setting a voltage on the VREF pin. See
the current regulation section for more information. A shunt-amplifier is also included in the devices to provide
accurate current measurements to the system controller. The SO pin outputs a voltage that is approximately 20
times the voltage across the sense resistor on the DRV8702-Q1 device. For the DRV8703-Q1, this gain is
configurable.
The DRV870x-Q1 device also has protection features beyond traditional discrete implementations including:
undervoltage lockout (UVLO), overcurrent protection (OCP), gate driver faults, and thermal shutdown (TSD).
The device integrates a spread spectrum clocking feature for both the internal digital oscillator and internal
charge pump. This feature combined with output slew rate control minimizes the radiated emissions from the
device.
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7.2 Functional Block Diagram
VM
0.1 …F
VM
10 µF
(minimum)
VM
VM
Gate Driver
Power
VDRAIN
1 µF
VVCP
VCP
GH1
HS
CPH
Charge Pump
SH1
VGLS
0.1 µF
CPL
DVDD
GL1
LS
3.3-V LDO
Logic
1 µF
VM
AVDD
BDC
5-V LDO
Gate Driver
VVCP
1 µF
VGLS LDO
GH2
HS
SH2
VGLS
IN1/PH
GL2
LS
IN2/EN
SL2
nSLEEP
Current Regulation
Control Inputs
SP
MODE
+
IDRIVE
RIDRIVE
R(SENSE)
AV
SN
±
VDS
SO
RVDS
VREF
nFAULT
Output
PAD
PAD
PAD
Figure 7-1. DRV8702-Q1 Functional Block Diagram
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VM
VM
VM
0.1 …F
10 µF
(minimum)
VM
Power
1 µF
VCP
VDRAIN
Gate Driver
VVCP
CPH
Charge Pump
GH1
HS
0.1 µF
CPL
SH1
VGLS
DVDD
GL1
LS
3.3-V LDO
1 µF
Logic
AVDD
5-V LDO
VM
Gate Driver
VVCP
1 µF
VGLS LDO
BDC
GH2
HS
IN1/PH
SH2
VGLS
GL2
LS
IN2/EN
SL2
Control Inputs
nSLEEP
Current Regulation
SP
MODE
Outputs
R(SENSE)
AV
+
-
nFAULT
SN
SO
nWDFLT
VREF
SCLK
SPI
SDI
SDO
nSCS
PAD
PAD
PAD
Copyright © 2017, Texas Instruments Incorporated
Figure 7-2. DRV8703-Q1 Functional Block Diagram
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7.3 Feature Description
Table 7-1 and Table 7-2 list the recommended external components for the device.
Table 7-1. External Components
(1)
(2)
COMPONENT
PIN 1
PIN 2
RECOMMENDED
C(VM1)
VM
GND
0.1-µF ceramic capacitor rated for VM
C(VM2)
VM
GND
≥ 10-µF electrolytic capacitor rated for VM
C(VCP)
VCP
VM
16-V, 1-µF ceramic capacitor
C(SW)
CPH
CPL
0.1-µF X7R capacitor rated for VM
C(DVDD)
DVDD
GND
6.3-V, 1-µF ceramic capacitor
C(AVDD)
AVDD
GND
6.3-V, 1-µF ceramic capacitor
R(IDRIVE)
IDRIVE
GND
For resistor sizing, see the Section 8.2 section
R(VDS)
VDS
GND
For resistor sizing, see the Section 8.2 section
R(nFAULT)
VCC (1)
nFAULT
≥ 10 kΩ
R(nWDFLT)
(1)
nWDFLT
≥ 10 kΩ
R(SENSE)
VCC
SP
SN or GND
Optional low-side sense resistor
R(VDRAIN) (2)
VDRAIN
VM
100-Ω series resistor
The VCC pin is not a pin on the DRV870x-Q1, but a VCC supply voltage pullup is required for open-drain outputs nFAULT. These pins
can be pulled up to either AVDD or DVDD.
The R(VDRAIN) resistor should be used between the VDRAIN and VM pins to minimize current to the VDRAIN pin if no external reverse
battery protection is implemented on the VDRAIN pin.
Table 7-2. External Gates
COMPONENT
GATE
DRAIN
SOURCE
Q(HS1)
GH1
VM
SH1
Q(LS1)
GL1
SH1
SP or GND
Q(HS2)
GH2
VM
SH2
Q(LS2)
GL2
SH2
SP or GND
RECOMMENDED
Supports FETs up to 200 nC at 40 kHz
PWM
For more information, see Section 8
7.3.1 Bridge Control
The DRV870x-Q1 device is controlled using a configurable input interface. The Section 7.3.1.1 section provides
the full H-bridge state . These tables do not consider the current control built into the DRV870x-Q1 device.
Positive current is defined in the direction of SH1 → SH2. The logic operation set by the MODE pin is latched on
power-up or when exiting sleep mode.
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VM
VM
1 Reverse drive
1 Forward drive
2 Slow decay (brake)
1
SH2
SH1
3 High-Z (coast)
2 Slow decay (brake)
1
SH2
SH1
2
2
3
3
3 High-Z (coast)
Figure 7-3. Bridge Control
7.3.1.1 Logic Tables
Table 7-3, Table 7-4, and Table 7-5 are the device logic tables. An X denotes a don’t care input or output.
Table 7-3. DRV870x-Q1 PH and EN Control Interface (MODE = 0)
nSLEEP
IN1/PH
IN2/EN
GH1
GL1
SH1
GH2
GL2
SH2
AVDD/DVDD
DESCRIPTION
0
X
X
X
X
Hi-Z
X
X
Hi-Z
Disabled
Sleep mode H bridge disabled Hi-Z
1
X
0
0
1
L
0
1
L
Enabled
Brake low-side slow decay
1
0
1
0
1
L
1
0
H
Enabled
Reverse (Current SH2 → SH1)
1
1
1
1
0
H
0
1
L
Enabled
Forward (Current SH1 → SH2)
nSLEEP
IN1/PH
IN2/EN
GH1
GL1
SH1
GH2
GL2
SH2
AVDD/DVDD
DESCRIPTION
0
X
X
X
X
Hi-Z
X
X
Hi-Z
Disabled
Sleep mode H bridge disabled Hi-Z
1
X
0
X
X
X
0
1
L
Enabled
Half-bridge 2 low side on
1
X
1
X
X
X
1
0
H
Enabled
Half-bridge 2 high side on
1
0
X
0
1
L
X
X
X
Enabled
Half-bridge 1 low side on
1
1
X
1
0
H
X
X
X
Enabled
Half-bridge 1 high side on
nSLEEP
IN1/PH
IN2/EN
GH1
GL1
SH1
GH2
GL2
SH2
AVDD/DVDD
DESCRIPTION
0
X
X
X
X
Hi-Z
X
X
Hi-Z
Disabled
Sleep mode H bridge disabled Hi-Z
1
0
0
0
0
Hi-Z
0
0
Hi-Z
Enabled
Coast H bridge disabled Hi-Z
1
0
1
0
1
L
1
0
H
Enabled
Reverse (Current SH2 → SH1)
1
1
0
1
0
H
0
1
L
Enabled
Forward (Current SH1 → SH2)
1
1
1
0
1
L
0
1
L
Enabled
Brake low-side slow decay
Table 7-4. DRV870x-Q1 Independent PWM Control Interface (MODE = 1)
Table 7-5. DRV870x-Q1 Standard PWM Control Interface (MODE = Hi-Z)
7.3.2 MODE Pin
The MODE pin of the device determines the control interface and latches on power-up or when exiting sleep
mode. Figure 7-4 shows an overview of the internal circuit of the MODE pin.
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DVDD
+
1.35 V
±
Digital
Core
26 k
MODE
+
65 k
0.75 V
±
Figure 7-4. MODE Pin Block Diagram
Table 7-6 lists the different control interfaces that can be set via MODE pin at power-up or when exiting sleep
mode.
Table 7-6. MODE Pin Configuration
MODE
CONTROL INTERFACE
0
PH or EN
1
Independent half-bridge
Hi-Z
PWM
During the device power-up sequence, the DVDD pin is enabled first. Then the MODE pin latches. Finally the
AVDD pin is enabled. For setting PWM control interface, TI does not recommended connecting the MODE pin to
the AVDD pin. Instead the MODE pin should be connected to an external 5-V or 3.3-V supply or to the DVDD pin
if not driven by an external microcontroller (MCU).
7.3.3 nFAULT Pin
The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. When a fault is
detected, the nFAULT line is logic low.
Output
nFAULT
Figure 7-5. nFAULT Block Diagram
For a 3.3-V pullup the nFAULT pin can be tied to the DVDD pin with a resistor (refer to the Section 8 section).
For a 5-V pullup an external 5-V supply should be used. TI does not recommended connecting the nFAULT pin
to the AVDD pin.
7.3.4 Current Regulation
The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation or
current chopping. When an H-bridge is enabled in forward or reverse drive, current rises through the winding at a
rate dependent on the DC voltage and inductance of the winding. When the current hits the current chopping
threshold, the bridge enters a brake (low-side slow decay) mode until the toff time expires.
Note
Immediately after the current is enabled, the voltage on the SP pin is ignored for a period (t(BLANK))
before enabling the current-sense circuitry.
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The PWM chopping current is set by a comparator that compares the voltage across a current-sense resistor
connected to the SP pin, multiplied by a factor of AV, with a reference voltage from the VREF pin. The factor AV
is the shunt-amplifier gain, which is 19.8 V/V for the DRV8702-Q1 device or configurable to 10, 19.8, 39.4, or 78
V/V for the DRV8703-Q1 device.
Use Equation 1 to calculate the chopping current (ICHOP).
I(CHOP)
VVREF VIO u A V
A V u R(SENSE)
(1)
For example, if a 50-mΩ sense resistor and a VREF value of 3.3 V are selected, the full-scale chopping current
is 3.28 A. The AV is 19.8 V/V and VIO is assumed to be 50 mV in this example.
For DC motors, current regulation is used to limit the start-up and stall current of the motor. If the current
regulation feature is not needed, it can be disabled by tying the VREF pin directly to the AVDD pin. If the
independent PWM control-interface mode (MODE pin is 1) is selected for operation, the device does not perform
PWM current regulation or current chopping.
7.3.5 Amplifier Output (SO)
The SO pin on the DRV870x-Q1 device outputs an analog voltage equal to the voltage across the SP and SN
pins multiplied by AV. The SO voltage is only valid for forward or reverse drive. Use Equation 2 to calculate the
approximate current for the H-bridge.
I
VSO VIO u A V
A V u R(SENSE)
(2)
When the SP and SN voltages are 0 V, the SO pin outputs the amplifier offset voltage times the amplifier gain,
Vio × Av. When SP minus SN is greater than 0 V, the SO pin outputs the sum of the amplifier offset voltage and
the sense resist or voltage, times the amplifier gain, (Vio + Vrsense) × Av. No capacitor is required on the SO pin.
AVDD
SO (V)
AV
VIO × AV
SP-SN (V)
Figure 7-6. Current Sense Amplifier Output
If the voltage across the SP and SN pins exceeds 1 V, then the DRV870x-Q1 device flags an overcurrent
condition.
The SO pin can source up to 5 mA of current. If the pin is shorted to ground, or if this pin drives a higher current
load, the output functions as a constant-current source. The output voltage is not representative of the H-bridge
current in this state.
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Drive Current (A)
I(CHOP)
Drive
Brake and Slow Decay
Drive
Brake and Slow Decay
t(DRIVE)
tOFF
t(DRIVE)
tOFF
(Vio+Vrsense) x AV
(Vio+Vrsense) x AV
SO (V)
VVREF
Figure 7-7. Current Sense Amplifier and Current Chopping Operation
During brake mode (slow decay), current is circulated through the low-side FETs. Because current is not flowing
through the sense resistor, the SO pin does not represent the motor current.
7.3.5.1 SO Sample and Hold Operation
The DRV8703-Q1 device allows the shunt amplifier to operate in a sample and hold configuration. To enable this
mode, set the SH_EN bit high through the SPI. In this mode, the shunt amplifier output is disabled to the
Hi-Z state whenever the driver is in a brake mode. Place an external capacitor on this pin.
Drive Current (A)
I(CHOP)
Drive
Brake and Slow Decay
Drive
Brake and Slow Decay
t(DRIVE)
tOFF
t(DRIVE)
tOFF
(Vio+Vrsense) x AV
(Vio+Vrsense) x AV
SO (V)
VVREF
SO Output Hi-Z
SO Output Hi-Z
Figure 7-8. Sample and Hold Operation
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7.3.6 PWM Motor Gate Drivers
The DRV870x-Q1 device has gate drivers for a single H-bridge with external NMOS FETs. Figure 7-9 shows a
block diagram of the predrive circuitry.
VGHS
VM
GH1
R(OFF)
IN1/PH
SH1
Predrive
VGLS
IN2/EN
GL1
nSLEEP
BDC
R(OFF)
Logic
VGHS
VM
GH2
R(OFF)
Predrive
SH2
VGLS
GL2
R(OFF)
SP
SN
R(SENSE)
Figure 7-9. Predrive Block Diagram
Gate drivers inside the DRV870x-Q1 device directly drive N-Channel MOSFETs, which drive the motor current.
The high-side gate drive is supplied by the charge pump, while an internal regulator generates the low-side gate
drive.
The peak drive current of the gate drivers is adjustable through the IDRIVE pin for DRV8702-Q1 device or the
IDRIVE register for the DRV8703-Q1 device. Peak source currents can be set to the values listed in the FET
gate drivers section of the Section 6.5 table. The peak sink current is approximately two times the peak source
current. Adjusting the peak current changes the output slew rate, which also depends on the FET input
capacitance and gate charge.
Fast switching times can cause extra noise on the VM and GND pins. This additional noise can occur specifically
because of a relatively slow reverse-recovery time of the low-side body diode, when the body diode conducts
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reverse-bias momentarily, similar to shoot-through. Slow switching times can cause excessive power dissipation
because the external FETs have a longer turn on and turn off time.
When changing the state of the output, the peak current (IDRIVE) is applied for a short period (t(DRIVE)), to charge
the gate capacitance. After this time, a weak current source (IHOLD) is used to keep the gate at the desired state.
When selecting the gate drive strength for a given external FET, the selected current must be high enough to
charge fully and discharge the gate during t(DRIVE), or excessive power is dissipated in the FET.
During high-side turn on, the low-side gate is pulled low with a strong pulldown (ISTRONG). This pulldown
prevents the low-side FET QGS from charging and keeps the FET off, even when fast switching occurs at the
outputs.
The gate-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. When the switching FETs are on, this handshaking prevents
the high-side or low-side FET from turning on until the opposite FET turns off.
t(DRIVE)
IHOLD
IDRIVE(SRC)
High-side
gate drive
current
IDRIVE(SNK)
ISTRONG
ISTRONG
High-side
VGS
tDRIVE
IHOLD
Low-side
gate drive
current
IHOLD
IDRIVE(SNK)
IDRIVE(SRC)
ISTRONG
Low-side
VGS
Figure 7-10. Gate Driver Output to Control External FETs
7.3.6.1 Miller Charge (QGD)
When a FET gate turns on, the following capacitances must be charged:
• Gate-to-source charge, QGS
• Gate-to-drain charge, QGD (Miller charge)
• Remaining QG
The FET output is slewing primarily during the QGD charge.
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Gate-To-Source Charge (V)
24 V
D
VGHS
Predrive
GHx
G
SHx
10
25
8
20
6
15
4
10
2
5
S
10
QGS
30
20
QGD
Gate Charge (nC)
40
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50
Figure 7-11. FET Gate Charging Profile
7.3.7 IDRIVE Pin (DRV8702-Q1 Only)
The rise and fall times of the H-bridge output (SHx pins) can be adjusted by setting the IDRIVE resistor value or
forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is selected.
The ramp of the FET gate directly affects the rise and fall times of the H-bridge output.
Tying the IDRIVE pin to ground selects the lowest drive setting of 10-mA source and 20-mA sink. Leaving this
pin open selects the drive setting of 155-mA high side and 130-mA low side for source current, and 265-mA high
side, 260-mA low side for sink current, at a VM voltage of 13.5 V. For a detailed list of IDRIVE configurations,
see Table 7-7.
+
4.9 V
±
AVDD
+
190 NŸ
3.7 V
±
IDRIVE
+
310 NŸ
2.5 V
±
Digital
Core
+
1.3 V
±
+
0.1 V
±
Figure 7-12. IDRIVE Pin Internal Circuitry
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Table 7-7. DRV8702-Q1 IDRIVE Settings
IDRIVE
RESISTANCE
IDRIVE
VOLTAGE
< 1 kΩ to GND
33 kΩ ± 5% to
GND
SOURCE CURRENT
SINK CURRENT
VVM = 5.5 V
VVM = 13.5 V
VVM = 5.5 V
VVM = 13.5 V
GND
High-side: 10 mA
Low-side: 10 mA
High-side: 10 mA
Low-side: 10 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
0.7 V ± 5%
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 40 mA
Low-side: 40 mA
CIRCUIT
IDRIVE
IDRIVE
RIDRIVE
200 kΩ ± 5% to
GND
2 V ± 5%
High-side: 50 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 45 mA
High-side: 90 mA
Low-side: 85 mA
IDRIVE
High-side: 95 mA
Low-side: 95 mA
RIDRIVE
> 2 MΩ to GND, HiZ
3 V ± 5%
High-side: 145 mA
Low-side: 115 mA
High-side: 155 mA
Low-side: 130 mA
High-side: 250 mA
Low-side: 235 mA
High-side: 265 mA
Low-side: 260 mA
IDRIVE
AVDD
68 kΩ ± 5% to
AVDD
4 V ± 5%
High-side: 190 mA
Low-side: 145 mA
High-side: 210 mA
Low-side: 180 mA
High-side: 330 mA
Low-side: 300 mA
High-side: 350 mA
Low-side: 350 mA
IDRIVE
AVDD
< 1 kΩ to AVDD
AVDD
High-side: 240 mA
Low-side: 190 mA
High-side: 260 mA
Low-side: 225 mA
High-side: 420 mA
Low-side: 360 mA
High-side: 440 mA
Low-side:430 mA
IDRIVE
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7.3.8 Dead Time
The dead time (t(DEAD)) is measured as the time when the SHx pin is in the Hi-Z state between turning off one of
the H-bridge FETs and turning on the other. For example, the output is Hi-Z between turning off the high-side
FET and turning on the low-side FET.
The dead time consists of an inserted digital dead time and FET gate slewing. The DRV8702-Q1 device has a
digital dead time of approximately 240 ns. The DRV8703-Q1 device has programmable dead-time options of
120, 240, 480, 960 ns. In addition to this digital dead time, the output is Hi-Z as long as the voltage across the
GLx pin to ground or GHx pin to SHx pin is less than the FET threshold voltage.
The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GHx
and GLx pins) includes the observable dead time.
7.3.9 Propagation Delay
The propagation delay time (tPD) is measured as the time between an input edge to an output change. This time
is composed of two parts: an input deglitcher and output slewing delay. The input deglitcher prevents noise on
the input pins from affecting the output state.
The gate drive slew rate also contributes to the delay time. For the output to change state during normal
operation, one FET must first be turned off. The FET gate is ramped down according to the IDRIVE resistor
selection, and the observed propagation delay ends when the FET gate falls below the threshold voltage.
7.3.10 Overcurrent VDS Monitor
The gate-driver circuit monitors the VDS voltage of each external FET when it is driving current. When the
voltage monitored is greater than the OCP threshold voltage (VDS(OCP)) after the OCP deglitch time has expired,
an OCP condition is detected. The VDS(OCP) voltage can be adjusted by changing the resistor (RVDS) on the VDS
pin of the DRV8702-Q1 device. The DRV8703-Q1 device provides VDS(OCP) voltage levels by setting the VDS
register.
32
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VM
VDRAIN
+
High-Side
VDS OCP
Monitor 1
GH1
SH1
±
GL1
+
Low-Side
VDS OCP
Monitor 1
BDC
+
GH2
High-Side
VDS OCP
Monitor 2
±
±
+
SH2
GL2
Low-Side
VDS OCP
Monitor 2
SL2
±
SP
SN
R(SENSE)
Figure 7-13. VDS(OCP) Block Diagram
The VDS voltage on the high-side FET is measured across the VDRAIN to SHx pins. The low-side VDS monitor
on half-bridge 1 measures the VDS voltage across the SH1 to SP pins. The low-side VDS monitor on half-bridge
2 measures the VDS voltage across the SH2 to SL2 pins. Ensure that the SP pin is always connected to the
source of the low-side FET of half-bridge 1, even when the sense amplifier is not used.
7.3.11 VDS Pin (DRV8702-Q1 Only)
The VDS pin on the DRV8702-Q1 device is used to select the VDS threshold voltage for overcurrent detection.
Tying the VDS pin to ground selects the lowest setting of 0.06 V. Leaving this pin open selects the setting of
0.48 V. Tying the VDS pin to the AVDD the pin disables the VDS monitor. For a detailed list of VDS
configurations, see Table 7-8.
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+
4.9 V
±
AVDD
+
190 NŸ
3.7 V
±
VDS
+
310 NŸ
2.5 V
±
Digital
Core
+
1.3 V
±
+
0.1 V
±
Figure 7-14. VDS Block Diagram
34
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Table 7-8. VDS Pin Resistor Setting
VDS RESISTANCE
VDS VOLTAGE
OVERCURRENT
TRIP LEVEL
(VDS(OCP))
< 1 kΩ to GND
GND
0.06 V
33 kΩ ± 5% to GND
0.7 V ± 5%
0.12 V
CIRCUIT
VDS
VDS
RIDRIVE
200 kΩ ± 5% to GND
2 V ± 5%
VDS
0.24 V
RIDRIVE
> 2 MΩ to GND, Hi-Z
3 V ± 5%
0.48 V
VDS
AVDD
68 kΩ ± 5% to AVDD
4 V ± 5%
0.96 V
VDS
AVDD
< 1 kΩ to AVDD
AVDD
Disabled
VDS
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7.3.12 Charge Pump
A charge pump is integrated to supply the gate drive voltage of a high-side NMOS (VGSH). The charge pump
requires a capacitor between the VM and VCP pins. Additionally, a low-ESR ceramic capacitor is required
between the CPH and CPL pins. When the VM voltage is below 13.5 V, this charge pump functions as a doubler
and generates a VVCP equal to 2 × VVM – 1.5 V if unloaded. When the VM voltage is more than 13.5 V, the
charge pump regulates VVCP such that it is equal to VVM + 10.5 V.
VM
1 F
VCP
CPH
VM
Charge
Pump
0.1 F
CPL
Figure 7-15. Charge Pump Block Diagram
7.3.13 Gate Drive Clamp
A clamping structure limits the gate-drive output voltage to the VC(GS) voltage to protect the power FETs from
damage. The positive voltage clamp is realized using a series of diodes. The negative voltage clamp uses the
body diodes of the internal predriver FET.
VGHS
VM
I(REVERSE)
GHx
VGS > VC
IC
SHx
Predriver
VGLS
VGS negative
GLx
R(SENSE)
PGND
Figure 7-16. Gate Drive Clamp
36
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7.3.14 Protection Circuits
The DRV870x-Q1 device is protected against VM undervoltage, charge-pump undervoltage, overcurrent, gatedriver shorts, and overtemperature events.
7.3.14.1 VM Undervoltage Lockout (UVLO2)
If the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (VUVLO2), all FETs in the
H-bridge are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The VM_UVFL bit of the
DRV8703-Q1 device is set. The operation resumes when the VM voltage rises above the UVLO2 threshold. The
nFAULT pin is released after the operation resumes but the VM_UVFL bit on the DRV8703-Q1 device remains
set until cleared by writing to the CLR_FLT bit.
The SPI settings on the DRV8703-Q1 device are not reset by this fault even though the output drivers are
disabled. The settings are maintained and internal logic remains active until the VM voltage falls below the logic
undervoltage threshold (VUVLO1).
7.3.14.2 Logic Undervoltage (UVLO1)
If the voltage on the VM pin falls below the logic undervoltage threshold voltage (VUVLO1), the internal logic is
reset. The operation resumes when the VM voltage rises above the UVLO1 threshold. The nFAULT pin is logic
low during this state because it is pulled low when the VM undervoltage condition occurs. Decreasing the VM
voltage below this undervoltage threshold resets the SPI settings.
7.3.14.3 VCP Undervoltage Lockout (CPUV)
If the voltage on the VCP pin falls below the threshold voltage of the charge-pump undervoltage (CPUV) lockout,
all FETs in the H-bridge are disabled and the nFAULT pin is driven low. The DRV8703-Q1 the VCP_UVFL bit is
set. The operation resumes when the VCP voltage rises above the CPUV threshold. The nFAULT pin is released
after the operation resumes but the VCP_UVFL bit on the DRV8703-Q1 device remains set until cleared by
writing to the CLR_FLT bit.
7.3.14.4 Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the VDS voltage drop across the external FETs. If the voltage across a
driven FET exceeds the VDS(OCP) level for longer than the OCP deglitch time, an OCP event is recognized. All
FETs in the H-bridge are disabled, and the nFAULT pin is driven low. The OCP bit of the DRV8703-Q1 device is
set. The drive re-enables after the t(RETRY) time has passed. The nFAULT pin becomes high again after the retry
time.
If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes
and the nFAULT pin goes high. The OCP bit on the DRV8703-Q1 remains set until cleared by writing to the
CLR_FLT bit. In addition to this FET VDS monitor, an overcurrent condition is detected if the voltage at the SP
pin exceeds VSP(OCP) and the nFAULT pin is driven low. The OCP bit in the DRV8703-Q1 device is set.
7.3.14.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external FET gate does not increase or
decrease after the t(DRIVE) time, a gate driver fault is detected. This fault occurs if the GHx or GLx pins are
shorted to the GND, SHx, or VM pin. Additionally, a gate-driver fault occurs if the selected IDRIVE setting is not
sufficient to turn on the external FET. All FETs in the H-bridge are disabled, and the nFAULT pin is driven low.
The GDF bit of the DRV8703-Q1 device is set. The driver re-enables after the OCP retry period (t(RETRY)) has
passed. The nFAULT pin is released after the operation has resumed but the GDF bit on the DRV8703-Q1
device remains set until cleared by writing to the CLR_FLT bit.
7.3.14.6 Thermal Shutdown (TSD)
If the die temperature exceeds the TSD temperature, all FETs in the H-bridge are disabled, the charge pump
shuts down, the AVDD regulator is disabled, and the nFAULT pin is driven low. The OTSD bit of the DRV8703Q1 device is set as well. After the die temperature falls below TSD – Thys temperature, device operation
automatically resumes. The nFAULT pin is released after the operation resumes, but the OTSD bit on the
DRV8703-Q1 device remains set until cleared by writing to the CLR_FLT bit.
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7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
An MCU watchdog function can be enabled to ensure that the external controller that is instructing the
DRV8703-Q1 device is active and in a known state. The SPI watchdog must be enabled by writing a 1 to the
WD_EN bit through the SPI (disabled by default, bit is 0). When the watchdog is enabled, an internal timer starts
to count down to an interval set by the WD_DLY bits. The register address 0x00 must be read by the MCU within
the interval set by the WD_DLY bit to reset the watchdog. If the timer is allowed to expire, the nWDFLT pin is
enabled. When the nWDFLT pin is enabled the following occurs:
• The nWDFLT pin goes low for 64 µs.
• The nFAULT pin is asserted.
• The WD_EN bit is cleared.
• The drivers are disabled.
The WDFLT bit remains asserted, and operation is halted until the CLR_FLT bit has been written to 1.
Table 7-9 lists the fault responses of the device under the fault conditions.
Table 7-9. Fault Response
38
FAULT
CONDITION
H-BRIDGE
CHARGE PUMP
AVDD
DVDD
RECOVERY
VM undervoltage
(UVLO)
VVM ≤ V(UVLOx)
(5.45 V, max)
Disabled
Disabled
Disabled
Operating
VVM ≥ V(UVLOx)
(5.65 V, max)
VCP undervoltage
(CPUV)
VVCP ≤ V(CP_UV)
(VVM + 1.5, typ)
Disabled
Operating
Operating
Operating
VVCP ≥ V(CP_UV)
(VVM + 1.5, typ)
External FET overload
(OCP)
VDS ≥ VDS(OCP)
VSP – VSN > 1 V
Disabled
Operating
Operating
Operating
t(RETRY)
Gate driver fault
(GDF)
Gate voltage unchanged after
t(DRIVE)
Disabled
Operating
Operating
Operating
t(RETRY)
Watchdog fault
(WDFLT)
Watchdog timer expires
Disabled
Operating
Operating
Operating
CLR_FLT bit
Thermal shutdown
(TSD)
TJ ≥ TSD (150°C, min)
Disabled
Disabled
Disabled
Operating
TJ ≤ TSD – Thys
(Thys is typically 20°C)
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7.3.14.8 Reverse Supply Protection
The circuit in Figure 7-17 can be implemented to help protect the system from reverse supply conditions. This
circuit requires the following additional components:
• NMOS FET
• NPN BJT
• Diode
• 10-kΩ resistor
• 43-kΩ resistor
VM
43 kŸ
10 kŸ
0.1 µF
1 µF
Bulk
10 µF (min)
0.1 µF
CP1
CP2
VCP
VM
+
GH1
SH1
GL1
BDC
GH2
SH2
GL2
SP
R(SENSE)
SN
Figure 7-17. Reverse Supply Protection
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7.3.15 Hardware Interface
The DRV8702-Q1 hardware interface allows the device to be configured without a SPI, however not all of the
functionality is configurable like the DRV8703-Q1 device. The following configuration settings are fixed for the
hardware-interface device option:
• The toff value is set to 25 µs.
• Current regulation is enabled
• The VREF pin voltage is not scaled internally (100%).
• The shunt amplifier has a fixed gain of 19.8 V/V.
7.3.15.1 IDRIVE (6-level input)
The voltage or resistance on the IDRIVE pin sets the peak source and peak sink IDRIVE setting as listed in
Table 7-10.
Table 7-10. DRV8702-Q1 IDRIVE Settings
IDRIVE
RESISTANCE
IDRIVE VOLTAGE
SOURCE CURRENT
SINK CURRENT
VVM = 5.5 V
VVM = 13.5 V
VVM = 5.5 V
VVM = 13.5 V
High-side: 10 mA
Low-side: 10 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
< 1 kΩ to GND
GND
High-side: 10 mA
Low-side: 10 mA
33 kΩ ± 5% to
GND
0.7 V ± 5%
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 40 mA
Low-side: 40 mA
200 kΩ ± 5% to
GND
2 V ± 5%
High-side: 50 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 45 mA
High-side: 90 mA
Low-side: 85 mA
High-side: 95 mA
Low-side: 95 mA
> 2 MΩ to GND,
Hi-Z
3 V ± 5%
High-side: 145 mA
Low-side: 115 mA
High-side: 155 mA
Low-side: 130 mA
High-side: 250 mA
Low-side: 235 mA
High-side: 265 mA
Low-side: 260 mA
68 kΩ ± 5% to
AVDD
4 V ± 5%
High-side: 190 mA
Low-side: 145 mA
High-side: 210 mA
Low-side: 180 mA
High-side: 330 mA
Low-side: 300 mA
High-side: 350 mA
Low-side: 350 mA
< 1 kΩ to AVDD
AVDD
High-side: 240 mA
Low-side: 190 mA
High-side: 260 mA
Low-side: 225 mA
High-side: 420 mA
Low-side: 360 mA
High-side: 440 mA
Low-side:430 mA
7.3.15.2 VDS (6-Level Input)
This input controls the VDS monitor trip voltage as listed in Table 7-11.
Table 7-11. DRV8702-Q1 VDS Settings
40
VDS RESISTANCE
VDS VOLTAGE
OVERCURRENT TRIP LEVEL
(VDS(OCP))
< 1 kΩ to GND
GND
0.06 V
33 kΩ ± 5% to GND
0.7 V ± 5%
0.12 V
200 kΩ ± 5% to GND
2 V ± 5%
0.24 V
> 2 MΩ to GND, Hi-Z
3 V ± 5%
0.48 V
68 kΩ ± 5% to AVDD
4 V ± 5%
0.96 V
< 1 kΩ to AVDD
AVDD
Disabled
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7.4 Device Functional Modes
The DRV870x-Q1 device is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is
disabled, the H-bridge FETs are disabled to the Hi-Z state, and the AVDD and DVDD regulators are disabled.
Note
The t(SLEEP) time must elapse after a falling edge on the nSLEEP pin before the device is in sleep
mode. The DRV870x-Q1 device is brought out of sleep mode automatically if the nSLEEP pin is
brought high.
The t(WAKE) time must elapse before the outputs change state after wakeup.
On the DRV8703-Q1 device, the SPI settings are reset when coming out of UVLO or exiting sleep mode.
While the nSLEEP pin is brought low, all external H-bridge FETs are disabled. The high-side gate pins, GHx, are
pulled to the output node, SHx, by an internal resistor and the low-side gate pins, GLx, are pulled to ground.
When the VM voltage is not applied and during the power-on time (ton) the outputs are disabled using weak
pulldown resistors between the GHx and SHx pins and the GLx and GND pins.
Note
The MODE pin controls the device-logic operation for phase and enable, independent half-bridge, or
PWM input modes. This operation is latched on power up or when exiting sleep mode.
7.5 Programming
7.5.1 SPI Communication
7.5.1.1 Serial Peripheral Interface (SPI)
The SPI (DRV8703-Q1 only) is used to set device configurations, operating parameters, and read out diagnostic
information. The DRV8703-Q1 SPI operates in slave mode. The SPI input data (SDI) word consists of a 16-bit
word, with a 5-bit command, 3 don't care bits, and 8 bits of data. The SPI output data (SDO) word consists of 8bit register data and the first 8 bits are don’t cares.
A valid frame has to meet following conditions:
• The clock polarity (CPOL) must be set to 0.
• The clock phase (CPHA) must be set to 0.
• The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.
• No SCLK signal can occur when the nSCS signal is in transition.
• The SCLK pin must be low when the nSCS pin goes high.
• The nSCS pin should be taken high for at least 500 ns between frames.
• When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is
in the high impedance state.
• Full 16 SCLK cycles must occur.
• Data is captured on the falling edge of the clock and data is driven on the rising edge of the clock.
• The most-significant bit (MSB) is shifted in and out first
• For a write command, if the data word sent to the SDI pin is less than or more than 16 bits, a frame error
occurs and the data word is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5-bit command data
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7.5.1.2 SPI Format
The SDI input-data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit 15)
• 4 address bits, A (bits 14 through 11)
• 3 don't care bits, X (10 through 8)
• 8 data bits, D (7:0)
The SDO output-data word is 16 bits long and the first 8 bits are don’t care bits. The data word is the content of
the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
Table 7-12. SDI Input Data Word Format
R/W
ADDRESS
DON'T CARE
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
W0
A3
A2
A1
A0
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
Table 7-13. SDO Output Data Word Format
DON'T CARE
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
nSCS
SCLK
SDI
X
MSB
LSB
X
SDO
Z
MSB
LSB
Z
Capture
Point
Propagate
Point
Figure 7-18. SPI Transaction
The SCLK pin should be low at power-up of the device for reliable SPI transaction. If the SCLK pin cannot be
guaranteed to be low at power-up, TI recommends performing a dummy SPI-read transaction (of any register)
after power-up to ensure reliable subsequent transactions. Data read from this dummy read transaction should
be discarded.
42
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7.6 Register Maps
Table 7-14. DRV8703-Q1 Memory Map
Register
Name
7
6
5
4
3
2
1
0
Access
Type
Address
(Hex)
0
FAULT Status
FAULT
WDFLT
GDF
OCP
VM_UVFL
VCP_UVFL
OTSD
OTW
R
VDS and GDF
H2_GDF
L2_GDF
H1_GDF
L1_GDF
H2_VDS
L2_VDS
H1_VDS
L1_VDS
R
1
IN1/PH
IN2/EN
CLR_FLT
RW
2
RW
3
DIS_L2_VDS
DIS_H1_VDS
RW
4
RW
5
Main
RESERVED
IDRIVE and WD
VDS
LOCK
TDEAD
WD_EN
SO_LIM
WD_DLY
VDS
Config
TOFF
IDRIVE
DIS_H2_VDS
CHOP_IDS
VREF_SCL
SH_EN
DIS_L1_VDS
GAIN_CS
Table 7-15. Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
7.6.1 Status Registers
The status registers are used to report warning and fault conditions. Status registers are read only registers.
Table 7-16 lists the memory-mapped registers for the status registers. All register offset addresses not listed in
Table 7-16 should be considered as reserved locations and the register contents should not be modified.
Table 7-16. Status Registers Summary Table
Address
Register Name
Section
0x00h
FAULT status
Go
0x01h
VDS and GDF status
Go
7.6.2 FAULT Status Register (address = 0x00h)
FAULT status is shown in Figure 7-19 and described in Table 7-17.
Return to Summary Table.
Read only
Figure 7-19. FAULT Status Register
7
6
5
4
3
2
1
0
FAULT
R-0b
WDFLT
GDF
OCP
VM_UVFL
VCP_UVFL
OTSD
OTW
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
Table 7-17. FAULT Status Field Descriptions
Bit
Field
Type
Default
Description
7
FAULT
R
0b
Logic OR of the FAULT status register excluding the OTW bit
6
WDFLT
R
0b
Watchdog time-out fault
5
GDF
R
0b
Indicates gate drive fault condition
4
OCP
R
0b
Indicates VDS monitor overcurrent fault condition
3
VM_UVFL
R
0b
Indicates VM undervoltage lockout fault condition
2
VCP_UVFL
R
0b
Indicates charge-pump undervoltage fault condition
1
OTSD
R
0b
Indicates overtemperature shutdown
0
OTW
R
0b
Indicates overtemperature warning
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7.6.3 VDS and GDF Status Register Name (address = 0x01h)
VDS and GDF status is shown in Figure 7-20 and described in Table 7-18.
Return to Summary Table.
Read only
Figure 7-20. VDS and GDF Status Register
7
6
5
4
3
2
1
0
H2_GDF
L2_GDF
H1_GDF
L1_GDF
H2_VDS
L2_VDS
H1_VDS
L1_VDS
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
Table 7-18. VDS and GDF Status Field Descriptions
Bit
Field
Type
Default
Description
7
H2_GDF
R
0b
Indicates gate drive fault on the high-side FET of half-bridge 2
6
L2_GDF
R
0b
Indicates gate drive fault on the low-side FET of half-bridge 2
5
H1_GDF
R
0b
Indicates gate drive fault on the high-side FET of half-bridge 1
4
L1_GDF
R
0b
Indicates gate drive fault on the low-side FET of half-bridge 1
3
H2_VDS
R
0b
Indicates VDS monitor overcurrent fault on the high-side FET of
half-bridge 2
2
L2_VDS
R
0b
Indicates VDS monitor overcurrent fault on the low-side FET of
half-bridge 2
1
H1_VDS
R
0b
Indicates VDS monitor overcurrent fault on the high-side FET of
half-bridge 1
0
L1_VDS
R
0b
Indicates VDS monitor overcurrent fault on the low-side FET of
half-bridge 1
7.6.4 Control Registers
The control registers are used to configure the device. Control registers are read and write capable.
Table 7-19 lists the memory-mapped registers for the status registers. All register offset addresses not listed in
Table 7-19 should be considered as reserved locations and the register contents should not be modified.
Table 7-19. Status Registers Summary Table
Address
44
Register Name
Section
0x02h
Main control
Go
0x03h
IDRIVE and WD control
Go
0x04h
VDS control
Go
0x05h
Config control
Go
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7.6.5 Main Control Register Name (address = 0x02h)
Main control is shown in Figure 7-21 and described in Table 7-20.
Return to Summary Table.
Read and write
Figure 7-21. Main Control Register
7
6
5
2
1
0
RESERVED
LOCK
4
3
IN1/PH
IN2/EN
CLR_FLT
R/W-00b
R/W-011b
R/W-0b
R/W-0b
R/W-0b
Table 7-20. Main Control Field Descriptions
Bit
Field
Type
Default
Description
7-6
RESERVED
R/W
00b
Reserved
5-3
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register
changes except to address 0x02h. Writing any sequence other
than 110b has no effect when unlocked.
Write 011b to this register to unlock all registers. Writing any
sequence other than 011b has no effect when locked.
2
IN1/PH
R/W
0b
This bit is ORed with the IN1/PH pin
1
IN2/EN
R/W
0b
This bit is ORed with the IN2/EN pin
0
CLR_FLT
R/W
0b
Write a 1 to this bit to clear the fault bits
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7.6.6 IDRIVE and WD Control Register Name (address = 0x03h)
IDRIVE and WD control is shown in Figure 7-22 and described in Table 7-21.
Return to Summary Table.
Read and write
Figure 7-22. IDRIVE and WD Register
7
6
5
4
3
2
1
0
TDEAD
WD_EN
WD_DLY
IDRIVE
R/W-00b
R/W-0b
R/W-00b
R/W-111b
Table 7-21. IDRIVE and WD Field Descriptions
Bit
Field
Type
Default
Description
7-6
TDEAD
R/W
00b
Dead time
00b = 120 ns
01b = 240 ns
10b = 480 ns
11b = 960 ns
5
WD_EN
R/W
0b
Enables or disables the watchdog time (disabled by default)
4-3
WD_DLY
R/W
00b
Watchdog timeout delay (if WD_EN = 1)
00b = 10 ms
01b = 20 ms
10b = 50 ms
11b = 100 ms
2-0
IDRIVE
R/W
111b
Sets the peak source current and peak sink current of the gate
drive. Table 7-22 lists the bit settings.
Table 7-22. IDRIVE Bit Settings
Bit Value
46
Source Current
Sink Current
VVM = 5.5 V
VVM = 13.5 V
VVM = 5.5 V
VVM = 13.5 V
000b
High-side: 10 mA
Low-side: 10 mA
High-side: 10 mA
Low-side: 10 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
001b
High-side: 20 mA
Low-side: 20 mA
High-side: 20 mA
Low-side: 20 mA
High-side: 40 mA
Low-side: 40 mA
High-side: 40 mA
Low-side: 40 mA
010b
High-side: 50 mA
Low-side: 40 mA
High-side: 50 mA
Low-side: 45 mA
High-side: 90 mA
Low-side: 85 mA
High-side: 95 mA
Low-side: 95 mA
011b
High-side: 70 mA
Low-side: 55 mA
High-side: 70 mA
Low-side: 60 mA
High-side: 120 mA
Low-side: 115 mA
High-side: 130 mA
Low-side: 125 mA
100b
High-side: 100 mA
Low-side: 75 mA
High-side: 105 mA
Low-side: 90 mA
High-side: 170 mA
Low-side: 160 mA
High-side: 185 mA
Low-side: 180 mA
101b
High-side: 145 mA
Low-side: 115 mA
High-side: 155 mA
Low-side: 130 mA
High-side: 250 mA
Low-side: 235 mA
High-side: 265 mA
Low-side: 260 mA
110b
High-side: 190 mA
Low-side: 145 mA
High-side: 210 mA
Low-side: 180 mA
High-side: 330 mA
Low-side: 300 mA
High-side: 350 mA
Low-side: 350 mA
111b
High-side: 240 mA
Low-side: 190 mA
High-side: 260 mA
Low-side: 225 mA
High-side: 420 mA
Low-side: 360 mA
High-side: 440 mA
Low-side: 430 mA
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7.6.7 VDS Control Register Name (address = 0x04h)
VDS control is shown in Figure 7-23 and described in Table 7-23.
Return to Summary Table.
Read and write
Figure 7-23. VDS Control Register
7
6
5
3
2
1
0
SO_LIM
VDS
4
DIS_H2_VDS
DIS_L2_VDS
DIS_H1_VDS
DIS_L1_VDS
R/W-0b
R/W-111b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
Table 7-23. VDS Control Field Descriptions
Bit
Field
Type
Default
Description
SO_LIM
R/W
0b
0b = Default operation
1b = SO output is voltage-limited to 3.6 V
VDS
R/W
111b
Sets the VDS(OCP) monitor for each FET
000b = 0.06 V
001b = 0.145 V
010b = 0.17 V
011b = 0.2 V
100b = 0.12 V
101b = 0.24 V
110b = 0.48 V
111b = 0.96 V
3
DIS_H2_VDS
R/W
0b
Disables the VDS monitor on the high-side FET of half-bridge 2
(enabled by default)
2
DIS_L2_VDS
R/W
0b
Disables the VDS monitor on the low-side FET of half-bridge 2
(enabled by default)
1
DIS_H1_VDS
R/W
0b
Disables the VDS monitor on the high-side FET of half-bridge 1
(enabled by default)
0
DIS_L1_VDS
R/W
0b
Disables the VDS monitor on the low-side FET of half-bridge 1
(enabled by default)
7
6-4
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7.6.8 Config Control Register Name (address = 0x05h)
Config control is shown in Figure 7-24 and described in Table 7-24.
Return to Summary Table.
Read and write
Figure 7-24. Config Control Register
7
6
5
4
3
2
1
0
TOFF
CHOP_IDS
VREF_SCL
SH_EN
GAIN_CS
R/W-00b
R/W-0b
R/W-00b
R/W-0b
R/W-01b
Table 7-24. Config Control Field Descriptions
Bit
Field
Type
Default
Description
7-6
TOFF
R/W
00b
Off time for PWM current chopping
00b = 25 µs
01b = 50 µs
10b = 100 µs
11b = 200 µs
5
CHOP_IDS
R/W
0b
Disables current regulation (enabled by default)
4-3
VREF_SCL
R/W
00b
Scale factor for the VREF input
00b = 100%
01b = 75%
10b = 50%
11b = 25%
SH_EN
R/W
0b
Enables sample and hold operation of the shunt amplifier
(disabled by default)
GAIN_CS
R/W
01b
Shunt amplifier gain setting
00b = 10 V/V
01b = 19.8 V/V
10b = 39.4 V/V
11b = 78 V/V
2
1-0
48
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DRV870x-Q1 device is used in brushed-DC, solenoid, or relay-control applications. The following typical
application can be used to configure the DRV870x-Q1 device.
8.2 Typical Application
This application features the DRV8702-Q1 device.
VM
+
0.1 µF
0.1 µF
VM
Bulk
1 µF
SH2
GND
GH1
R1
23
22
21
BDC
10 mŸ
20
19
18
17
VM
SO
GND
24
+
16
VREF
15
10
9
AVDD
SH1
nSLEEP
Bulk
25
26
GH2
27
28
VM
29
VCP
31
30
CPH
VDRAIN
GL1
VDS
GND
8
IDRIVE
14
7
SP
GND
(PAD)
GND
0Ÿ
GND
DVDD
6
200 kŸ
SN
13
5
IN2/EN
12
4
SL2
MODE
3
GL2
IN1/PH
11
2
GND
nFAULT
1
CPL
NC
32
+
VM
Bulk
R2
10 kŸ
1 µF
1 µF
Copyright © 2017, Texas Instruments Incorporated
Figure 8-1. DRV8702-Q1 Typical Application Schematic
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8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8-1 as the input parameters.
Table 8-1. Design Parameters
DESIGN PARAMETER
Nominal supply voltage
Supply voltage range
REFERENCE
VM
FET part number
EXAMPLE VALUE
14 V
7 V to 35 V
CSD18502Q5B
FET total gate charge
Qg
52 nC (typical)
FET gate-to-drain charge
Qgd
8.4 nC (typical)
tr
100 to 300 ns
I(CHOP)
15 A
Target FET gate rise time
Motor current chopping level
8.2.2 Detailed Design Procedure
8.2.2.1 External FET Selection
The DRV8702-Q1 FET support is based on the charge-pump capacity and PWM-output frequency. For a quick
calculation of FET driving capacity, use Equation 3 when drive and brake (slow decay) are the primary modes of
operation.
Qg
IVCP
f(PWM)
(3)
where
•
•
fPWM is the maximum desired PWM frequency to be applied to the DRV8702-Q1 inputs or the current
chopping frequency, whichever is larger.
IVCP is the charge-pump capacity, which depends on the VM voltage.
The internal current chopping frequency is at most equal to the PWM frequency as shown in Equation 4.
f(PWM)
t off
1
t(BLANK)
(4)
For example, if the VM voltage of a system is 7 V (IVCP = 8 mA) and uses a maximum PWM frequency of 40
kHz, then the DRV8702-Q1 device will support FETs with a Qg up to 200 nC.
If the application requires a forced fast decay (or alternating between drive and reverse drive), use Equation 5 to
calculate the maximum FET driving capacity.
Qg
IVCP
2 u f(PWM)
(5)
8.2.2.2 IDRIVE Configuration
The IDRIVE current is selected based on the gate charge of the FETs. The IDRIVE pin must be configured so
that the FET gates are charged entirely during the t(DRIVE) time. If the selected IDRIVE current is too low for a
given FET, then the FET may not turn on completely. TI recommends adjusting these values in-system with the
required external FETs and motor to determine the best possible setting for any application.
For FETs with a known gate-to-drain charge (Qgd) and desired rise time (tr), the IDRIVE current can be selected
based on the Equation 6.
IDRIVE !
50
Qgd
tr
(6)
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If the gate-to-drain charge is 2.3 nC and the desired rise time is around 100 to 300 ns, use Equation 7 to
calculate the minimum IDRIVE (IDRIVE1) and Equation 8 to calculate the maximum IDRIVE (IDRIVE2).
IDRIVE1 = 8.4 nC / 100 ns = 84 mA
(7)
IDRIVE2 = 8.4 nC / 300 ns = 28 mA
(8)
Select a value for IDRIVE between 28 and 84 mA. An IDRIVE value of approximately 50 mA for the source
(approximately 100 mA sink) was selected for this application. This value requires a 200-kΩ resistor from the
IDRIVE pin to ground.
8.2.2.3 VDS Configuration
The VDS monitor threshold voltage, VDS(OCP), is configured based on the maximum current, IVDS, and RDS(on) of
the FETs. The drain to source voltage, VDSFET, is the maximum current, IVDS, multiplied by the RDS(on) of the
FET.
The VDS pin of the DRV8702-Q1 selects the VDS monitor trip threshold, VDS(OCP). The VDS bits in the VDS
register of the DRV8703-Q1 selects the VDS(OCP) voltage. Use Equation 9 to calculate the trip current.
IVDS !
VDSFET
RDS(on)
(9)
If the RDS(on) of the FET is 1.8 mΩ and the desired maximum current is less than 100 A, the VDSFET voltage is
equal to 180 mV as shown in Equation 10.
For this example, select a value for the VDS(OCP) that is less than 180 mV. A VDS(OCP) value of 0.12 V was
selected for this application.
To set the VDS(OCP) to 0.12 V, use the SPI (DRV8703-Q1 Only) or place a 33k resistor at the VDS pin to ground
(DRV8702-Q1 Only).
The VDS pin can configured to select other VDS(OCP) threshold voltages. See the Section 7.3.11 section for more
information on VDS operation.
VDSFET= IVDS × RDS(on) = 100 A × 1.8 mΩ = 180 mV
(10)
8.2.2.4 Current Chopping Configuration
The chopping current is set based on the sense resistor value and the analog voltage at the VREF pin. Use
Equation 11 to calculate the current (I(CHOP)). The amplifier gain, AV, is 19.8 V/V for the DRV8702-Q1 and VIO is
typically 5 mV (input referred).
I(CHOP)
VVREF VIO u A V
A V u R(SENSE)
(11)
For example, if the desired chopping current is 15 A, select a value of 10 mΩ for R(SENSE). The value of VVREF
must therefore be 2.975 V. Add a resistor divider from the AVDD (5 V) pin to set the VVREF at approximately
2.975 V. Select a value of 13 kΩ for R2 and 19.1 kΩ for R1 (the VREF resistor).
If current chopping is not required, the sense resistor can be removed and the source of the low side FET can be
connected to ground.
SN and SP should be connected to the source of the low side FET and VREF should be connected to AVDD
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8.2.3 Application Curves
10-mA source
20-mA sink
10-mA source
20-mA sink
Figure 8-2. SH1 Fall Time
Figure 8-3. SH1 Rise Time
Figure 8-4. Current Profile on Motor Startup With
Regulation
Figure 8-5. Current Profile on Motor Startup
Without Regulation
Figure 8-6. Current Regulating at 2.25 A on Motor Startup
52
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9 Power Supply Recommendations
The DRV8702-Q1 device is designed to operate with an input voltage supply (VM) rangefrom 5.5 V to 45 V. A
0.1-µF ceramic capacitor rated for VM must be placed as close to the DRV8702-Q1 device as possible. Also, a
bulk capacitor valued at least 10 µF must be placed on the VM pin.
Additional bulk capacitance is required to bypass the external H-bridge FETs.
9.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk
capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors including:
• The highest current required by the motor system.
• The capacitance of the power supply and the ability of the power supply to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (brushed DC, brushless DC, and stepper).
• The motor braking method.
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage
remains stable, and high current can be quickly supplied.
The data sheet provides a recommended value, but system-level testing is required to determine the appropriate
sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
±
+
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Copyright © 2016, Texas Instruments Incorporated
Figure 9-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases
when the motor transfers energy to the supply.
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10 Layout
10.1 Layout Guidelines
The VM pin should be bypassed to ground using a low-ESR ceramic bypass capacitor with a recommended
value of 0.1 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground-plane connection to the GND pin of the device. The VM pin must also be bypassed to ground
using a bulk capacitor rated for VM. This capacitor can be electrolytic and must be at least 10 µF.
A low-ESR ceramic capacitor must be placed between the CPL and CPH pins. A value of 0.1 µF rated for VM is
recommended. Place this capacitor as close to the pins as possible. A low-ESR ceramic capacitor must be
placed in between the VM and VCP pins. A value of 1 µF rated for 16 V is recommended. Place this component
as close to the pins as possible.
Bypass the AVDD and DVDD pins to ground with ceramic capacitors rated for 6.3 V. Place these bypassing
capacitors as close to the pins as possible.
Use separate traces to connect the SP and SN pins to the R(SENSE) resistor.
10.2 Layout Example
Bulk
1 µF
0.1 µF
24
GL2
23
SL2
22
SN
21
SP
20
GL1
GND
GND 4
(PAD)
VDS 6
19
SH1
7
18
GH1
nSLEEP 8
17
GND
GND
D
S
D
S
D
S
SO
VREF
AVDD
GND
MODE
DVDD
nFAULT
GND
S
D
S
D
S
D
G
D
S
D
S
D
S
D
G
D
16
15
14
13
12
11
9
10
1 µF
RSENSE
SH2 25
GH2 26
VM 28
VDRAIN 27
VCP 29
CPH 30
NC 32
CPL 31
GND 1
IN1/PH 2
IDRIVE 5
G
SH2
0.1 µF
IN2/EN 3
D
1 µF
Bulk
SH1
D
G
D
S
D
S
D
S
Figure 10-1. DRV8702-Q1 Layout Example
54
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Automotive Relay Replacement Application Note
• Texas Instruments, DRV8702-Q1 EVM User’s Guide
• Texas Instruments, DRV8703-Q1 EVM User’s Guide
• Texas Instruments, Small Footprint Motor Driver Sunroof Module Design Guide
• Texas Instruments, Relay Replacement for Brushed DC Motor Drive in Automotive Applications application
report
• Texas Instruments, Understanding IDRIVE and TDRIVE in TI Smart Gate Drivers
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11-1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DRV8702-Q1
Click here
Click here
Click here
Click here
Click here
DRV8703-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DRV8702-Q1 DRV8703-Q1
55
DRV8702-Q1, DRV8703-Q1
www.ti.com
SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
PACKAGE OUTLINE
RHB0032N
VQFN - 0.9 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
5.1
4.9
0.1 MIN
(0.05)
SECTION A-A
TYPICAL
A-A 30.000
C
0.9 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
A
33
A
SYMM
32X
24
1
PIN 1 ID
(OPTIONAL)
32
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
0.5
32X
0.3
4222893/B 02/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
56
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DRV8702-Q1 DRV8703-Q1
DRV8702-Q1, DRV8703-Q1
www.ti.com
SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
EXAMPLE BOARD LAYOUT
RHB0032N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222893/B 02/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DRV8702-Q1 DRV8703-Q1
57
DRV8702-Q1, DRV8703-Q1
www.ti.com
SLVSDR9E – OCTOBER 2016 – REVISED JANUARY 2021
EXAMPLE STENCIL DESIGN
RHB0032N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222893/B 02/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
58
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DRV8702-Q1 DRV8703-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8702QRHBRQ1
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU | SN
Level-3-260C-168 HR
-40 to 125
DRV8702
DRV8702QRHBTQ1
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU | SN
Level-3-260C-168 HR
-40 to 125
DRV8702
DRV8703QRHBRQ1
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU | SN
Level-3-260C-168 HR
-40 to 125
DRV8703
DRV8703QRHBTQ1
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU | SN
Level-3-260C-168 HR
-40 to 125
DRV8703
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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