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DRV8846
SLLSEK2A – JUNE 2014 – REVISED MARCH 2017
DRV8846 Dual H-Bridge Stepper Motor Driver
1 Features
3 Description
•
The DRV8846 provides a highly-integrated stepper
motor driver for cameras, printers, projectors, and
other automated equipment applications. The device
has two H-bridges and a microstepping indexer and
is intended to drive a bipolar stepper motor. The
output block of each H-bridge driver consists of Nchannel and P-channel power MOSFETs configured
as full H-bridges to drive the motor windings. The
DRV8846 is capable of driving up to 1.4-A full-scale
output current (with proper heatsinking and TA =
25°C).
1
•
•
•
•
•
•
•
•
•
PWM Microstepping Motor Driver
– Built-In Microstepping Indexer
– Up to 1/32 Microstepping
– Step/Direction Control
Multiple Decay Modes
– Smart tune Technology
– Mixed Decay
– Slow Decay
– Fast Decay
Configurable Off-Time PWM Chopping
– 10-, 20-, or 30-μs Off-Time
Adaptive Blanking Time for Smooth Stepping
4- to 18-V Operating Supply Voltage Range
1.4-A (Full Scale (Max Drive) Current per HBridge (at 25°C)
Low-Current Sleep Mode
3-Bit Torque DAC to Scale Motor Current
Thermally Enhanced Surface Mount Package
Protection Features
– VM Undervoltage Lockout (UVLO)
– Overcurrent Protection (OCP)
– Thermal Shutdown (TSD)
– Fault Condition Indication Pin (nFAULT)
A simple STEP/DIR interface allows easy interfacing
to controller circuits. Pins allow configuration of the
motor in full-step up to 1/32-step modes. Decay mode
is configurable so that smart tune, slow decay, fast
decay, and mixed decay can be used. The PWM
current chopping off-time can also be selected. A lowpower sleep mode is provided which shuts down
internal circuitry to achieve very-low quiescent current
draw. This sleep mode can be set using a dedicated
nSLEEP pin.
Internal protection functions are provided for UVLO,
overcurrent protection, short circuit protection, and
overtemperature. Fault conditions are indicated via a
nFAULT pin.
Device Information(1)
PART NUMBER
DRV8846
2 Applications
•
•
•
•
PACKAGE
VQFN (24)
BODY SIZE (NOM)
4.00 × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Printers
Scanners
Video Security Cameras
Projectors
Simplified Schematic
4 to 18 V
M
1A
Step size
Decay Mode
-
Controller
DRV8846
+
STEP/DIR
Stepper
Motor Driver
+
t
nFAULT
1/32 µstep
1A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8846
SLLSEK2A – JUNE 2014 – REVISED MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 22
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2014) to Revision A
Page
•
Changed references of adaptive decay to smart tune .......................................................................................................... 1
•
Updated Description .............................................................................................................................................................. 1
•
Changed Handling Ratings table to an ESD Ratings table and moved Tstg to Absolute Maximum Ratings ........................ 4
•
Changed references of rms current to full-scale current and changed the maximum current from 1 to 1.4 A
throughout the document........................................................................................................................................................ 4
•
Updated the RDS(ON) units and VHYS in the Electrical Characteristics ..................................................................................... 5
•
Changed changed the nENBL setting from 0 to 1 in the Micro-Stepping Indexer section................................................... 10
•
Added more information regarding the ADEC pin ............................................................................................................... 18
•
Updated the Device Functional Modes ............................................................................................................................... 21
•
Added the Documentation Support, Receiving Notification of Documentation Updates, and Community Resources
sections................................................................................................................................................................................. 26
2
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5 Pin Configuration and Functions
19
20
21
22
1
18
2
17
3
16
GND
(PPAD)
4
15
12
GND
VINT
NC
VM
VREF
DIR
M0
M1
TOFF_SEL
nENBL
STEP
nFAULT
11
13
10
6
9
14
8
5
7
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
23
24
DEC1
nSLEEP
DEC0
I1
I0
ADEC
RGE Package
24-Pin VQFN With Exposed Thermal PAD
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
ADEC
19
I
Smart tune enable
Logic low sets decay modes by DEC0 and DEC1 pins; logic high –
smart tune operation is enabled; must be set prior to coming out of
sleep; internal pulldown
AISEN
2
O
Winding A sense
Connect to current sense resistor for bridge A, or GND if current
regulation is not required
AOUT1
1
AOUT2
3
O
Winding A output
BISEN
5
O
Winding B sense
BOUT1
6
BOUT2
4
O
Winding B output
DEC0
22
I
DEC1
24
I
DIR
13
GND
Connect to current sense resistor for bridge B, or GND if current
regulation is not required
Decay mode setting pins
Sets the decay mode; see description section; tri-level pin
I
Direction input
Logic level sets the direction of stepping; internal pulldown
18, PPAD
PWR
Device ground
Both the GND pin and device thermal pad must be connected to
ground
I0
20
I
I1
21
I
Torque DAC current scalar
Scales the current from 100% to 12.5% in 12.5% steps; tri-level pin
MO
8
I
M1
9
I
Microstepping mode setting
pins
Controls step mode (full, half, up to 1/32-step) and single- or dualedge clocking; tri-level pin
NC
16
—
No connect
Unused pin not connected internally
nENBL
11
I
Enable driver output
Logic low to enable device outputs and internal indexer; logic high to
disable; internal pulldown
nFAULT
7
OD
Fault indication pin
Pulled logic low with fault condition; open-drain output requires
external pullup
nSLEEP
23
I
Sleep mode input
Logic high to enable device; logic low to enter low-power sleep mode;
internal pulldown
STEP
12
I
Step input
A rising edge (or rising and falling depending on step mode) advances
the indexer one step; internal pulldown
TOFF_SEL
10
I
Decay mode off time set
Sets the off-time during current chopping; tri-level pin
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Pin Functions (continued)
PIN
NAME
I/O
NO.
VINT
17
—
VM
15
PWR
VREF
14
I
DESCRIPTION
Internal regulator
Internal supply voltage; bypass to GND with 2.2-μF, 6.3-V capacitor
Power supply
Connect to motor power supply; bypass to GND with a 0.1- and 10-μF
(minimum) ceramic capacitor rated for VM
Full-scale current reference
input
Voltage on this pin sets the full scale chopping current; short to VINT
if not supplying an external reference voltage
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature referenced with respect to GND (unless otherwise noted) (1)
MIN
MAX
–0.3
20
V
0
2
V/µs
Internal regulator voltage (VINT)
–0.3
3.6
V
Analog input pin voltage (VREF)
–0.3
3.6
V
Control pin voltage (nENABLE, STEP, DIR, I0, I1, M0, M1, DEC0, DEC1, TOFF_SEL, nSLEEP,
nFAULT, ADEC)
–0.3
7.0
V
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
–0.3
VM + 0.6
V
–0.6
0.6
V
Power supply voltage (VM)
Power supply voltage ramp rate (VM)
Continuous shunt amplifier input pin voltage (AISEN, BISEN)
(2)
UNIT
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2, AISEN, BISEN)
Internally limited
A
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Transients of ±1 V for less than 25 ns are acceptable.
6.2 ESD Ratings
MAX
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
(1)
MAX
UNIT
VM
Power supply voltage range
4
18
VREF
Reference rms voltage range (2)
1
3.3
V
ƒPWM
Applied STEP signal
0
250
kHz
IVINT
VINT external load current
1
mA
IFS
Motor full-scale current per H-bridge
TA
Operating ambient temperature
(1)
(2)
(3)
4
(3)
V
0
1.4
A
–40
85
°C
Note that RDS(ON) increases and maximum output current is reduced at VM supply voltages below 5 V
Operational at VREF between 0 to 1 V, but accuracy is degraded
Power dissipation and thermal limits must be observed
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6.4 Thermal Information
DRV8846
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
36.9
RθJB
Junction-to-board thermal resistance
12.5
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
12.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.5
(1)
34
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, VINT)
VM
VM operating voltage
4
18
V
4.5
5.5
mA
1.2
3
μA
IVM
VM operating supply current
VM = 12 V, excluding winding current,
nSLEEP = 1, nENBL = 0 or 1
IVMQ
VM sleep mode supply current
VM = 12 V, nSLEEP = 0, nENBL = 0 or 1
tSLEEP
Sleep time
nSLEEP = 0 to sleep mode
1
ms
tWAKE
Wake time
nSLEEP = 1 to output transition
1
ms
tON
Power-on time
VM > VUVLO rising to output transition
1
ms
VINT
VINT voltage
VM > 4 V, IOUT = 0 A to 1 mA
3.5
0.5
3.13
3.3
3.47
V
0.7
V
LOGIC-LEVEL INPUTS (STEP, DIR, nENBL, nSLEEP, ADEC)
VIL
Input logic low voltage
0
VIH
Input logic high voltage
VHYS
Input logic hysteresis
IIL
Input logic low current
VIN = 0 V
–1
1
μA
IIH
Input logic high current
VIN = 5 V
1
30
μA
RPD
Pulldown resistance
tDEG
Input deglitch time
tPROP
Propagation delay
1.6
5.5
100
nENBL, STEP, DIR, ADEC
200
nSLEEP
500
STEP edge to current change
V
mV
kΩ
200
ns
600
ns
TRI-LEVEL INPUTS (I0, I1, M0, M1, DEC0, DEC1, TOFF_SEL)
VIL
Tri-level input logic low voltage
0
0.7
VIZ
Tri-level input Hi-Z voltage
VIH
Tri-level input logic high voltage
1.6
VHYS
Tri-level input hysteresis
100
IIL
Tri-level input logic low current
VIN = 0 V
–30
IIH
Tri-level input logic high current
VIN = 5 V
1
RPD
Tri-level pulldown resistance
To GND
170
kΩ
RPU
Tri-level pullup resistance
To VINT
340
kΩ
1.1
V
V
5.5
V
mV
–1
30
μA
μA
CONTROL OUTPUTS (nFAULT)
VOL
Output logic low voltage
IO = 5 mA
IOH
Output logic high leakage
VO = 3.3 V
–1
0.5
V
1
μA
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Electrical Characteristics (continued)
TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ON)
High-side FET on resistance
RDS(ON)
Low-side FET on resistance
IOFF
Off-state leakage current
tRISE
Output rise time
tFALL
Output fall time
tDEAD
Output dead time
VM = 12 V, I = 0.5 A, TJ = 25°C
550
VM = 12 V, I = 0.5 A, TJ = 85°C (1)
660
VM = 12 V, I = 0.5 A, TJ = 25°C
350
VM = 12 V, I = 0.5 A, TJ = 85°C (1)
420
VM = 5 V, TJ = 25°C
mΩ
mΩ
–1
Internal dead time
1
μA
60
ns
60
ns
200
ns
PWM CURRENT CONTROL (VREF, AISEN, BISEN)
IREF
Externally applied VREF input current
VREF = 1 to 3.3 V
VTRIP
xISEN trip voltage
For 100% current step with VREF = 3.3 V
500
1
mV
AISENSE
Current sense amplifer gain
Reference only
6.6
V/V
TOFF_SEL = GND
20
tOFF
Current control constant off time
TOFF_SEL = Hi-Z
10
TOFF_SEL = VINT
30
μA
μs
PROTECTION CIRCUITS
VM falling; UVLO report
2.9
VUVLO
VM undervoltage lockout
IOCP
Overcurrent protection trip level
tOCP
Overcurrent deglitch time
2.8
μs
tRETRY
Overcurrent protection period
1.6
ms
TTSD
Thermal shutdown temperature
Die temperature TJ
THYS
Thermal shutdown hysteresis
Die temperature TJ
(1)
VM rising; UVLO recovery
V
3
2
150
A
160
180
°C
50
°C
Not tested in production; limits are based on characterization data
6.6 Timing Requirements
TA = 25°C, over recommended operating conditions unless otherwise noted
NO.
MIN
MAX
UNIT
250
kHz
1
ƒSTEP
Step frequency
2
tWH(STEP)
Pulse duration, STEP high
1.9
μs
3
tWL(STEP)
Pulse duration, STEP low
1.9
μs
4
tSU(STEP)
Setup time, DIR or Mx to STEP rising
200
ns
5
tH(STEP)
Hold time, DIR or Mx to STEP rising
200
ns
1
2
3
STEP
DIR, M0, M1
4
5
Figure 1. Timing Diagram
6
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5.5
3.5
5
3
4.5
2.5
IVMQ (PA)
IVM (mA)
6.7 Typical Characteristics
4
3.5
3
2
1.5
1
-40qC
25qC
85qC
125qC
2.5
-40qC
25qC
85qC
125qC
0.5
0
2
0
5
10
VM (V)
15
0
20
5
D001
Figure 2. IVM vs VM
10
VM (V)
15
20
D001
Figure 3. IVMQ vs VM
1.8
1.8
1.6
1.6
RDSON HS + LS (:)
RDSON HS + LS (:)
1.4
1.2
1
0.8
0.6
-40qC
25qC
85qC
125qC
0.4
0.2
5
10
VM (V)
15
1.2
1
4V
12 V
18 V
0.8
0
0
1.4
20
0.6
-50
D001
Figure 4. RDSON vs VM
0
50
TA (qC)
100
150
D004
Figure 5. RDSON vs Temperature
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7 Detailed Description
7.1 Overview
The DRV8846 is an integrated motor driver solution for bipolar stepper motors. The device integrates 2 H-bridges
that use NMOS low-side drivers and PMOS high-side drivers, current sense regulation circuitry, and a
microstepping indexer. The DRV8846 can be powered with a supply range between 4 to 18 V and is capable of
providing an output current to 1.4-A full scale per H-bridge.
A simple STEP/DIR interface allows easy interfacing to the controller circuit. The internal indexer is able to
execute high-accuracy microstepping without requiring the processor to control the current level.
The PWM off-time, tOFF can be adjusted to 10, 20, or 30 μs.
The DRV8846 has an smart tune feature that automatically adjusts the decay setting to minimize current ripple
while still reacting quickly to step changes. This feature allows the DRV8846 to quickly be integrated into a
system.
A torque DAC feature allows the controller to scale the output current without needing to scale the analog
reference voltage input VREF. The torque DAC is accessed using digital input pins. This allows the controller to
save power by decreasing the current consumption when not required.
A low-power sleep mode is included, which allows the system to save power when not driving the motor.
8
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7.2 Functional Block Diagram
VM
VM
VM
+
0.1 µF
VINT
Internal Ref and
Regs
2.2 µF
10 µF
VREF
VM
AOUT1
nENBL
STEP
DIR
Gate
Drive
and
OCP
VINT
M0
Step
Motor
VM
VINT
AOUT2
M1
VINT
I0
VINT
AISEN
ISEN
I1
VINT
Logic
VREF
VM
TOFF_SEL
VINT
nSLEEP
BOUT1
nFAULT
Gate
Drive
and
OCP
ADEC
VM
VINT
BOUT2
DEC0
VINT
DEC1
ISEN
OverTemp
BISEN
VREF
PPAD
GND
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7.3 Feature Description
Table 1 lists the recommended external components for the device.
Table 1. External Components
(1)
COMPONENT
PIN 1
PIN 2
CVM
VM
GND
10-µF (minimum) ceramic capacitor rated for VM
RECOMMENDED
CVM
VM
GND
0.1-µF ceramic capacitor rated for VM
6.3-V, 2.2-µF ceramic capacitor
CVINT
VINT
GND
RnFAULT
VCC (1)
nFAULT
RAISEN
AISEN
GND
Sense resistor, see applications section for sizing
RBISEN
BISEN
GND
Sense resistor, see applications section for sizing
>5 kΩ
VCC is not a pin on the DRV8846, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled
up to VINT through a resistor RnFAULT
7.3.1 PWM Motor Drivers
DRV8846 contains two identical H-bridge motor drivers with current-control PWM circuitry. Figure 6 shows a
block diagram of the circuitry.
VM
OCP
VM
STEP
xOUT1
Indexer
DIR
Predrive
Step
Motor
xOUT2
To other
channel
PWM
VREF
Internal
reference
OCP
To other
channel
±
A = 6.6
xISEN
+
Optional
I1
I0
3level
Input
buffer
DAC
3
From Indexer
5
SIN
DAC
Figure 6. PWM Motor Driver Circuitry
7.3.2 Micro-Stepping Indexer
To allow a simple step and direction interface to control stepper motors, the DRV8846 contains a microstepping
indexer. The indexer controls the state of the H-bridges automatically. When the correct transition is applied at
the STEP input, the indexer moves to the next step, according to the direction set by the DIR pin. In 1/8, 1/16,
and 1/32 step modes, both the rising and falling edges of the STEP input may be used to advance the indexer,
depending on the M0 / M1 setting.
The nENBL pin disables the output stage in indexer mode. When nENBL = 1, the indexer inputs are still active
and respond to the STEP and DIR input pins; only the output stage is disabled.
10
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The indexer logic in the DRV8846 allows a number of different stepping configurations. The M0 and M1 pins
configure the stepping format (see Table 2).
Table 2. Step Mode Settings
M1
M0
STEP MODE
0
0
Full step (2-phase excitation), rising-edge only
0
Z
1/2 step (1-2 phase excitation), rising-edge only
0
1
1/4 step (W1-2 phase excitation), rising-edge only
Z
0
8 microsteps/step, rising-edge only
Z
Z
8 microsteps/step, rising and falling edges
Z
1
16 microsteps/step, rising-edge only
1
0
16 microsteps/step, rising and falling edges
1
Z
32 microsteps/step, rising-edge only
1
1
32 microsteps/step, rising and falling edges
Note that the M0 and M1 pins are tri-level inputs. These pins can be driven logic low, logic high, or highimpedance (Z), like the I0 and I1 pins described previously.
For 1/8, 1/16, and 1/32-step modes, selections are available to advance the indexer only on the rising edge of
the STEP input, or on both the rising and falling edges.
The step mode may be changed on-the-fly while the motor is moving. The indexer advances to the next valid
state for the new M0 / M1 setting at the next rising edge of STEP.
The home state is 45°. The indexer enters the home state after power-up, after exiting UVLO, or after exiting
sleep mode (see the yellow-shaded cells in Table 3 also indicated with a table note).
Table 3 shows the relative current and step directions for different step mode settings. At each rising edge of the
STEP input, the indexer travels to the next state in the table. The direction is shown with the DIR pin high; if the
DIR pin is low, the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to xOUT2.
Table 3. Relative Current and Step Directions
1/32 STEP
1/16 STEP
1/8 STEP
1/4 STEP
1/2 STEP
1
1
1
1
1
FULL STEP
70%
2
3
2
4
5
3
2
6
7
4
8
9
5
3
2
10
11
6
12
13
7
4
14
15
8
16
17 (1)
9 (1)
5 (1)
3 (1)
2 (1)
1 (1)
18
19
10
20
(1)
WINDING
WINDING
CURRENT A CURRENT B
ELECTRICAL
ANGLE
100%
0%
0
100%
5%
3
100%
10%
6
99%
15%
8
98%
20%
11
97%
24%
14
96%
29%
17
94%
34%
20
92%
38%
23
90%
43%
25
88%
47%
28
86%
51%
31
83%
56%
34
80%
60%
37
77%
63%
39
74%
67%
42
71%
71%
45
67%
74%
48
63%
77%
51
60%
80%
53
The indexer enters the home state after power-up, after exiting UVLO, or after exiting sleep mode.
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Table 3. Relative Current and Step Directions (continued)
1/32 STEP
1/16 STEP
1/8 STEP
21
11
6
1/4 STEP
1/2 STEP
FULL STEP
70%
22
23
12
24
25
13
7
4
26
27
14
28
29
15
8
30
31
16
32
33
17
9
5
3
34
35
18
36
37
19
10
38
39
20
40
41
21
11
6
42
43
22
44
45
23
12
46
47
24
48
49
25
13
7
4
2
50
51
26
52
53
27
14
54
55
28
56
57
29
15
8
58
59
30
60
61
31
16
62
63
32
64
65
33
17
9
5
66
67
12
34
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WINDING
WINDING
CURRENT A CURRENT B
ELECTRICAL
ANGLE
56%
83%
56
51%
86%
59
47%
88%
62
43%
90%
65
38%
92%
68
34%
94%
70
29%
96%
73
24%
97%
76
20%
98%
79
15%
99%
82
10%
100%
84
5%
100%
87
0%
100%
90
–5%
100%
93
–10%
100%
96
–15%
99%
98
–20%
98%
101
–24%
97%
104
–29%
96%
107
–34%
94%
110
–38%
92%
113
–43%
90%
115
–47%
88%
118
–51%
86%
121
–56%
83%
124
–60%
80%
127
–63%
77%
129
–67%
74%
132
–71%
71%
135
–74%
67%
138
–77%
63%
141
–80%
60%
143
–83%
56%
146
–86%
51%
149
–88%
47%
152
–90%
43%
155
–92%
38%
158
–94%
34%
160
–96%
29%
163
–97%
24%
166
–98%
20%
169
–99%
15%
172
–100%
10%
174
–100%
5%
177
–100%
0%
180
–100%
–5%
183
–100%
–10%
186
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Table 3. Relative Current and Step Directions (continued)
1/32 STEP
1/16 STEP
1/8 STEP
35
18
1/4 STEP
1/2 STEP
FULL STEP
70%
68
69
70
71
36
72
73
37
19
10
74
75
38
76
77
39
20
78
79
40
80
81
41
21
11
6
3
82
83
42
84
85
43
22
86
87
44
88
89
45
23
12
90
91
46
92
93
47
24
94
95
48
96
97
49
25
13
7
98
99
50
100
101
51
26
102
103
52
104
105
53
27
14
106
107
54
108
109
55
28
110
111
56
112
113
57
29
15
8
4
114
WINDING
WINDING
CURRENT A CURRENT B
ELECTRICAL
ANGLE
–99%
–15%
188
–98%
–20%
191
–97%
–24%
194
–96%
–29%
197
–94%
–34%
200
–92%
–38%
203
–90%
–43%
205
–88%
–47%
208
–86%
–51%
211
–83%
–56%
214
–80%
–60%
217
–77%
–63%
219
–74%
–67%
222
–71%
–71%
225
–67%
–74%
228
–63%
–77%
231
–60%
–80%
233
–56%
–83%
236
–51%
–86%
239
–47%
–88%
242
–43%
–90%
245
–38%
–92%
248
–34%
–94%
250
–29%
–96%
253
–24%
–97%
256
–20%
–98%
259
–15%
–99%
262
–10%
–100%
264
–5%
–100%
267
0%
–100%
270
5%
–100%
273
10%
–100%
276
15%
–99%
278
20%
–98%
281
24%
–97%
284
29%
–96%
287
34%
–94%
290
38%
–92%
293
43%
–90%
295
47%
–88%
298
51%
–86%
301
56%
–83%
304
60%
–80%
307
63%
–77%
309
67%
–74%
312
71%
–71%
315
74%
–67%
318
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Table 3. Relative Current and Step Directions (continued)
1/32 STEP
1/16 STEP
115
58
1/8 STEP
1/4 STEP
1/2 STEP
FULL STEP
70%
WINDING
WINDING
CURRENT A CURRENT B
116
117
59
30
118
119
60
120
121
61
31
16
122
123
62
124
125
63
32
126
127
64
128
ELECTRICAL
ANGLE
77%
–63%
321
80%
–60%
323
83%
–56%
326
86%
–51%
329
88%
–47%
332
90%
–43%
335
92%
–38%
338
94%
–34%
340
96%
–29%
343
97%
–24%
346
98%
–20%
349
99%
–15%
352
100%
–10%
354
100%
–5%
357
7.3.3 Current Regulation
The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation
circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage,
inductance of the winding, and the magnitude of the back EMF present. After the current reaches the current
chopping threshold, the bridge enters a decay mode for a fixed period of time to decrease the current, which is
configurable between 10 to 30 µs through the tri-level input TOFF_SEL. After the time expires, the bridge is reenabled, starting another PWM cycle.
Table 4. Fixed Off-Time Selection
TOFF_SEL
TOFF Duration
0
20 μs
Z
10 μs
1
30 μs
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pin, with a reference voltage. The reference voltage can be supplied by an internal
reference of 3.3 V (which requires VINT to be connected to VREF), or externally supplied to the VREF pin. The
reference voltage is then scaled first by the 3-bit torque DAC, then by the output of a sine lookup table that is
applied to a sine-weighted DAC (sine DAC). The voltage is attenuated by a factor of 6.6.
The full-scale (100%) chopping current is calculated as follows:
VREF
IFS
u TORQUE
6.6 u RISENSE
where
•
•
•
•
IFS is the full scale regulated current
VREF is the voltage on the VREF pin
RISENSE is the resistance of the sense resistor
TORQUE is the scaling percentage from the torque DAC.
(1)
Example: Using VREF is 3.3 V, torque DAC = 100%, and a 500-mΩ sense resistor, the full-scale chopping
current is 3.3 V / (6.6 × 500 mΩ) × 100% = 1 A.
The current for both motor windings is scaled depending on the I0 and I1 pins, which drive a 3-bit linear DAC, as
in Table 5.
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Table 5. Torque DAC Settings
I1
I0
CURRENT SCALING (TORQUE)
0
0
100%
0
Z
87.5%
0
1
75%
Z
0
62.5%
Z
Z
50%
Z
1
37.5%
1
0
25%
1
Z
12.5%
1
1
0% (outputs disabled)
Table 6 gives the xISEN trip voltage at a given DAC code and I[1:0] setting.
Table 6. Torque DAC xISENS Trip Levels (VREF = 3.3 V)
Torque DAC I[1:0] Setting
Sine DAC
Code
00 - 100%
0Z - 87.5%
01 - 75%
Z0 - 62.5%
ZZ - 50%
Z1 - 37.5%
10 - 25%
1Z - 12.5%
31
500 mV
438 mV
375 mV
313 mV
250 mV
188 mV
125 mV
63 mV
30
500 mV
438 mV
375 mV
313 mV
250 mV
188 mV
125 mV
63 mV
29
495 mV
433 mV
371 mV
309 mV
248 mV
186 mV
124 mV
62 mV
28
490 mV
429 mV
368 mV
306 mV
245 mV
184 mV
123 mV
61 mV
27
485 mV
424 mV
364 mV
303 mV
243 mV
182 mV
121 mV
61 mV
26
480 mV
420 mV
360 mV
300 mV
240 mV
180 mV
120 mV
60 mV
25
470 mV
411 mV
353 mV
294 mV
235 mV
176 mV
118 mV
59 mV
24
460 mV
403 mV
345 mV
288 mV
230 mV
173 mV
115 mV
58 mV
23
450 mV
394 mV
338 mV
281 mV
225 mV
169 mV
113 mV
56 mV
22
440 mV
385 mV
330 mV
275 mV
220 mV
165 mV
110 mV
55 mV
21
430 mV
376 mV
323 mV
269 mV
215 mV
161 mV
108 mV
54 mV
20
415 mV
363 mV
311 mV
259 mV
208 mV
156 mV
104 mV
52 mV
19
400 mV
350 mV
300 mV
250 mV
200 mV
150 mV
100 mV
50 mV
18
385 mV
337 mV
289 mV
241 mV
193 mV
144 mV
96 mV
48 mV
17
370 mV
324 mV
278 mV
231 mV
185 mV
139 mV
93 mV
46 mV
16
355 mV
311 mV
266 mV
222 mV
178 mV
133 mV
89 mV
44 mV
15
335 mV
293 mV
251 mV
209 mV
168 mV
126 mV
84 mV
42 mV
14
315 mV
276 mV
236 mV
197 mV
158 mV
118 mV
79 mV
39 mV
13
300 mV
263 mV
225 mV
188 mV
150 mV
113 mV
75 mV
38 mV
12
280 mV
245 mV
210 mV
175 mV
140 mV
105 mV
70 mV
35 mV
11
255 mV
223 mV
191 mV
159 mV
128 mV
96 mV
64 mV
32 mV
10
235 mV
206 mV
176 mV
147 mV
118 mV
88 mV
59 mV
29 mV
9
215 mV
188 mV
161 mV
134 mV
108 mV
81 mV
54 mV
27 mV
8
190 mV
166 mV
143 mV
119 mV
95 mV
71 mV
48 mV
24 mV
7
170 mV
149 mV
128 mV
106 mV
85 mV
64 mV
43 mV
21 mV
6
145 mV
127 mV
109 mV
91 mV
73 mV
54 mV
36 mV
18 mV
5
120 mV
105 mV
90 mV
75 mV
60 mV
45 mV
30 mV
15 mV
4
100 mV
88 mV
75 mV
63 mV
50 mV
38 mV
25 mV
13 mV
3
75 mV
66 mV
56 mV
47 mV
38 mV
28 mV
19 mV
9 mV
2
50 mV
44 mV
38 mV
31 mV
25 mV
19 mV
13 mV
6 mV
1
25 mV
22 mV
19 mV
16 mV
13 mV
9 mV
6 mV
3 mV
0
0 mV
0 mV
0 mV
0 mV
0 mV
0 mV
0 mV
0 mV
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7.3.4 Decay Mode
After the chopping current threshold is reached, the drive current is interrupted, but due to the inductive nature of
the motor, current must continue to flow for some period of time (called recirculation current). To handle this
recirculation current, the H-bridge can operate in two different states, fast decay or slow decay (or a mixture of
fast and slow decay).
In fast-decay mode, after the PWM chopping current level is reached, the H-bridge reverses state to allow
winding current to flow through the opposing FETs. As the winding current approaches 0, the bridge is disabled
to prevent any reverse current flow. For fast-decay mode, see number 2 in Figure 7.
In slow-decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. For
slow-decay mode, see number 3 in Figure 7.
xVM
1 Drive Current
1
2 Fast decay
xOUT2
xOUT1
3 Slow decay
2
3
Figure 7. Decay Modes
The DRV8846 supports fast, slow, mixed, and smart tune modes. With stepper motors, the decay mode is
chosen for a given stepper motor and operating conditions to minimize mechanical noise and vibration.
In mixed decay mode, the current recirculation begins as fast decay, but at a fixed period of time (determined by
the state of the DEC1 and DEC0 pins shown in Table 7) the current recirculation switches to slow decay mode
for the remainder of the fixed PWM period. Note that the DEC1 and DEC0 pins are tri-level inputs; these pins
can be driven logic low, logic high, or high-impedance (Z).
Figure 8 shows the current waveforms in slow, fast, and 25% and 1 tBLANK mixed decay modes.
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PWM
ON
PWM OFF (tOFF)
Slow Decay
Fast Decay
Mixed Decay
25%
25% of cycle
1 tBLANK
Mixed Decay
1 tBLANK
Itrip
PWM CYCLE
Figure 8. Decay Behavior
Table 7. Decay Pins Configuration
DEC1
DEC0
Decay Mode (Increasing Current)
Decay Mode (Decreasing Current)
0
0
Slow decay
Slow decay
0
Z
Slow decay
Mixed decay: 25% fast
0
1
Slow decay
Mixed decay: 1 tBLANK
Z
0
Mixed decay: 1 tBLANK
Mixed decay: 1 tBLANK
Z
Z
Mixed decay: 50% fast
Mixed decay: 50% fast
Z
1
Mixed decay: 25% fast
Mixed decay: 25% fast
1
0
Slow decay
Mixed decay: 50% fast
1
Z
Slow decay
Mixed decay: 12.5% fast
1
1
Slow decay
Fast decay
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AOUT Current
Figure 9 shows increasing and decreasing current. When current is decreasing, the decay mode used is fast,
slow, or mixed as commanded by the DEC1 and DEC0 pins. Three DEC pin selections allow for mixed decay
during increasing current.
Increasing Decreasing
Increasing Decreasing
BOUT Current
STEP Input
Decreasing
Increasing
Increasing Decreasing
STEP Input
Figure 9. Increasing and Decreasing Current
Smart tune mode simplifies the decay mode selection by dynamically changing to adjust for current level, step
change, supply variation, BEMF, and load. To enable smart tune mode, pull the ADEC pin to logic high and pull
DEC0 and DEC1 pins to logic high. The state of the ADEC pin is only evaluated when exiting sleep mode.
(ADEC pin must be high before exiting sleep to enable smart tune mode.)
Smart tune adjusts the time spent in fast decay to minimize current ripple and quickly adjust to current-step
changes. If the drive time is longer than the minimum (tBLANK), in order to reach the current trip point, the decay
mode applied is slow decay (see Figure 10).
Iref
tON
tBLANK
tBLANK
tBLANK
tOFF (fixed)
tON
tOFF (fixed)
tON
tOFF (fixed)
FET Drive On (FWD or REV)
Slow Decay
Figure 10. Smart Tune – Slow Decay Operation
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When the minimum drive time (tBLANK) provides more current than the regulation point, fast decay of 1- tBLANK is
applied. If the second drive period also provides more current than the regulation point, fast decay of 2 tBLANK is
applied. If a third (or more) consecutive period provides more current than the regulation point, fast decay using
25% of tOFF time is applied. When the minimum drive time is insufficient to reach the current regulation level,
slow decay is applied until the current exceeds the current reference level (see Figure 11).
Iref
t
tBLANKBLANK
tBLANK
tBLANK
tOFF (fixed)
tOFF (fixed)
tBLANK
tBLANK toff 25%
tOFF (fixed)
tBLANK
tOFF (fixed)
FET Drive On (FWD or REV)
Slow Decay
Fast Decay
Figure 11. Smart Tune – Mixed Decay Operation
Figure 12 shows a case for smart tune where a step occurs. The system starts with 1 tBLANK of fast decay and
works up to 25% of tOFF time for fast decay until the current is regulated again.
Iref
tBLANK
tBLANK
tBLANK
tOFF (fixed)
tBLANK
tOFF (fixed)
tBLANK tBLANK
tBLANK
tBLANK
tOFF (fixed)
tBLANK
tOFF (fixed)
tBLANKtoff 25%
STEP
tBLANKtoff 25%
FET Drive On (FWD or REV)
tBLANKtoff 25%
Slow Decay
tBLANK
Fast Decay
Figure 12. Smart Tune – Step Operation
7.3.5 Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a period of time before
enabling the current sense circuitry. Note that the blanking time also sets the minimum drive time of the PWM.
The time, tBLANK, is determined by the sine DAC code and the torque DAC setting. The timing information for
tBLANK is given in Table 8.
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Table 8. tBLANK Settings
Torque DAC I[1:0] Setting
Sine DAC
Code
00 - 100%
0Z - 87.5%
01 - 75%
Z0 - 62.5%
ZZ - 50%
Z1 - 37.5%
10 - 25%
1Z - 12.5%
31
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
30
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
29
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
28
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
27
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
26
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
25
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
24
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
23
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
22
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
21
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
20
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
19
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
18
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
17
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
16
1.80 µs
1.80 µs
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
0.90 µs
15
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
14
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
13
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
12
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
11
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
10
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
9
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
8
1.50 µs
1.50 µs
1.50 µs
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
7
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
6
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
5
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
4
1.20 µs
1.20 µs
1.20 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
3
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
2
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
1
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
0.90 µs
7.3.6 Protection Circuits
The DRV8846 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.6.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this
analog current limit persists for longer than the OCP deglitch time tOCP, all FETs in the H-bridge are disabled and
the nFAULT pin is driven low. The device remains disabled until the retry time, tRETRY, occurs. The OCP is
independent for each H-bridge.
Overcurrent conditions are detected independently on both high-side and low-side devices; that is, a short to
ground, supply, or across the motor winding all result in an OCP event. Note that OCP does not use the current
sense circuitry used for PWM current control, so OCP functions without the presence of the xISEN resistors.
20
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7.3.6.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled and the nFAULT pin is driven
low. After the die temperature falls to a safe level, operation automatically resumes. The nFAULT pin is released
after operation has resumed.
7.3.6.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, and all internal logic is reset. Operation resumes when VM rises above the UVLO rising
threshold. The nFAULT pin is driven low during an undervoltage condition and is released after operation has
resumed.
Table 9. Fault Behavior
Error Report
H-Bridge
Internal Circuits
VM UVLO
Fault
nFAULT unlatched
Disabled
Shut down
System and fault clears on recovery
Recovery
OCP
nFAULT unlatched
Disabled
Operating
System and fault clears on recovery and motor is driven
after time, tRETRY
TSD
nFAULT unlatched
Disabled
Operating
System and fault clears on recovery
7.4 Device Functional Modes
The DRV8846 device is active unless the nSLEEP pin is driven low. In sleep mode, the VINT regulator is
disabled and the H-bridge FETs are disabled (Hi-Z). The time tSLEEP must elapse after a falling edge on the
nSLEEP pin before the device enters sleep mode. The DRV8846 is brought out of sleep mode by bringing the
nSLEEP pin high. The time tWAKE must elapse, after nSLEEP is brought high, before the outputs change state.
If the nENBL pin is brought high, the H-bridge outputs are disabled, but the internal logic is still active. An
appropriate edge on STEP (depending on the step mode) advances the indexer, but the outputs do not change
state until nENBL is driven low.
Table 10. Operating Modes
Mode
Condition
H-Bridge
VINT
Indexer
Operating
4 V < VM < 18 V
nSLEEP pin = 1
nENBL = 0
Operating
Operating
Operating
Disabled
4 V < VM < 18 V
nSLEEP pin = 1
nENBL = 1
Disabled
Operating
Operating
Sleep
4 V < VM < 18 V
nSLEEP pin = 0
Disabled
Disabled
Disabled
Fault
Any fault condition met
Disabled
Depends on fault
Depends on fault
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8846 is used in stepper motor control.
8.2 Typical Application
Step
Motor
ADEC
I0
I1
DEC0
nSLEEP
DEC1
The following design procedure can be used to configure the DRV8846.
AOUT1
GND
AISEN
VINT
500 PŸ
DRV8846
AOUT2
NC
BOUT2
VM
GND
(PPAD)
500 PŸ
BISEN
VREF
VCC
17
16
15
2.2 µF
0.1 µF
10 µF
VM
14
13
STEP
nENBL
TOFF_SEL
M1
M0
DIR
nFAULT
BOUT1
18
10 NŸ
logic supply
22
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Typical Application (continued)
8.2.1 Design Requirements
Table 11 gives design input parameters for system design.
Table 11. System Design Input Parameters
DESIGN PARAMETER
Nominal supply voltage
Supply voltage range
Motor winding resistance
Motor winding inductance
REFERENCE
VM
EXAMPLE VALUE
12 V
4 to 18 V
RL
3.0 Ω/phase
LL
330 µH/phase
Motor full step angle
θstep
1.8°/step
Target stepping level
nm
1/8 step
Target motor speed
v
400 rpm
Target chopping current
ICHOP
500 mA
Chopping current reference voltage
VREF
3.3 V
TORQUE
100%
Current scaling
8.2.2 Detailed Design Procedure
8.2.2.1 Stepper Motor Speed
The first step in configuring the DRV8846 requires the desired motor speed and stepping level. The DRV8846
can support from full step to 1/32 step mode.
If the target motor speed is too high, the motor will not spin. Make sure that the motor can support the target
speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
v(rpm) u nm (steps) u 6
¦step VWHSV V
Tstep (q / step)
(2)
θstep can be found in the stepper motor data sheet or often written on the motor itself.
For DRV8846, the microstepping levels are set by the M0/M1 pins and can be any of the settings in Table 2.
Higher microstepping means a smoother motor motion and less audible noise, but increases the switching losses
and requires a higher ƒstep to achieve the same motor speed.
8.2.2.2 Current Regulation
The chopping current (ICHOP) is the maximum current driven through either winding. This quantity will depend on
the sense resistor value (RXISEN).
VREF
ICHOP
u TORQUE
6.6 u RISENSE
(3)
ICHOP is set by a comparator which compares the voltage across RXISEN to a reference voltage. Note that ICHOP
must follow Equation 4 to avoid saturating the motor.
VM (V)
ICHOP (A)
RL (:) 2 u RDS(ON) (:) RSENSE (:)
where
•
•
VM is the motor supply voltage.
RL is the motor winding resistance.
(4)
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8.2.2.3 Decay Modes
The DRV8846 supports four different decay modes: slow decay, fast decay, mixed decay, and smart tune. The
first selection to try is the smart tune mode, which adjusts the decay mode automatically to improve current
regulation. The current through the motor windings is regulated using a fixed-off-time PWM scheme. This means
that after any drive phase, when a motor has reached the current chopping threshold (ICHOP), the DRV8846
places the motor in one of the four decay modes until the PWM cycle has expired. Afterward, a new drive phase
starts.
The blanking time, tBLANK, defines the minimum drive time for the current chopping. ICHOP is ignored during tBLANK,
so the winding current may overshoot the trip level during this blanking period.
8.2.3 Application Curves
Figure 13. Microstepping Waveform, Phase A, Smart Tune
24
Figure 14. Microstepping Waveform, Smart Tune, Step
Current Regulation
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9 Power Supply Recommendations
The DRV8846 is designed to operate from an input voltage supply (VM) range between 4 and 18 V. A 0.1-μF
ceramic capacitor rated for VM must be placed as close to the DRV8846 as possible. In addition, a bulk 10-μF
capacitor must be included on VM.
10 Layout
10.1 Layout Guidelines
The VM terminal should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended
value of 10 μF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace
or ground plane connection to the device GND pin.
Bypass VINT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin
as possible.
I0
ADEC
I1
DEC0
nSLEEP
DEC1
10.2 Layout Example
2.2 µF
GND
AOUT1
10 µF
AISEN
VINT
AOUT2
NC
BOUT2
VM
BISEN
VREF
BOUT1
DIR
STEP
nENBL
TOFF_SEL
M1
nFAULT
RBISEN
M0
0.1 µF
RAISEN
Figure 15. Layout Recommendation
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Achieving Changeable Holding Current of a DRV88x Stepper Motor Driver
• DRV8846 Evaluation Module
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8846RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8846
DRV8846RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8846
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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