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DRV8886
SLVSDA4C – JANUARY 2017 – REVISED MARCH 2020
DRV8886 2-A Stepper Motor Driver With Integrated Current Sense
1 Features
3 Description
•
The DRV8886 is a stepper motor driver for industrial
and consumer end equipment applications. The
device is fully integrated with two N-channel power
MOSFET H-bridge drivers, a microstepping indexer,
and integrated current sensing. The DRV8886 is
capable of driving up to 2-A full scale or 1.4-A rms
output current (24-V and TA = 25°C, dependent on
PCB design).
•
•
•
•
•
•
•
•
•
•
PWM microstepping stepper motor driver
– Up to 1/16 microstepping
– Non-circular and standard ½ step modes
Integrated current sense functionality
– No sense resistors required
– ±6.25% Full-scale current accuracy
Slow and mixed decay options
8 to 37-V Operating supply voltage range
Low RDS(ON): 550 mΩ HS + LS at 24 V, 25°C
High current capacity
– 3-A Peak per bridge
– 2-A Full-scale per bridge
– 1.4-A rms per bridge
Fixed off-time PWM current regulation
Simple STEP/DIR interface
Low-current sleep mode (20 μA)
Small package and footprint
– 24 HTSSOP PowerPAD™ package
– 28 WQFN package
Protection features
– VM Undervoltage lockout (UVLO)
– Charge pump undervoltage (CPUV)
– Overcurrent protection (OCP)
– Thermal shutdown (TSD)
– Fault condition indication pin (nFAULT)
2 Applications
Device protection features are provided for supply
undervoltage, charge pump faults, overcurrent, short
circuits, and overtemperature. Fault conditions are
indicated by the nFAULT pin.
Device Information
PART NUMBER
DRV8886
PACKAGE
(1)
BODY SIZE (NOM)
HTSSOP (24)
7.80 mm × 4.40 mm
WQFN (28)
5.50 mm × 3.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
8 to 37 V
DRV8886
STEP
DIR
M
2A
±
Bipolar stepper motors
Multi-function printers and scanners
Laser beam printers
3D printers
Automatic teller and money handling machines
Video security cameras
Office automation machines
Factory automation and robotics
A simple STEP/DIR interface allows an external
controller to manage the direction and step rate of the
stepper motor. The device can be configured in
different step modes ranging from full-step to 1/16
microstepping. A low-power sleep mode is provided
for very low standby quiescent standby current using
a dedicated nSLEEP pin.
+
•
•
•
•
•
•
•
•
The DRV8886 uses an internal current sense
architecture to eliminate the need for two external
power sense resistors, saving PCB area and system
cost. The DRV8886 uses an internal fixed off-time
PWM current regulation scheme adjustable between
slow and mixed decay options.
Controller
1
Step Size
Decay Mode
nFAULT
Stepper Motor
Driver
Current Sense
+
±
2A
1/16 µstep
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8886
SLVSDA4C – JANUARY 2017 – REVISED MARCH 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Indexer Timing Requirements...................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 32
8
Application and Implementation ........................ 33
8.1 Application Information............................................ 33
8.2 Typical Application .................................................. 33
9
Power Supply Recommendations...................... 36
9.1 Bulk Capacitance ................................................... 36
10 Layout................................................................... 37
10.1 Layout Guidelines ................................................. 37
10.2 Layout Example .................................................... 37
11 Device and Documentation Support ................. 38
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
38
12 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2018) to Revision C
•
Added Various Sources of Error and Application-Specific Error Calculations sections. ...................................................... 18
Changes from Revision A (July 2018) to Revision B
•
Page
Page
Changed device status from Advanced Information to Production Data................................................................................ 1
Changes from Original (January 2017) to Revision A
Page
•
Added the WQFN package option.......................................................................................................................................... 1
•
Changed the units of the High-Side and Low-Side RDS(ON) axis labels from mΩ to Ω in the high-side and low-side
RDS(ON) over VM and over temperature graphs ...................................................................................................................... 9
2
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SLVSDA4C – JANUARY 2017 – REVISED MARCH 2020
5 Pin Configuration and Functions
PWP PowerPAD™ Package
24-Pin HTSSOP
Top View
22
M1
VM
4
21
M0
AOUT1
5
20
DIR
PGND
6
19
STEP
18
ENABLE
Thermal
AOUT2
7
Pad
BOUT2
8
17
nSLEEP
PGND
9
16
RREF
BOUT1
10
15
nFAULT
VM
11
14
DVDD
GND
12
13
AVDD
DECAY
3
25
VCP
VCP
1
24
TRQ
VM
2
23
M1
AOUT1
3
22
M0
PGND
4
21
DIR
AOUT2
5
20
STEP
Thermal
Pad
BOUT2
6
19
ENABLE
PGND
7
18
nSLEEP
BOUT1
8
17
RREF
VM
9
16
nFAULT
10
15
NC
11
GND
14
TRQ
NC
23
CPL
2
26
CPH
27
DECAY
13
24
12
1
CPH
CPL
28
RHR Package
28-Pin WQFN With Exposed Thermal Pad
Top View
NC
AVDD
DVDD
NC
Not to scale
Not to scale
Pin Functions
PIN
NAME
TYPE (1)
NO.
HTSSOP
WQFN
AOUT1
5
3
AOUT2
7
5
AVDD
13
12
BOUT1
10
8
BOUT2
8
6
CPH
2
28
CPL
1
27
DECAY
24
25
DIR
20
DVDD
14
ENABLE
O
PWR
O
DESCRIPTION
Winding A output. Connect to stepper motor winding.
Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor.
Winding B output. Connect to stepper motor winding.
PWR
Charge pump switching node. Connect a X5R or X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL.
I
Decay-mode setting. Sets the decay mode (see the Decay Modes section). Decay mode can be adjusted during
operation.
21
I
Direction input. Logic level sets the direction of stepping; internal pulldown resistor.
13
PWR
18
19
I
GND
12
10
PWR
M0
21
22
M1
22
23
I
Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor.
Enable driver input. Logic high to enable device outputs; logic low to disable; internal pulldown resistor.
Device ground. Connect to system ground.
Microstepping mode-setting. Sets the step mode; tri-level pins; sets the step mode; internal pulldown resistor.
11
NC
—
14
15
—
No connect. No internal connection
26
PGND
RREF
(1)
6
4
9
7
16
17
PWR
I
Power ground. Connect to system ground.
Current-limit analog input. Connect a resistor to ground to set full-scale regulation current.
I = input, O = output, PWR = power, OD = open-drain
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Pin Functions (continued)
PIN
NAME
TYPE (1)
NO.
DESCRIPTION
HTSSOP
WQFN
STEP
19
20
I
Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor.
TRQ
23
24
I
Current-scaling control. Scales the output current; tri-level pin.
VCP
3
1
PWR
Charge pump output. Connect a X5R or X7R, 0.22-μF, 16-V ceramic capacitor to VM.
4
2
11
9
PWR
Power supply. Connect to motor supply voltage and bypass to GND with two 0.01-μF ceramic capacitors (one for
each pin) plus a bulk capacitor rated for VM.
nFAULT
15
16
OD
Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
nSLEEP
17
18
I
Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown
resistor.
VM
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Power supply voltage (VM)
Power supply voltage ramp rate (VM)
MIN
MAX
UNIT
–0.3
40
V
0
2
V/µs
Charge pump voltage (VCP, CPH)
–0.3
VM + 7
V
Charge pump negative switching pin (CPL)
–0.3
VM
V
Internal regulator voltage (DVDD)
–0.3
3.8
V
Internal regulator current output (DVDD)
0
1
mA
Internal regulator voltage (AVDD)
–0.3
5.7
V
Control pin voltage (STEP, DIR, ENABLE, nFAULT, M0, M1, DECAY, TRQ, nSLEEP)
–0.3
5.7
V
Open drain output current (nFAULT)
0
10
mA
Current limit input pin voltage (RREF)
–0.3
6.0
V
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
–1.0
VM + 1.0
V
Transient 100 ns phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
–3.0
VM + 3.0
V
0
3
A
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VVM
Power supply voltage (VM)
8
37
V
VI
Input voltage (DECAY, DIR, ENABLE, M0, M1, nSLEEP, STEP,
TRQ)
0
5.3
V
ƒPWM
Applied STEP signal (STEP)
0
100 (1)
kHz
(2)
mA
IDVDD
External load current (DVDD)
0
1
IFS
Motor full-scale current (xOUTx)
0
2 (2)
A
Irms
Motor RMS current (xOUTx)
0
1.4 (2)
A
TA
Operating ambient temperature
–40
125
°C
(1)
(2)
STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load
Power dissipation and thermal limits must be observed
6.4 Thermal Information
DRV8886
THERMAL METRIC (1)
PWP (HTSSOP)
RHR (WQFN)
UNIT
24 PINS
28 PINS
RθJA
Junction-to-ambient thermal resistance
33.8
33.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
18.0
23.1
°C/W
RθJB
Junction-to-board thermal resistance
7.7
12.2
°C/W
ψJT
Junction-to-top characterization parameter
0.2
0.3
°C/W
ψJB
Junction-to-board characterization parameter
7.8
12.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.3
3.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = -40 to 125°C, VVM = 8 to 37 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, DVDD, AVDD)
VVM
VM operating voltage
8
ENABLE = 1, nSLEEP = 1, No motor
load
IVM
VM operating supply current
IVMQ
VM sleep mode supply current
tSLEEP
Sleep time
nSLEEP = 0 to sleep-mode
tWAKE
Wake-up time
tON
Turn-on time
VDVDD
Internal regulator voltage
0- to 1-mA external load
VAVDD
Internal regulator voltage
No external load
5
37
V
8
mA
nSLEEP = 0; TA = 25°C
20
nSLEEP = 0; TA = 125°C (1)
40
μA
50
200
μs
nSLEEP = 1 to output transition
0.85
1.5
ms
VM > UVLO to output transition
0.85
1.5
ms
2.9
3.3
3.6
V
4.5
5
5.5
V
CHARGE PUMP (VCP, CPH, CPL)
VVCP
VCP operating voltage
VM + 5.5
V
LOGIC-LEVEL INPUTS (STEP, DIR, ENABLE, nSLEEP, M1)
VIL
Input logic-low voltage
VIH
Input logic-high voltage
VHYS
Input logic hysteresis
IIL
Input logic-low current
VIN = 0 V
IIH
Input logic-high current
VIN = 5 V
RPD
Pulldown resistance
To GND
Propagation delay
STEP to current change
tPD
(1)
0
0.8
1.6
5.3
200
–1
V
V
mV
1
100
100
μA
μA
kΩ
1.2
μs
0.65
V
1.25
V
5.3
V
TRI-LEVEL INPUT (M0, TRQ)
VIL
Tri-level input logic low voltage
VIZ
Tri-level input Hi-Z voltage
0
VIH
Tri-level input logic high
voltage
IIL
Tri-level input logic low current
VIN = 0 V
IIH
Tri-level input logic high
current
VIN = 5 V
RPD
Tri-level pulldown resistance
VIN = Hi-Z, to GND
RPU
Tri-level pullup resistance
VIN = Hi-Z, to DVDD
0.95
1.1
1.5
–90
μA
155
μA
65
kΩ
130
kΩ
QUAD-LEVEL INPUT (DECAY)
VI1
Quad-level input voltage 1
Can set with 1% 5 kΩ to GND
0
0.14
V
VI2
Quad-level input voltage 2
Can set with 1% 15 kΩ to GND
0.24
0.46
V
VI3
Quad-level input voltage 3
Can set with 1% 44.2 kΩ to GND
0.71
1.24
V
VI4
Quad-level input voltage 4
Can set with 1% 133 kΩ to GND
2.12
5.3
V
IO
Output current
To GND
27.25
μA
17
22
CONTROL OUTPUTS (nFAULT)
VOL
Output logic-low voltage
IO = 1 mA, RPULLUP = 4.7 kΩ
IOH
Output logic-high leakage
VO = 5 V, RPULLUP = 4.7 kΩ
(1)
6
–1
0.5
V
1
μA
Specified by design and characterization data
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Electrical Characteristics (continued)
at TA = -40 to 125°C, VVM = 8 to 37 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ON)
High-side FET on resistance
VM = 24 V, I = 1.4 A, TA = 25°C
290
346
mΩ
RDS(ON)
Low-side FET on resistance
VM = 24 V, I = 1.4 A, TA = 25°C
260
320
mΩ
tRISE
(1)
Output rise time
100
ns
tFALL
(1)
Output fall time
100
ns
Output dead time
200
(1)
tDEAD
Vd
(1)
Body diode forward voltage
IOUT = 0.5 A
ns
0.7
1
V
28.1
30
31.9
kAΩ
1.18
1.232
1.28
V
PWM CURRENT CONTROL (RREF)
ARREF
RREF transimpedance gain
VRREF
RREF voltage
tOFF
PWM off-time
CRREF
Equivalent capacitance on
RREF
tBLANK
ΔITRIP
PWM blanking time
Current trip accuracy
RREF = 18 to 132 kΩ
20
μs
10
IRREF = 2.0 A, 63% to 100% current
setting
1.5
µs
IRREF = 2.0 A, 0% to 63% current
setting
1
IRREF = 1.5 A, 10% to 20% current
setting, 1% reference resistor
–15%
15%
IRREF = 1.5 A, 20% to 63% current
setting, 1% reference resistor
–10%
10%
–6.25%
6.25%
7
7.8
7.2
8
IRREF = 1.5 A, 71% to 100% current
setting, 1% reference resistor
pF
PROTECTION CIRCUITS
VM falling, UVLO report
VUVLO
VM UVLO
VUVLO,HYS
Undervoltage hysteresis
Rising to falling threshold
200
VCPUV
Charge pump undervoltage
VCP falling; CPUV report
VM + 2
IOCP
Overcurrent protection trip
level
Current through any FET
tOCP
(1)
tRETRY
VM rising, UVLO recovery
Overcurrent deglitch time
Overcurrent retry time
TTSD
Die temperature TJ
THYS
(1)
Thermal shutdown hysteresis
Die temperature TJ
V
A
1.9
1
Thermal shutdown
temperature
mV
3
1.3
(1)
V
2.8
μs
1.6
ms
150
°C
20
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6.6 Indexer Timing Requirements
at TA = -40 to 125°C, VVM = 8 to 37 V (unless otherwise noted)
NO.
(1)
MIN
(1)
UNIT
500
kHz
1
ƒSTEP
2
tWH(STEP)
Pulse duration, STEP high
970
ns
3
tWL(STEP)
Pulse duration, STEP low
970
ns
4
tSU(DIR, Mx)
Setup time, DIR or USMx to STEP rising
200
ns
5
tH(DIR,
Hold time, DIR or USMx to STEP rising
200
ns
Mx)
Step frequency
MAX
STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load.
1
2
3
STEP
DIR, Mx
4
5
Figure 1. Timing Diagram
8
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6.7 Typical Characteristics
Over recommended operating conditions (unless otherwise noted)
7
7
TA = 40°C
TA = 25°C
TA = 125°C
6.8
6.8
Supply Current (mA)
Supply Current (mA)
6.6
6.4
6.2
6
5.8
5.6
6.6
6.4
6.2
6
5.4
5
5
10
15
20
25
Supply Voltage (V)
30
35
5.6
-40
40
20
18
18
Sleep Current (PA)
16
14
12
10
8
TA = 40°C
TA = 25°C
TA = 125°C
6
15
20
25
Supply Voltage (V)
30
35
10
6
-40
40
VM = 8 V
VM = 24 V
VM = 37 V
-20
0.38
0.4
0.36
High-Side RDS(ON) (:)
High-Side RDS(ON) (:)
0.45
0.35
0.3
0.25
0.2
0.15
30
120
140
D004
D002
35
0.34
0.32
0.3
0.28
VM = 8 V
VM = 24 V
VM = 37 V
0.24
0
20
25
Supply Voltage (V)
20
40
60
80
100
Ambient Temperature (°C)
0.26
TA = 40°C
TA = 25°C
TA = 125°C
15
0
Figure 5. Sleep Current over Temperature
0.4
10
D002
12
Figure 4. Sleep Current over VM
5
140
14
0.5
0.05
120
16
D003
0.1
20
40
60
80
100
Ambient Temperature (°C)
8
4
10
0
Figure 3. Supply Current over Temperature
20
5
-20
D001
Figure 2. Supply Current over VM
Sleep Current (PA)
VM = 8 V
VM = 24 V
VM = 37 V
5.8
5.2
40
0.22
-40
-20
D005
Figure 6. High-Side RDS(ON) over VM
0
20
40
60
80
100
Ambient Temperature (°C)
120
140
D006
Figure 7. High-Side RDS(ON) over Temperature
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Typical Characteristics (continued)
Over recommended operating conditions (unless otherwise noted)
0.42
0.4
0.4
0.38
Low-Side RDS(ON) (:)
Low-Side RDS(ON) (:)
0.5
0.45
0.35
0.3
0.25
0.2
0.15
0.1
10
15
20
25
Supply Voltage (V)
30
35
0.32
0.3
0.28
0.26
VM = 8 V
VM = 24 V
VM = 37 V
0.22
0.2
-40
0
5
0.34
0.24
TA = 40°C
TA = 25°C
TA = 125°C
0.05
0.36
40
-20
0
D007
Figure 8. Low-Side RDS(ON) over VM
20
40
60
80
100
Ambient Temperature (°C)
140
D008
Figure 9. Low-Side RDS(ON) over Temperature
2
3.339
TRQ = 0
3.336
3.333
3.33
1
TRQ = Z
0.7
TRQ = 1
0.5
3.327
0.3
3.324
IF S (A )
D V D D V o lta g e ( V )
120
3.321
3.318
3.315
T A = 125°C
3.312
T A = 85°C
3.309
0.2
0.1
0.07
0.05
T A = 25°C
0.03
T A = -40°C
0.02
3.306
3.303
0.01
0
0.1
0.2
0.3
0.4
0.5
0.6
DVDD Load (mA)
0.7
0.8
0.9
1
Figure 10. DVDD Regulator over Load (VM = 24 V)
10
10
20
30
40
50 60 70
R REF (k:)
D009
100
200
300
D010
Figure 11. Full-Scale Current over RREF Selection
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7 Detailed Description
7.1 Overview
The DRV8886 device is an integrated motor-driver solution for bipolar stepper motors. The device integrates two
N-channel power MOSFET H-bridges, integrated current sense and regulation circuitry, and a microstepping
indexer. The DRV8886 device can be powered with a supply voltage from 8 to 37 V and is capable of providing
an output current up to 3-A peak, 2-A full-scale, or 1.4-A root mean square (rms). The actual full-scale and rms
current depends on the ambient temperature, supply voltage, and PCB thermal capability.
The DRV8886 device uses an integrated current-sense architecture which eliminates the need for two external
power sense resistors. This architecture removes the power dissipated in the sense resistors by using a current
mirror approach and using the internal power MOSFETs for current sensing. The current regulation set point is
adjusted with a standard low-power resistor connected to the RREF pin. This features reduces external
component cost, board PCB size, and system power consumption.
A simple STEP/DIR interface allows for an external controller to manage the direction and step rate of the
stepper motor. The internal indexer can execute high-accuracy microstepping without requiring the external
controller to manage the winding current level. The indexer is capable of full step, half step, and 1/4, 1/8, 1/16
microstepping. In addition to a standard half stepping mode, a non-circular half stepping mode is available for
increased torque output at higher motor RPM.
The current regulation is configurable between several decay modes. The decay mode can be selected as a
fixed slow, slow-mixed, or mixed decay current regulation scheme. The slow-mixed decay mode uses slow decay
on increasing steps and mixed decay on decreasing steps.
An adaptive blanking time feature automatically scales the minimum drive time with output current level. This
feature helps alleviate zero-crossing distortion by limiting the drive time at low-current steps.
A torque DAC feature allows the controller to scale the output current without needing to scale the RREF
reference resistor. The torque DAC is accessed using a digital input pin which allows the controller to save
system power by decreasing the motor current consumption when high output torque is not required.
A low-power sleep mode is included which allows the system to save power when not actively driving the motor.
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7.2 Functional Block Diagram
VM
0.01 F
VM
0.01 F
Bulk
VM
VM
0.22 F
Power
VCP
AOUT1
CPH
Charge
Pump
0.022 F
CPL
Current
Sense
AVDD
AVDD
Regulator
0.47 F
DVDD
Stepper
Motor
VM
Gate
Drivers
DVDD
Regulator
AOUT2
0.47 F
GND
Digital
Core
STEP
Current
Sense
IREF
PGND
SINE DAC
VM
DIR
ENABLE
BOUT1
nSLEEP
Current
Sense
Control
Inputs
M1
Microstepping
Indexer
DVDD
M0
VM
Gate
Drivers
BOUT2
Adaptive
Blanking
DVDD
TRQ
DVDD
IREF
Current
Sense
PGND
DECAY
SINE DAC
DVDD
VCC
IREF
Protection
Fault Output
Overcurrent
RREF
RREF
RREF
Analog
Input
RPU
nFAULT
Undervoltage
Overtemperature
PPAD
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7.3 Feature Description
Table 1 lists the recommended external components for the DRV8886 device.
Table 1. DRV8886 External Components
COMPONENT
PIN 1
PIN 2
CVM1
VM
GND
Two X5R or X7R, 0.01-µF, VM-rated ceramic capacitors
CVM2
VM
GND
Bulk, VM-rated capacitor
CVCP
VCP
VM
X5R or X7R, 0.22-µF, 16-V ceramic capacitor
CSW
CPH
CPL
X5R or X7R, 0.022-µF, VM-rated ceramic capacitor
CAVDD
AVDD
GND
X5R or X7R, 0.47-µF, 6.3-V ceramic capacitor
GND
X5R or X7R, 0.47-µF, 6.3-V ceramic capacitor
CDVDD
RnFAULT
RREF
(1)
RECOMMENDED
DVDD
VCC
(1)
nFAULT
RREF
>4.7-kΩ resistor
Resistor to limit chopping current must be installed. See the Typical Application
section for value selection.
GND
VCC is not a pin on the DRV8886 device, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be
pulled up to DVDD
7.3.1 Stepper Motor Driver Current Ratings
Stepper motor drivers can be classified using three different numbers to describe the output current: peak, rms,
and full-scale.
7.3.1.1 Peak Current Rating
The peak current in a stepper driver is limited by the overcurrent protection trip threshold, IOCP. The peak current
describes any transient duration current pulse, for example when charging capacitance, when the overall duty
cycle is very low. In general the minimum value of IOCP specifies the peak current rating of the stepper motor
driver. For the DRV8886 device, the peak current rating is 3 A per bridge.
7.3.1.2 rms Current Rating
The rms (average) current is determined by the thermal considerations of the device. The rms current is
calculated based on the RDS(ON), rise and fall time, PWM frequency, device quiescent current, and package
thermal performance in a typical system at 25°C. The actual operating rms current may be higher or lower
depending on heatsinking and ambient temperature. For the DRV8886 device, the rms current rating is 1.4 A per
bridge.
7.3.1.3 Full-Scale Current Rating
The full-scale current describes the top of the sinusoid current waveform while microstepping. Because the
sinusoid amplitude is related to the rms current, the full-scale current is also determined by the thermal
considerations of the device. The full-scale current rating is approximately √2 × IRMS. The full-scale current is set
by the RREF pin and the torque DAC when configuring the DRV8886 device, for details see the Current
Regulation section. For the DRV8886 device, the full-scale current rating is 2 A per bridge.
Full-scale current
Output Current
RMS current
AOUT
BOUT
Step Input
Figure 12. Full-Scale and rms Current
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7.3.2 PWM Motor Drivers
The DRV8886 device has drivers for two full H-bridges to drive the two windings of a bipolar stepper motor.
Figure 13 shows a block diagram of the circuitry.
VM
xOUT1
Current
Sense
Microstepping and
Current Regulation
Logic
VM
Gate
Drivers
xOUT2
Current
Sense
PGND
Figure 13. PWM Motor Driver Block Diagram
7.3.3 Microstepping Indexer
Built-in indexer logic in the DRV8886 device allows a number of different step modes. The M1 and M0 pins are
used to configure the step mode as shown in Table 2.
Table 2. Microstepping Settings
M1
M0
STEP MODE
0
0
Full step (2-phase excitation) with 71% current
0
1
1/16 step
1
0
1/2 step
1
1
1/4 step
0
Z
1/8 step
1
Z
Non-circular 1/2 step
Table 3 shows the relative current and step directions for full-step through 1/16-step operation. The AOUT
current is the sine of the electrical angle and the BOUT current is the cosine of the electrical angle. Positive
current is defined as current flowing from the xOUT1 pin to the xOUT2 pin while driving.
At each rising edge of the STEP input the indexer travels to the next state in the table. The direction is shown
with the DIR pin logic high. If the DIR pin is logic low, the sequence is reversed.
On power-up or when exiting sleep mode, keep the STEP pin logic low, otherwise the indexer advances one
step.
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NOTE
If the step mode is changed from full, 1/2, 1/4, 1/8, or 1/16 to full, 1/2, 1/4, 1/8, or 1/16
while stepping, the indexer advances to the next valid state for the new step mode setting
at the rising edge of STEP. If the step mode is changed from or to noncircular 1/2 step the
indexer goes immediately to the valid state for that mode.
The home state is an electrical angle of 45°. This state is entered after power-up, after exiting logic undervoltage
lockout, or after exiting sleep mode. Table 3 lists the home state in red.
Table 3. Microstepping Relative Current Per Step (DIR = 1)
FULL STEP
1/2 STEP
1/4 STEP
1/8 STEP
1/16 STEP
ELECTRICAL
ANGLE
(DEGREES)
1
1
1
1
2
2
2
3
4
1
2
3
5
6
4
7
8
3
5
9
10
6
11
12
2
4
7
13
14
8
15
16
5
9
17
18
10
19
AOUT
CURRENT (%
FULL-SCALE)
BOUT
CURRENT (%
FULL-SCALE)
0.000°
0%
100%
5.625°
10%
100%
3
11.250°
20%
98%
4
16.875°
29%
96%
5
22.500°
38%
92%
6
28.125°
47%
88%
7
33.750°
56%
83%
8
39.375°
63%
77%
9
45.000°
71%
71%
10
50.625°
77%
63%
11
56.250°
83%
56%
12
61.875°
88%
47%
13
67.500°
92%
38%
14
73.125°
96%
29%
15
78.750°
98%
20%
16
84.375°
100%
10%
17
90.000°
100%
0%
18
95.625°
100%
–10%
19
101.250°
98%
–20%
20
106.875°
96%
–29%
21
112.500°
92%
–38%
22
118.125°
88%
–47%
23
123.750°
83%
–56%
24
129.375°
77%
–63%
25
135.000°
71%
–71%
26
140.625°
63%
–77%
27
146.250°
56%
–83%
28
151.875°
47%
–88%
29
157.500°
38%
–92%
30
163.125°
29%
–96%
31
168.750°
20%
–98%
32
174.375°
10%
–100%
33
180.000°
0%
–100%
34
185.625°
–10%
–100%
35
191.250°
–20%
–98%
36
196.875°
–29%
–96%
37
202.500°
–38%
–92%
38
208.125°
–47%
–88%
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Table 3. Microstepping Relative Current Per Step (DIR = 1) (continued)
FULL STEP
1/2 STEP
3
1/4 STEP
6
11
1/8 STEP
1/16 STEP
ELECTRICAL
ANGLE
(DEGREES)
AOUT
CURRENT (%
FULL-SCALE)
BOUT
CURRENT (%
FULL-SCALE)
20
39
213.750°
–56%
–83%
40
219.375°
–63%
–77%
41
225.000°
–71%
–71%
42
230.625°
–77%
–63%
43
236.250°
–83%
–56%
44
241.875°
–88%
–47%
45
247.500°
–92%
–38%
46
253.125°
–96%
–29%
47
258.750°
–98%
–20%
48
264.375°
–100%
–10%
49
270.000°
–100%
0%
50
275.625°
–100%
10%
51
281.250°
–98%
20%
52
286.875°
–96%
29%
53
292.500°
–92%
38%
54
298.125°
–88%
47%
55
303.750°
–83%
56%
56
309.375°
–77%
63%
57
315.000°
–71%
71%
58
320.625°
–63%
77%
59
326.250°
–56%
83%
60
331.875°
–47%
88%
61
337.500°
–38%
92%
62
343.125°
–29%
96%
63
348.750°
–20%
98%
64
354.375°
–10%
100%
1
360.000°
0%
100%
21
22
12
23
24
7
13
25
26
14
27
28
4
8
15
29
30
16
31
32
1
1
1
Table 4 shows the noncircular 1/2–step operation. This stepping mode consumes more power than circular 1/2step operation, but provides a higher torque at high motor rpm.
Table 4. Non-Circular 1/2-Stepping Current
NON-CIRCULAR 1/2-STEP
16
AOUT CURRENT
(% FULL-SCALE)
BOUT CURRENT
(% FULL-SCALE)
1
0
100
0
2
100
100
45
3
100
0
90
4
100
–100
135
5
0
–100
180
6
–100
–100
225
7
–100
0
270
8
–100
100
315
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ELECTRICAL ANGLE
(DEGREES)
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7.3.4 Current Regulation
The current through the motor windings is regulated by an adjustable, fixed-off-time PWM current-regulation
circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the supply
voltage, inductance of the winding, and the magnitude of the back EMF present. When the current hits the
current regulation threshold, the bridge enters a decay mode for a fixed 20 μs, period of time to decrease the
current. After the off time expires, the bridge is re-enabled, starting another PWM cycle.
Motor Current (A)
ITRIP
tBLANK
tDRIVE
tOFF
Figure 14. Current Chopping Waveform
The PWM regulation current is set by a comparator which monitors the voltage across the current sense
MOSFETs in parallel with the low-side power MOSFETs. The current sense MOSFETs are biased with a
reference current that is the output of a current-mode sine-weighted DAC whose full-scale reference current is
set by the current through the RREF pin. An external resistor is placed from the RREF pin to GND to set the
reference current. In addition, the TRQ pin can further scale the reference current.
Use Equation 1 to calculate the full-scale regulation current.
ARREF (kA:)
30 (kA:)
IFS (A)
u TRQ (%)
u TRQ (%)
RREF (k :)
RREF (k:)
(1)
For example, if a 30-kΩ resistor is connected to the RREF pin, the full-scale regulation current is 1 A (TRQ at
100%).
The TRQ pin is the input to a DAC used to scale the output current. Table 5 lists the current scalar value for
different inputs.
Table 5. Torque DAC Settings
TRQ
CURRENT SCALAR (TRQ)
0
100%
Z
75%
1
50%
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7.3.5 Controlling RREF With an MCU DAC
In some cases, the full-scale output current may need to be changed between many different values, depending
on motor speed and loading. The reference current of the RREF pin can be adjusted in the system by tying the
RREF resistor to a DAC output instead of GND.
In this mode of operation, as the DAC voltage increases, the reference current decreases and therefore the fullscale regulation current decreases as well. For proper operation, the output of the DAC should not rise above
VRREF.
DVDD
IREF
Controller
RREF
Analog
Input
RREF
RREF
DAC
Figure 15. Controlling RREF With a DAC Resource
Use Equation 2 to calculate the full-scale regulation current as controlled by a controller DAC.
IFS (A)
$RREF N$: u > 9RREF 9 ± 9DAC 9
VRREF (V) u RREF (k :)
@ u TRQ (%)
(2)
For example, if a 20-kΩ resistor is connected from the RREF pin to the DAC, and the DAC outputs 0.74 V, the
chopping current is 600 mA (TRQ at 100%)
The RREF pin can also be adjusted using a PWM signal and low-pass filter.
DVDD
IREF
Controller
RREF
PWM
R1
R2
RREF
RREF
Analog
Input
C1
Figure 16. Controlling RREF With a PWM Resource
7.3.5.1 Various Sources of Error
When performing a design error calculation, the different variables that contribute the most to the error must be
considered. To do so, first consider the typical values extracted from DRV8885 data sheet which are listed in
Table 6 with a 20-kΩ 1% resistor .
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Table 6. DRV8885 Data Sheet Values
Parameter
ARREF
Minimum
Typical
Maximum
28100
30000
31900
VRREF
1.18
1.232
1.28
RREF
19800
20000
20200
Using and knowing the desired output current, the VDAC value can be obtained. For example, the DRV8885EVM,
which has a 20-kΩ resistor for RREF, was selected to operate at a 1-A, 400mA, and 200 mA current. Table 7
lists the calculated VDAC values using typical ARREF and VRREF data sheet values
Table 7. VDAC Calculation
Parameter
IFS
ARREF
Minimum
Typical
1
0.4
Maximum
0.2
30 000
30 000
30 000
VRREF
1.232
1.232
1.232
RREF
20 000
20 000
20 000
VDAC
0.4107
0.9035
1.0677
Next, use Equation 3 and Equation 4 to calculate the worst case value for the minimum and maximum full scale
current, respectively.
ARREFmin (kA:) u [VRREFmin (V) VDACmax (V)]
u TRQ (%)
IFSmin (A)
VRREFmin (V) u RREFmax (k:)
(3)
IFSmax (A)
ARREFmax (kA:) u [VRREFmax (V) VDACmin (V)]
VRREFmax (V) u RREFmin (k:)
u TRQ (%)
(4)
These two equations show that error contributions come from VDAC, ARREF, VRREF, and RREF. The next sections
will show how these different error contributors, affect the overall IFS error and how they can be improved.
7.3.5.1.1 VRREF, ARREF, and RREF Error
To observe how VRREF, ARREF, and RREFVRREF affect the IFS error , Equation 3 and Equation 4 are used with the
data sheet values from earlier while VDAC voltage remains constant. Table 8, Table 9, and Table 10 list the
results at different current levels (1 A, 400 mA, and 200 mA, respectively).
Table 8. Worst Case Calculation—IFS Error at 1 A
Parameter
Minimum
Typical
Maximum
VDAC
0.4107
0.4107
0.4107
ARREF
28100
30000
31900
VRREF
1.18
1.232
1.28
RREF
19800
20000
20200
IFS (mA)
906.95
1000
1094.21
Error (%)
–9.30
9.42
Table 9. Worst Case Calculation—IFS Error at 400 mA
Parameter
Minimum
Typical
Maximum
VDAC
0.9035
0.9035
0.9035
ARREF
28100
30000
31900
VRREF
1.18
1.232
1.28
RREF
19800
20000
20200
IFS (mA)
326.00
400
473.93
Error (%)
–18.50
18.48
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Table 10. Worst Case Calculation—IFS Error at 200 mA
Parameter
Minimum
Typical
Maximum
VDAC
1.0677
1.0677
1.0677
ARREF
28100
30000
31900
VRREF
1.18
1.232
1.28
RREF
19800
20000
20200
IFS (mA)
135.35
200
267.18
Error (%)
–33.83
33.59
These tables show that as the IFS current level decreases, the overall error percentage increases due to
increasing offset error from the internal signal chain. It is worthy to clarify that the VRREF and ARREF values in
these tables are data sheet values which represent the characterization data variation across a wide range of
temperatures and voltages with additional margin. For information on how to further minimize this percentage of
error based on targeted characterization data for VRREF and ARREF, see Application-Specific Error Calculations .
7.3.5.1.2
VDAC Error
Using the same methodology along with Equation 3 and Equation 4, the VDAC error contribution to IFS can be
shown. This is done by removing the error from VRREF, ARREF, and RREF. The following examples show the VDAC
error value with a 3% and 10% variation.
Table 11. Worst Case Calculation—VDAC 3% and 10%,
IFS Error at 1 A
Parameter
Minimum
Typical
Maximum
VDAC
0.3983
0.4107
0.423
ARREF
30000
30000
30000
VRREF
1.232
1.232
1.232
RREF
20000
20000
20000
IFS (mA)
985.08
1000
1015.07
Error (%)
–1.50
3% ERROR
1.50
10% ERROR
VDAC
0.3696
0.4107
0.4517
ARREF
30000
30000
30000
VRREF
1.232
1.232
1.232
RREF
20000
20000
20000
IFS (mA)
950.08
1000
1050.07
Error (%)
–5.00
5.00
Table 12. Worst Case Calculation—VDAC 3% and 10%,
IFS Error at 400 mA
Parameter
Minimum
Typical
Maximum
VDAC
0.8764
0.9035
0.9306
ARREF
30000
30000
31 900
VRREF
1.232
1.232
1.232
RREF
20000
20000
20000
IFS (mA)
367.18
400
433.17
Error (%)
–8.25
3% ERROR
8.25
10% ERROR
20
VDAC
0.8131
0.9035
0.9938
ARREF
30000
30000
30000
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Table 12. Worst Case Calculation—VDAC 3% and 10%,
IFS Error at 400 mA (continued)
Parameter
Minimum
Typical
Maximum
1.232
1.232
1.232
RREF
20000
20000
20000
IFS (mA)
290.19
400
510.16
Error (%)
–27.48
VRREF
27.48
Table 13. Worst Case Calculation—VDAC 3% and 10%,
IFS Error at 200 mA
Parameter
Minimum
Typical
Maximum
VDAC
1.0357
1.0677
1.0998
ARREF
30000
30000
30000
VRREF
1.232
1.232
1.232
RREF
20000
20000
20000
IFS (mA)
161.22
200
239.20
Error (%)
–19.48
3% ERROR
19.48
10% ERROR
VDAC
0.9610
1.0677
1.1745
ARREF
30000
30000
30000
VRREF
1.232
1.232
1.232
RREF
20000
20000
20000
IFS (mA)
70.23
200
330.19
Error (%)
–64.92
64.92
These tables show that as the variation in VDAC increases, the error percentage increases. Also, for very low
currents, the error percentage increases greatly because of the VDAC proximity to the VRREF voltage.
7.3.5.2 Application-Specific Error Calculations
As described in the previous analysis, it is possible to obtain a tighter error calculations by using values for VRREF
and ARREF for the specific application use case. The data sheet parameters represent limits based on design and
characterization data across a wide range of temperatures and voltage with additional margin. For the following
example, the operational voltage is limited to VVM = 24 V, a common operating point for the DRV8884, DRV8885,
DRV8886, and DRV8886AT.
Considering this use case, Table 14 provides updated values for VRREF and ARREF.
Table 14. Values For DRV8885 VVM= 24-V
Parameter
Minimum
Typical
Maximum
ARREF
28800
30000
31200
VRREF
1.207
1.232
1.257
RREF
19800
20000
20200
Using values above and maintaining VDAC constant, the error percentage is reduced as shown in the following
tables.
Table 15. IFS Error at 1 A, VDAC Fixed and Application Values
Parameter
Minimum
Typical
Maximum
VDAC
0.4107
0.4107
0.4107
ARREF
28800
30000
31200
VRREF
1.207
1.232
1.257
RREF
19800
20000
20200
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Table 15. IFS Error at 1 A, VDAC Fixed and Application Values (continued)
Parameter
Minimum
Typical
Maximum
IFS (mA)
940.79
1000
1060.8
Error (%)
–5.93
6.07
Table 16. IFS Error at 400 mA, VDAC Fixed and Application Values
Parameter
Minimum
Typical
Maximum
VDAC
0.9035
0.9035
0.9035
ARREF
28800
30000
31200
VRREF
1.207
1.232
1.257
RREF
19800
20000
20200
IFS (mA)
358.54
400
443.18
Error (%)
–10.4
10.75
Table 17. IFS Error at 200 mA, VDAC Fixed and Application Values
Parameter
Minimum
Typical
Maximum
VDAC
1.0677
1.0677
1.0677
ARREF
28800
30000
31200
VRREF
1.207
1.232
1.257
RREF
19800
20000
20200
IFS (mA)
164.51
200
267.26
Error (%)
–17.83
18.51
By keeping VDAC value fixed or close to be fixed, yields much less error variation. The same calculation can be
made using a VDAC value with a ±3 % variation to compare error percentage difference as shown in the following
tables.
Table 18. VDAC 3%, VRREF and ARREF for 24-V
Application at 1 A
Parameter
Minimum
Typical
Maximum
VDAC
0.3983
0.4107
0.4230
ARREF
28800
30000
31200
VRREF
1.207
1.232
1.257
RREF
19800
20000
20200
IFS (mA)
926.09
1000
1076.39
Error (%)
–7.4
7.63
Table 19. VDAC 3%, VRREF and ARREF for 24-V
Application at 400 mA
Parameter
22
Minimum
Typical
Maximum
VDAC
0.8764
0.9035
0.9306
ARREF
28800
30000
31200
VRREF
1.207
1.232
1.257
RREF
19800
20000
20200
IFS (mA)
326.52
400
477.16
Error (%)
–18.41
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Table 20. VDAC 3%, VRREF and ARREF for 24-V
Application at 200 mA
Parameter
Minimum
Typical
Maximum
VDAC
1.0357
1.0677
1.0998
ARREF
28800
30000
31200
VRREF
1.207
1.232
1.257
RREF
19800
20000
20200
IFS (mA)
126.67
200
277.42
Error (%)
–36.73
38.56
Table 18, Table 19, and Table 20 show values closer to the typical values for both VDAC, ARREF, and VRREF. From
all these calculations, the error percentages for the 200 mA current are higher because at those very low values,
the minimum change greatly affects the full current equation. One method to improve the low-value current
accuracy is to use a combination of the MCU DAC and TRQ pin. This method can help improve the error by
reducing the need to use only the DAC voltage to achieve the low full-scale current. An example of this method
is to achieve 200 mA using the 400 mA DAC setting and the 50% TRQ setting.
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7.3.6 Decay Modes
The DRV8886 decay mode is selected by setting the quad-level DECAY pin to the voltage range listed in
Table 21. The decay mode setting can be modified during device operation.
Table 21. Decay Mode Settings
DECAY
INCREASING STEPS
DECREASING STEPS
100 mV
Can be tied to ground
Slow decay
Mixed decay: 30% fast
300 mV, 15 kΩ to GND
Mixed decay: 30% fast
Mixed decay: 30% fast
1 V, 45 kΩ to GND
Mixed decay: 60% fast
Mixed decay: 60% fast
2.9 V
Can be tied to DVDD
Slow decay
Slow decay
AOUT Current
Figure 17 defines increasing and decreasing current. For the slow-mixed decay mode, the decay mode is set as
slow during increasing current steps and mixed decay during decreasing current steps. In full step mode the
decreasing steps decay mode is always used. In noncircular 1/2-step mode the increasing step decay mode is
used after a level transition (0% to 100% and 0% to –100%). When the level transition is to a similar level (100%
to 100% and –100% to –100%), the decreasing step decay mode is used.
Increasing
Decreasing
Increasing
Decreasing
STEP Input
BOUT Current
AOUT Current
Decreasing
Increasing
Increasing
Decreasing
STEP Input
Figure 17. Definition of Increasing and Decreasing Steps
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7.3.6.1 Mode 1: Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
Increasing Phase Current (A)
ITRIP
tBLANK
tOFF
tBLANK
tOFF
tDRIVE
Decreasing Phase Current (A)
tDRIVE
tBLANK
tDRIVE
ITRIP
tBLANK
tDRIVE
tFAST
tBLANK
tOFF
tFAST
tDRIVE
tOFF
Figure 18. Slow-Mixed Decay Mode
Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of the tOFF time. In this
mode, mixed decay only occurs during decreasing current. Slow decay is used for increasing current.
This mode exhibits the same current ripple as slow decay for increasing current because for increasing current,
only slow decay is used. For decreasing current, the ripple is larger than slow decay, but smaller than fast decay.
On decreasing current steps, mixed decay will settle to the new ITRIP level faster than slow decay.
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7.3.6.2 Mode 2: Mixed Decay for Increasing and Decreasing Current
Increasing Phase Current (A)
ITRIP
tOFF
tBLANK
tOFF
tDRIVE
Decreasing Phase Current (A)
tDRIVE
tBLANK
tDRIVE
ITRIP
tBLANK
tDRIVE
tFAST
tBLANK
tOFF
tFAST
tDRIVE
tOFF
Figure 19. Mixed-Mixed Decay Mode
Mixed decay begins as fast decay for a time, followed by slow decay for the remainder of tOFF. In this mode,
mixed decay occurs for both increasing and decreasing current steps.
This mode exhibits ripple larger than slow decay, but smaller than fast decay. On decreasing current steps,
mixed decay settles to the new ITRIP level faster than slow decay.
In cases where current is held for a long time (no input in the STEP pin) or at very low stepping speeds, slow
decay may not properly regulate current because no back-EMF is present across the motor windings. In this
state, motor current can rise very quickly, and requires an excessively large off-time. Increasing or decreasing
mixed decay mode allows the current level to stay in regulation when no back-EMF is present across the motor
windings.
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7.3.6.3 Mode 3: Slow Decay for Increasing and Decreasing Current
Increasing Phase Current (A)
ITRIP
tBLANK
tOFF
tBLANK
tOFF
tDRIVE
Decreasing Phase Current (A)
tDRIVE
ITRIP
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
tOFF
tBLANK
tDRIVE
Figure 20. Slow-Slow Decay Mode
During slow decay, both of the low-side MOSFETs of the H-bridge are turned on, allowing the current to be
recirculated.
Slow decay exhibits the least current ripple of the decay modes for a given tOFF. However, on decreasing current
steps, slow decay takes a long time to settle to the new ITRIP level because the current decreases very slowly.
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7.3.7 Blanking Time
After the current is enabled in an H-bridge, the current sense comparator is ignored for a period of time (tBLANK)
before enabling the current-sense circuitry. The blanking time also sets the minimum drive time of the PWM.
Table 22 shows the blanking time based on the sine table index and the torque DAC setting. The torque DAC
index is not the same as one step as given in Table 3.
Table 22. Adaptive Blanking
Time over Torque DAC and
Microsteps
tblank = 1.5 µs
SINE INDEX
28
tblank = 1 µs
TORQUE DAC (TRQ)
100%
75%
50%
16
100%
75%
50%
15
98%
73.5
49%
14
96%
72%
48%
13
92%
69%
46%
12
88%
66%
44%
11
83%
62.3%
41.5%
10
77%
57.8%
38.5%
9
71%
53.3%
35.5%
8
63%
47.3%
31.5%
7
56%
42%
28%
6
47%
35.3
23.5%
5
38%
28.5
19%
4
29%
21.8%
14.5%
3
20%
15%
10%
2
10%
7.5%
5%
1
0%
0%
0%
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7.3.8 Charge Pump
A charge pump is integrated to supply a high-side N-channel MOSFET gate-drive voltage. The charge pump
requires a capacitor between the VM and VCP pins to act as the storage capacitor. Additionally a ceramic
capacitor is required between the CPH and CPL pins to act as the flying capacitor.
VM
VM
0.22 …F
VCP
CPH
0.022 …F
VM
Charge
Pump
Control
CPL
Figure 21. Charge Pump Block Diagram
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7.3.9 Linear Voltage Regulators
An linear voltage regulator is integrated into the DRV8886 device. The DVDD regulator can be used to provide a
reference voltage. For proper operation, bypass the DVDD pin to GND using a ceramic capacitor.
The DVDD output is nominally 3.3 V. When the DVDD LDO current load exceeds 1 mA, the output voltage drops
significantly.
The AVDD pin also requires a bypass capacitor to GND. This LDO is for DRV8886 internal use only.
VM
+
±
DVDD
3.3-V, 1-mA
0.47 …F
VM
+
±
AVDD
0.47 …F
Figure 22. Linear Voltage Regulator Block Diagram
If a digital input must be tied permanently high (that is, Mx, DECAY or TRQ), tying the input to the DVDD pin
instead of an external regulator is preferred. This method saves power when the VM pin is not applied or in sleep
mode: the DVDD regulator is disabled and current does not flow through the input pulldown resistors. For
reference, logic level inputs have a typical pulldown of 100 kΩ, and tri-level inputs have a typical pulldown of 60
kΩ.
7.3.10 Logic and Multi-Level Pin Diagrams
Figure 23 shows the input structure for the logic-level pins STEP, DIR, ENABLE, nSLEEP, and M1.
DVDD
100 kŸ
Figure 23. Logic-Level Input Pin Diagram
The tri-level logic pins, M0 and TRQ, have the structure shown in Figure 24.
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DVDD
DVDD
+
-
60 kŸ
DVDD
32 kŸ
+
-
Figure 24. Tri-Level Input Pin Diagram
The quad-level logic pin, DECAY, has the structure shown in Figure 25.
DVDD
+
DVDD
20 µA
t
DVDD
+
tDVDD
+
t
Figure 25. Quad-Level Input Pin Diagram
7.3.11 Protection Circuits
The DRV8886 device is fully protected against supply undervoltage, charge pump undervoltage, output
overcurrent, and device overtemperature events.
7.3.11.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the VM undervoltage-lockout threshold voltage (VUVLO), all
MOSFETs in the H-bridge are disabled, the charge pump is disabled, the logic is reset, and the nFAULT pin is
driven low. Operation resumes when the VM voltage rises above the VUVLO threshold. The nFAULT pin is
released after operation resumes. Decreasing the VM voltage below this undervoltage threshold resets the
indexer position.
7.3.11.2 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the charge-pump undervoltage-lockout threshold voltage
(VCPUV), all MOSFETs in the H-bridge are disabled and the nFAULT pin is driven low. Operation resumes when
the VCP voltage rises above the VCPUV threshold. The nFAULT pin is released after operation resumes.
7.3.11.3 Overcurrent Protection (OCP)
An analog current-limit circuit on each MOSFET limits the current through the MOSFET by removing the gate
drive. If this analog current limit persists for longer than tOCP, all MOSFETs in the H-bridge are disabled and the
nFAULT pinis driven low.
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The driver is re-enabled after the OCP retry period (tRETRY) has passed. The nFAULT pin becomes high again at
after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal
operation resumes and nFAULT remains deasserted.
7.3.11.4 Thermal Shutdown (TSD)
If the die temperature exceeds TTSD level, all MOSFETs in the H-bridge are disabled and the nFAULT pin is
driven low. When the die temperature falls below the TTSD level, operation automatically resumes. The nFAULT
pin is released after operation resumes.
Table 23. Fault Condition Summary
FAULT
CONDITION
ERROR
REPORT
H-BRIDGE
CHARGE
PUMP
INDEXER
DVDD
AVDD
RECOVERY
VM undervoltage
(UVLO)
VM < VUVLO
(max 7.8 V)
nFAULT
Disabled
Disabled
Disabled
Operating
Disabled
VM > VUVLO
(max 8 V)
VCP undervoltage
(CPUV)
VCP < VCPUV
(typ VM + 2 V)
nFAULT
Disabled
Operating
Operating
Operating
Operating
VCP > VCPUV
(typ VM + 2.7 V)
Overcurrent (OCP)
IOUT > IOCP
(min 3 A)
nFAULT
Disabled
Operating
Operating
Operating
Operating
tRETRY
Thermal shutdown
(TSD)
TJ > TTSD
(min 150°C)
nFAULT
Disabled
Operating
Operating
Operating
Operating
TJ < TTSD –
THYS
(THYS typ 20°C)
7.4 Device Functional Modes
The DRV8886 device is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is
disabled, the H-bridge MOSFETs are disabled Hi-Z, and the regulators are disabled.
NOTE
The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device is in
sleep mode. The DRV8886 device is brought out of sleep mode automatically if nSLEEP
is brought logic high.
The tWAKE time must elapse before the outputs change state after wake-up.
TI recommends to keep the STEP pin logic low when coming out of nSLEEP or when applying power.
If the ENABLE pin is brought logic low, the H-bridge outputs are disabled, but the internal logic is still active. A
rising edge on STEP advances the indexer, but the outputs do not change state until the ENABLE pin is
asserted.
Table 24 lists a summary of the functional modes.
Table 24. Functional Modes Summary
CONDITION
H-BRIDGE
CHARGE PUMP
INDEXER
DVDD
AVDD
Operating
8 V < VM < 40 V
nSLEEP pin = 1
ENABLE pin = 1
Operating
Operating
Operating
Operating
Operating
Disabled
8 V < VM < 40 V
nSLEEP pin = 1
ENABLE pin = 0
Disabled
Operating
Operating
Operating
Operating
Sleep mode
8 V < VM < 40
nSLEEP pin = 0
Disabled
Disabled
Disabled
Disabled
Disabled
VM undervoltage (UVLO)
Disabled
Disabled
Disabled
Operating
Disabled
VCP undervoltage (CPUV)
Disabled
Operating
Operating
Operating
Operating
Overcurrent (OCP)
Disabled
Operating
Operating
Operating
Operating
Thermal Shutdown (TSD)
Disabled
Operating
Operating
Operating
Operating
Fault encountered
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8886 device is used in bipolar stepper control.
8.2 Typical Application
The following design procedure can be used to configure the DRV8886 device.
DRV8886PWP
24
1
DECAY
CPL
TRQ
CPH
M1
VCP
M0
VM
23
2
22
3
21
4
20
0.22 F
VM
5
DIR
0.01 F
AOUT1
6
7
+
STEP
±
19
PGND
18
ENABLE
AOUT2
nSLEEP
BOUT2
17
Step
Motor
8
16
+
±
9
RREF
15
30 k
0.022 F
PGND
10
nFAULT
BOUT1
14
11
DVDD
VM
AVDD
GND
13
VM
12
0.47 F
0.01 F
+ 100 F
0.47 F
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Figure 26. Typical Application Schematic
8.2.1 Design Requirements
Table 25 lists the design input parameters for system design.
Table 25. Design Parameters
DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
Supply voltage
VM
24 V
Motor winding resistance
RL
2.6 Ω/phase
Motor winding inductance
LL
1.4 mH/phase
θstep
1.8°/step
Motor full step angle
Target microstepping level
Target motor speed
Target full-scale current
nm
1/8 step
v
120 rpm
IFS
2A
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8.2.2 Detailed Design Procedure
8.2.2.1 Stepper Motor Speed
The first step in configuring the DRV8886 device requires the desired motor speed and microstepping level. If the
target application requires a constant speed, then a square wave with frequency ƒstep must be applied to the
STEP pin.
If the target motor speed is too high, the motor does not spin. Make sure that the motor can support the target
speed.
Use Equation 5 to calculate ƒstep for a desired motor speed (v), microstepping level (nm), and motor full step
angle (θstep).
v (rpm) u 360 (q / rot)
¦step VWHSV V
Tstep (q / step) u nm (steps / microstep) u 60 (s / min)
(5)
The value of θstep can be found in the stepper motor data sheet, or written on the motor.
For the DRV8886 device, the microstepping level is set by the Mx pins and can be any of the settings listed in
Table 26. Higher microstepping results in smoother motor motion and less audible noise, but increases switching
losses and requires a higher ƒstep to achieve the same motor speed.
Table 26. Microstepping Indexer Settings
M1
M0
STEP MODE
0
0
Full step (2-phase excitation) with 71% current
0
1
1/16 step
1
0
1/2 step
1
1
1/4 step
0
Z
1/8 step
1
Z
Non-circular 1/2 step
For example, the motor is 1.8°/step for a target of 120 rpm at 1/8 microstep mode.
120 rpm u 360q / rot
¦step VWHSV V
N+]
1.8q / step u 1/ 8 steps / microstep u 60 s / min
(6)
8.2.2.2 Current Regulation
In a stepper motor, the full-scale current (IFS) is the maximum current driven through either winding. This quantity
depends on the RREF resistor and the TRQ setting. During stepping, IFS defines the current chopping threshold
(ITRIP) for the maximum current step.
ARREF (kA:) 30 (kA:) u TRQ%
IFS (A)
RREF (k:)
RREF (k:)
(7)
NOTE
The IFS current must also follow Equation 8 to avoid saturating the motor. VM is the motor
supply voltage, and RL is the motor winding resistance.
IFS (A)
RL (:)
VM (V)
2 u RDS(ON) (:)
(8)
8.2.2.3 Decay Modes
The DRV8886 device supports three different decay modes: slow decay, slow-mixed decay, and all mixed decay.
The current through the motor windings is regulated using an adjustable fixed-time-off scheme which means that
after any drive phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8886
places the winding in one of the three decay modes for tOFF. After tOFF, a new drive phase starts.
The blanking time, tBLANK, defines the minimum drive time for the PWM current chopping. ITRIP is ignored during
tBLANK, so the winding current may overshoot the trip level.
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8.2.3 Application Curves
Figure 27. 1/8 Microstepping With Slow-Slow Decay;
Loss of Current Regulation on Falling Steps
Figure 28. 1/8 Microstepping With Slow-Mixed Decay
Figure 29. 1/8 Microstepping With Mixed30-Mixed30 Decay
Figure 30. 1/8 Microstepping With Mixed60-Mixed60 Decay
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9 Power Supply Recommendations
The DRV8886 device is designed to operate from an input voltage supply (VM) range from 8 V to 37 V. A 0.01µF ceramic capacitor rated for VM must be placed at each VM pin as close to the DRV8886 device as possible.
In addition, a bulk capacitor must be included on VM.
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The power supply’s capacitance and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed DC, brushless DC, stepper)
• The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
±
+
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
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Figure 31. Example Setup of Motor Drive System With External Power Supply
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10 Layout
10.1 Layout Guidelines
The VM pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value
of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace or
ground plane connection to the device GND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an
electrolytic capacitor.
A low-ESR ceramic capacitor must be placed between the CPL and CPH pins. A value of 0.022 µF rated for VM
is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed between the VM and VCP pins. A value of 0.22 µF rated for 16 V
is recommended. Place this component as close to the pins as possible.
Bypass the AVDD and DVDD pins to ground with a low-ESR ceramic capacitor rated 6.3 V. Place this bypass
capacitor as close to the pin as possible.
10.2 Layout Example
+
CPL
DECAY
CPH
TRQ
VCP
M1
VM
M0
AOUT1
DIR
PGND
STEP
AOUT2
ENABLE
BOUT2
nSLEEP
PGND
RREF
BOUT1
nFAULT
VM
DVDD
GND
AVDD
0.47 µF
0.01 µF
0.47 µF
0.22 µF
0.022 µF
0.01 µF
Figure 32. Layout Recommendation
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Product Folder Links: DRV8886
37
DRV8886
SLVSDA4C – JANUARY 2017 – REVISED MARCH 2020
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Current Recirculation and Decay Modes application report
• Texas Instruments, DRV8886 Evaluation Module User's Guide
• Texas Instruments, Full-Scale Current Adjustment Using a Digital-to-Analog Converter (DAC) application
report
• Texas Instruments, Industrial Motor Drive Solution Guide
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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Product Folder Links: DRV8886
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
DRV8886PWP
ACTIVE
HTSSOP
PWP
24
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8886
Samples
DRV8886PWPR
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8886
Samples
DRV8886RHRR
ACTIVE
WQFN
RHR
28
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
DRV8886
Samples
DRV8886RHRT
ACTIVE
WQFN
RHR
28
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
DRV8886
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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