DS125BR401SQE/NOPB

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents DS125BR401 SNLS419D – JULY 2012 – REVISED MAY 2015 DS125BR401 Low-Power, 12.5-Gbps, 4-Lane Repeater With Input Equalization and Output De-Emphasis 1 Features 3 Description • The DS125BR401 device is an extremely low-power high-performance multiprotocol repeater and redriver designed to support four lanes of PCIe Gen-3/2/1, 10G-KR, and other high-speed interface serial protocols up to 12.5 Gbps. The continuous time linear equalizer (CTLE) of the receiver provides a boost of up to 30 dB at 6.25 GHz (12.5 Gbps) in each of its eight channels and can open an input eye that is completely closed due to intersymbol interference (ISI) induced by interconnect medium such as backplane traces of 30 inches or more or copper cables of 8 meters or more, hence enabling host controllers to ensure an error-free end-to-end link. The transmitter provides a de-emphasis boost of up to –12 dB and output voltage amplitude control from 700 mV to 1300 mV to allow maximum flexibility in the physical placement within the interconnect channel. 1 • • • • • • • • • Comprehensive Family, Proven System Interoperability – DS125BR111: 1-Lane Repeater – DS125BR401: 4-Lane Repeater – DS125BR800: 8-Channel Repeater – DS125MB203: 2-Port 2:1/1:2 Mux/Switch – DS125DF410: 4-Channel Unidirectional Retimer With CDR Low 65-mW/Channel (Typical) Power Consumption, With Option to Power Down Unused Channels Nonlimiting Output for PCIe and 10G-KR Link Training Support Advanced Signal Conditioning Features – Receive Equalization up to 30 dB at 6.25 GHz – Transmit De-Emphasis up to –12 dB – Transmit Output Voltage Control: 700 mV to 1300 mV Programmable Through Pin Selection, EEPROM, or SMBus Interface Single Supply Voltage: 2.5 V or 3.3 V (Selectable) −40°C to 85°C Operating Temperature Range 5-kV HBM ESD Rating Flow-Thru Pinout in 10-mm × 5.5-mm 54-Pin Leadless WQFN Package Supported Protocols – sRIO, Infiniband, Interlaken, CPRI, OBSAI – Other Proprietary Interface up to 12.5 Gbps Device Information(1) PART NUMBER DS125BR401 PACKAGE WQFN (54) • • SAS/SATA (up to 6 Gbps), Fibre Channel (up to 10 GFC) PCIe Gen-3/2/1, 10G-KR, 10GbE, XAUI, RXAUI 10.00 mm × 5.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Typical Application 4 TX ASIC or PCIe EP Connector 4 RX DS125BR401 4 2 Applications BODY SIZE (NOM) RX System Board Root Complex Connector 4 TX ard Bo ce Tra DS125BR401 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS125BR401 SNLS419D – JULY 2012 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Typical Application ................................................ Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 3 5 8.1 8.2 8.3 8.4 8.5 8.6 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 6 Electrical Characteristics — Serial Management Bus Interface .................................................................... 9 8.7 Typical Characteristics ............................................ 11 9 Detailed Description ............................................ 12 9.1 Overview ................................................................. 12 9.2 Functional Block Diagram ....................................... 12 9.3 Feature Description................................................. 12 9.4 Device Functional Modes........................................ 13 9.5 Programming........................................................... 13 9.6 Register Maps ......................................................... 25 10 Application and Implementation........................ 39 10.1 Application Information.......................................... 39 10.2 Typical Application ............................................... 39 11 Power Supply Recommendations ..................... 43 11.1 3.3-V or 2.5-V Supply Mode Operation................. 43 11.2 Power Supply Bypassing ...................................... 43 12 Layout................................................................... 44 12.1 Layout Guidelines ................................................. 44 12.2 Layout Example .................................................... 44 13 Device and Documentation Support ................. 45 13.1 13.2 13.3 13.4 13.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 45 45 45 45 45 14 Mechanical, Packaging, and Orderable Information ........................................................... 45 5 Revision History Changes from Revision C (April 2013) to Revision D • 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 DS125BR401 www.ti.com SNLS419D – JULY 2012 – REVISED MAY 2015 6 Description (continued) When operating in 10G-KR, and PCIe Gen-3 mode, the DS125BR401 allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This transparency to the link training protocol can extend the maximum channel loss with minimum latency. With a low power consumption of 65 mW/channel (typical) and the option to turn off unused channels, the DS125BR401 enables energy efficient system design. A single supply of 3.3 V or 2.5 V is required to power the device. The programmable settings can be applied easily through pins, software (SMBus or I2C), or loaded through an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver. 7 Pin Configuration and Functions DEMA0/SDA ENSMB EQB1/AD2 EQB0/AD3 47 46 DEMA1/SCL 50 48 VDD 49 PWDN 51 DEMB0/AD1 53 52 DEMB1/AD0 54 NJY Package 54-Pin WQFN Top View SMBUS AND CONTROL OUTB_0+ 1 45 INB_0+ OUTB_0- 2 44 INB_0- OUTB_1+ 3 43 INB_1+ OUTB_1- 4 42 INB_1- OUTB_2+ 5 41 VDD OUTB_2- 6 40 INB_2+ OUTB_3+ 7 39 INB_2- OUTB_3- 8 38 INB_3+ VDD 9 37 INB_3- DAP = GND INA_0+ 10 36 VDD INA_0- 11 35 OUTA_0+ INA_1+ 12 34 OUTA_0- INA_1- 13 33 OUTA_1+ VDD 14 32 OUTA_1- INA_2+ 15 31 OUTA_2+ 23 24 25 26 27 VIN VDD_SEL SD_TH/READ_EN ALL_DONE EQA1 LPBK OUTA_3- 22 28 RXDET 18 21 INA_3- 20 OUTA_2OUTA_3+ EQA0 30 29 MODE 16 17 19 INA_2INA_3+ Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 3 DS125BR401 SNLS419D – JULY 2012 – REVISED MAY 2015 www.ti.com Pin Functions (1) PIN NAME I/O, TYPE NUMBER DESCRIPTION DIFFERENTIAL HIGH-SPEED I/Os INB_0+, INB_0-, INB_1+, INB_1-, INB_2+, INB_2-, INB_3+, INB_3- 45, 44, 43, 42 40, 39, 38, 37 I Inverting and noninverting CML differential inputs to the equalizer. Onchip 50-Ω termination resistor connects INB_n+ to VDD and INB_n- to VDD when enabled. AC coupling required on high-speed I/O OUTB_0+, OUTB_1+, OUTB_2+, OUTB_3+, 1, 2, 3, 4 5, 6, 7, 8 O Inverting and noninverting 50-Ω driver outputs with de-emphasis. Compatible with AC coupled CML inputs. AC coupling required on high-speed I/O INA_0+, INA_0-, INA_1+, INA_1-, INA_2+, INA_2-, INA_3+, INA_3- 10, 11, 12, 13 15, 16, 17, 18 I Inverting and noninverting CML differential inputs to the equalizer. Onchip 50-Ω termination resistor connects INA_n+ to VDD and INA_n- to VDD when enabled. AC coupling required on high-speed I/O OUTA_0+, OUTA_1+, OUTA_2+, OUTA_3+, 35, 34, 33, 32 31, 30, 29, 28 O Inverting and noninverting 50-Ω driver outputs with de-emphasis. Compatible with AC coupled CML inputs. AC coupling required on high-speed I/O I, 4-LEVEL, LVCMOS System Management Bus (SMBus) Enable pin Tie 1 kΩ to VDD = Register Access SMBus Slave mode FLOAT = Read External EEPROM (Master SMBUS Mode) Tie 1 kΩ to GND = Pin Mode OUTB_0-, OUTB_1-, OUTB_2-, OUTB_3- OUTA_0-, OUTA_1-, OUTA_2-, OUTA_3- CONTROL PINS — SHARED (LVCMOS) ENSMB 48 ENSMB = 1 (SMBUS MODE) SCL 50 I, 2-LEVEL, LVCMOS, O, OPEN Drain ENSMB Master or Slave mode SMBUS clock input pin is enabled (slave mode). Clock output when loading EEPROM configuration (master mode). SDA 49 I, 2-LEVEL, LVCMOS, O, OPEN Drain ENSMB Master or Slave mode The SMBus bidirectional SDA pin is enabled. Data input or open-drain (pulldown only) output. AD0-AD3 54, 53, 47, 46 I, 4-LEVEL, LVCMOS ENSMB Master or Slave mode SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus slave address inputs. There are 16 addresses supported by these pins. Pins must be tied LOW or HIGH when used to define the device SMBus address. READ_EN 26 I, 2-LEVEL, LVCMOS When using an External EEPROM, a transition from high to low starts the load from the external EEPROM EQA0, EQA1 EQB0, EQB1 20, 19 46, 47 I, 4-LEVEL, LVCMOS EQA[1:0] and EQB[1:0] control the level of equalization of the A/B sides as shown in . The pins are active only when ENSMB is deasserted (low). Each of the 4 A/B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane. The EQB[1:0] pins are converted to SMBUS AD2, AD3 inputs. See Table 2. DEMA0, DEMA1 DEMB0, DEMB1 49, 50 53, 54 I, 4-LEVEL, LVCMOS DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the A/B sides as shown in . The pins are only active when ENSMB is deasserted (low). Each of the 4 A/B channels have the same level unless controlled by the SMBus control registers. When ENSMB goes high the SMBus registers provide independent control of each lane. The DEMA[1:0] pins are converted to SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1 inputs. See Table 3. ENSMB = 0 (PIN MODE) (1) 4 LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured. Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%. For 3.3-V mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V. For 2.5-V mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 DS125BR401 www.ti.com SNLS419D – JULY 2012 – REVISED MAY 2015 Pin Functions(1) (continued) PIN NAME I/O, TYPE NUMBER DESCRIPTION MODE 21 I, 4-LEVEL, LVCMOS MODE control pin selects operating modes. Tie 1 kΩ to GND = PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps) FLOAT = AUTO Rate Select (for PCIe) Tie 20 kΩ to GND = PCIe Gen-3 without De-emphasis Tie 1 kΩ to VDD = 10G-KR See Table 6 SD_TH 26 I, 4-LEVEL, LVCMOS Controls the internal Signal Detect Threshold. For datarates above 8 Gbps the Signal Detect function should be disabled to avoid potential for intermittent data loss. See Table 5. CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS) RXDET 22 I, 4-LEVEL, LVCMOS The RXDET pin controls the receiver detect function. Depending on the input level, a 50 Ω or >50 kΩ termination to the power rail is enabled. See Table 4. LPBK 23 I, 4-LEVEL, LVCMOS Controls the loopback function Tie 1 kΩ to GND = Root Complex Loopback (INA_n to OUTB_n) Float = Normal Operation Tie 1 kΩ to VDD = End-point Loopback (INB_n to OUTA_n) VDD_SEL 25 I, LVCMOS Controls the internal regulator Float = 2.5-V mode Tie GND = 3.3-V mode PWDN 52 I, LVCMOS Tie High = Low power - power down Tie GND = Normal Operation See Table 4. ALL_DONE 27 O, LVCMOS Valid Register Load Status Output HIGH = External EEPROM load failed LOW = External EEPROM load passed VIN 24 Power In 3.3-V mode, feed 3.3 V to VIN In 2.5-V mode, leave floating. VDD 9, 14,36, 41, 51 Power Power supply pins CML/analog 2.5-V mode, connect to 2.5 V 3.3-V mode, connect 0.1-µF capacitor to each VDD pin GND DAP Power Ground pad (DAP - die attach pad). See Power Supply Recommendations for proper power supply decoupling. POWER 8 Specifications 8.1 Absolute Maximum Ratings (1) MIN MAX UNIT Supply Voltage (VDD - 2.5 V) –0.5 2.75 V Supply Voltage (VIN - 3.3 V) –0.5 4 V LVCMOS Input/Output Voltage –0.5 4 V CML Input Voltage –0.5 (VDD + 0.5) V CML Input Current –30 30 mA Junction Temperature 125 °C Lead Temperature Range Soldering (4 sec.) (2) 260 °C 125 °C Storage Temperature, Tstg (1) (2) –40 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For soldering specifications: See application note SNOA549. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 5 DS125BR401 SNLS419D – JULY 2012 – REVISED MAY 2015 www.ti.com 8.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±5000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 Machine model (MM), JESD22-A115-A ±150 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute maximum numbers are specified for a junction temperature range of –40°C to 125°C. Models are validated to maximum operating voltages only. MIN NOM MAX UNIT Supply Voltage (2.5-V mode) 2.375 2.5 2.625 V Supply Voltage (3.3-V mode) 3.0 3.3 3.6 V Ambient Temperature –40 25 85 °C 3.6 V 100 mVp-p SMBus (SDA, SCL) Supply Noise up to 50 MHz (1) (1) Allowed supply noise (mVp-p sine wave) under typical conditions. 8.4 Thermal Information DS125BR401 THERMAL METRIC (1) NJY [WQFN] UNIT 54 PINS RθJA Junction-to-ambient thermal resistance 26.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 10.8 °C/W RθJB Junction-to-board thermal resistance 4.4 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 4.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 8.5 Electrical Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER PD Power Dissipation VDD = 2.5-V supply, EQ Enabled, VOD = 1 Vp-p, RXDET = 1, PWDN = 0 500 700 VIN = 3.3-V supply, EQ Enabled, VOD = 1 Vp-p, RXDET = 1, PWDN = 0 660 900 mW LVCMOS / LVTTL DC SPECIFICATIONS VIH25 High Level Input Voltage 2.5-V Mode 2.0 VDD V VIH33 High Level Input Voltage 3.3-V Mode 2.0 VIN V VIL Low Level Input Voltage 0 0.8 V VOH High Level Output Voltage (ALL_DONE pin) Ioh = –4 mA VOL Low Level Output Voltage (ALL_DONE pin) Iol = 4 mA IIH Input High Current (PWDN pin) Input High Current with internal resistors (4-level input pin) 6 VIN = 3.6 V, LVCMOS = 3.6 V Submit Documentation Feedback 2.0 V 0.4 –15 15 20 150 V µA Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 DS125BR401 www.ti.com SNLS419D – JULY 2012 – REVISED MAY 2015 Electrical Characteristics (continued) PARAMETER IIL TEST CONDITIONS Input Low Current (PWDN pin) VIN = 3.6 V, LVCMOS = 0 V Input Low Current with internal resistors (4-level input pin) MIN TYP MAX –15 15 –160 –40 UNIT µA CML RECEIVER INPUTS (IN_N+, IN_N-) RLRX-DIFF 0.05 - 7.5 GHz RX Differential return loss –15 7.5 - 15 GHz dB –5 RLRX-CM RX Common mode return loss 0.05 - 5 GHz ZRX-DC RX DC common mode impedance Tested at VDD = 2.5 V 40 –10 50 60 dB Ω ZRX-DIFF-DC RX DC differential mode impedance Tested at VDD = 2.5 V 80 100 120 Ω VRX-DIFF-DC Differential RX peak-to-peak voltage (VID) Tested at pins 1.2 V VRX-SIGNAL-DET- Signal detect assert level for active data signal DIFF-PP SD_TH = F (float), 0101 pattern at 8 Gbps 180 mVp-p VRX-IDLE-DET- SD_TH = F (float), 0101 pattern at 8 Gbps 110 mVp-p DIFF-PP Signal detect deassert level for electrical idle HIGH SPEED OUTPUTS VTX-DIFF-PP Output Voltage Differential Swing Differential measurement with Out_n+ and OUT_n-, terminated by 50 Ω to GND, AC-Coupled, VID = 1 Vp-p, DEM0 = 1, DEM1 = 0 (1) TX de-emphasis ratio VOD = 1 Vp-p, DEM0 = 0, DEM1 = R, PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps) –3.5 dB TX de-emphasis ratio VOD = 1 Vp-p, DEM0 = R, DEM1 = R, PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps) –6 dB VTX-DERATIO_3.5 VTX-DE-RATIO_6 0.8 1 1.2 Vp-p TTX-DJ Deterministic Jitter VID = 800 mV, PRBS15 pattern, 8.0 Gbps, VOD = 1 V, EQ = 0x00, DE = 0 dB, (no input or output trace loss) 0.05 UIpp TTX-RJ Random Jitter VID = 800 mV, 0101 pattern, 8.0 Gbps, VOD = 1 V, EQ = 0x00, DE = 0 dB, (no input or output trace loss) 0.3 ps RMS TTX-RISE-FALL Transmitter rise/fall time 20% to 80% of differential output voltage TRF-MISMATCH Transmitter rise/fall mismatch 20% to 80% of differential output voltage 0.01 0.05 - 7.5 GHz –15 RLTX-DIFF TX Differential return loss RLTX-CM TX Common mode return loss ZTX-DIFF-DC DC differential TX impedance 35 –10 dB 100 Ω ITX-SHORT Transmitter short circuit current limit Total current the transmitter can supply when shorted to VDD or GND DELTA TTX-IDLE-DATA (1) dB 0.05 - 5 GHz TX AC common mode voltage VTX-CM-DC-LINE- UI –5 VOD = 1 Vp-p, DEM0 = 1, DEM1 = 0 ACTIVE-IDLEDELTA ps 0.1 7.5 - 15 GHz VTX-CM-AC-PP VTX-CM-DC- 45 100 20 mVp-p mA Absolute delta of DC common mode voltage during L0 and electrical idle 100 mV Absolute delta of DC common mode voltage between TX+ and TX- 25 mV Max time to transition to valid differential signal after idle VID = 1 Vp-p, 8 Gbps 3.5 ns In PCIe Gen-3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output VOD level set by DEMA/B[1:0] in this MODE is dependent on the VID level and the frequency content. The DS125BR401 repeater is designed to be nonlimiting in this MODE, so the TX-FIR (de-emphasis) is passed to the RX to support the handshake negotiation link training. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 7 DS125BR401 SNLS419D – JULY 2012 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TTX-DATA-IDLE Max time to transition to idle after differential signal VID = 1 Vp-p, 8 Gbps 6.2 ns TPDEQ Differential propagation delay EQ = 00 (2) 200 ps TLSK Lane-to-lane skew T = 25°C, VDD = 2.5 V 25 ps TPPSK Part-to-part propagation delay skew T = 25°C, VDD = 2.5 V 40 ps Residual deterministic jitter at 12 Gbps 30” 5mils FR4, VID = 0.6 Vp-p, PRBS15, EQ = 0x07, DEM = 0 dB 0.18 UIpp Residual deterministic jitter at 8 Gbps 30” 5mils FR4, VID = 0.6 Vp-p, PRBS15, EQ = 0x07, DEM = 0 dB 0.11 UIpp Residual deterministic jitter at 5 Gbps 30” 5mils FR4, VID = 0.6 Vp-p, PRBS15, EQ = 0x07, DEM = 0 dB 0.07 UIpp Residual deterministic jitter at 12 Gbps 5-meter 30-AWG cable, VID = 0.6 Vp-p, PRBS15, EQ = 0x07, DEM = 0 dB 0.25 UIpp Residual deterministic jitter at 12 Gbps 8-meter 30-AWG cable, VID = 0.6 Vp-p, PRBS15, EQ = 0x0F, DEM = 0 dB 0.33 UIpp 0.1 UIpp EQUALIZATION DJE1 DJE2 DJE3 DJE4 DJE5 DE-EMPHASIS — PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps) DJD1 Residual deterministic jitter at 12 Gbps (2) 8 Input Channel: 20" 5mils FR4, Output Channel: 10” 5mils FR4, VID = 0.6 Vp-p, PRBS15, EQ = 0x03, VOD = 1 Vp-p, DEM = −3.5 dB Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the longest propagation delays. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 DS125BR401 www.ti.com SNLS419D – JULY 2012 – REVISED MAY 2015 8.6 Electrical Characteristics — Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIAL BUS INTERFACE DC SPECIFICATIONS VIL Data, Clock Input Low Voltage VIH Data, Clock Input High Voltage IPULLUP Current Through Pullup Resistor or Current Source VDD Nominal Bus Voltage ILEAK-Bus Input Leakage Per Bus Segment ILEAK-Pin Input Leakage Per Device Pin CI Capacitance for SDA and SCL See (1) (2) RTERM External Termination Resistance pull to VDD = 2.5 V ± 5% OR 3.3 V ± 10% Pullup VDD = 3.3 V (1) (2) (3) 2000 Pullup VDD = 2.5 V (1) (2) (3) 1000 2.1 High Power Specification See (1) 0.8 V 3.6 V 4 mA 2.375 3.6 V –200 200 µA –15 µA 10 pF Ω SERIAL BUS INTERFACE TIMING SPECIFICATIONS FSMB Bus Operating Frequency ENSMB = VDD (Slave Mode) ENSMB = FLOAT (Master Mode) TBUF Bus Free Time Between Stop and Start Condition THD:STA Hold time after (Repeated) Start Condition. After this period, the first clock is generated. 400 280 400 520 kHz 1.3 µs 0.6 µs At IPULLUP, Max TSU:STA Repeated Start Condition Setup Time 0.6 µs TSU:STO Stop Condition Setup Time 0.6 µs THD:DAT Data Hold Time 0 ns TSU:DAT Data Setup Time 100 ns TLOW Clock Low Period 1.3 µs (4) THIGH Clock High Period See 50 µs tF Clock/Data Fall Time See (4) 300 ns tR Clock/Data Rise Time See (4) 300 ns tPOR Time in which a device must be operational after power-on reset See (4) (5) 500 ms (1) (2) (3) (4) (5) 0.6 Recommended value. Recommended maximum capacitance load per bus segment is 400 pF. Maximum termination voltage should be identical to the device supply voltage. Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details. Ensured by Design. Parameter not tested in production. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 9 DS125BR401 SNLS419D – JULY 2012 – REVISED MAY 2015 www.ti.com 80% 80% VOD = [Out+ - Out-] 0V 20% 20% tRISE tFALL Figure 1. CML Output and Rise and FALL Transition Time IN 0V tPLHD OUT tPHLD 0V Figure 2. Propagation Delay Timing Diagram + IN 0V DATA tIDLE-DATA tDATA-IDLE + OUT 0V DATA IDLE IDLE Figure 3. Transmit IDLE-DATA and DATA-IDLE Response Time tLOW tR tHIGH SCL tHD:STA tBUF tHD:DAT tF tSU:STA tSU:DAT tSU:STO SDA SP ST SP ST Figure 4. SMBus Timing Parameters 10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 DS125BR401 www.ti.com SNLS419D – JULY 2012 – REVISED MAY 2015 8.7 Typical Characteristics 1021 640.0 VDD = 2.625V 620.0 T = 25°C VDD = 2.5V 600.0 1019 VDD = 2.375V 560.0 VOD (mVp-p) PD (mW) 580.0 540.0 520.0 500.0 1016 1013 480.0 1010 T = 25oC 460.0 440.0 1007 2.375 420.0 0.8 0.9 1 1.1 1.2 1.3 VOD (Vp-p) 2.5 2.625 VDD (V) Figure 5. Power Dissipation (PD) vs Output Differential Voltage (VOD) Figure 6. Output Differential Voltage (VOD = 1 Vp-p) vs Supply Voltage (VDD) 1020 VDD = 2.5 V VOD (mVp-p) 1018 1016 1014 1012 - 40 -15 10 35 60 85 TEMPERATURE (°C) Figure 7. Output Differential Voltage (VOD = 1 Vp-p) vs Temperature Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 11 DS125BR401 SNLS419D – JULY 2012 – REVISED MAY 2015 www.ti.com 9 Detailed Description 9.1 Overview The DS125BR401 device compensates for lossy printed-circuit-board (PCB) backplanes and balanced cables. The DS125BR401 compensates for lossy FR-4 PCB backplanes and balanced cables. The DS125BR401 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode (ENSMB = float) to load register informations from external EEPROM; refer to SMBUS Master Mode for additional information. 9.2 Functional Block Diagram VDD Auto/Manual RXDET INx_n+ RATE DET VOD/DeEMPHASIS CONTROL DEMA/B SMBus EQ OUTBUF INx_n- OUTx_n+ OUTx_n- TX Idle Enable IDLE DET EQA/B SMBus SMBus Figure 8. Block Diagram - Detail View Of Channel (1 Of 8) 9.3 Feature Description The 4-level input pins use a resistor divider to help settings when ENSMB=0. There is an internal 30-kΩ These resistors, together with the external resistor Using the 1-kΩ pullup, 1-kΩ pulldown, no connect, each of the four input states. set the 4 valid levels and provide a wider range of control pullup and a 60-kΩ pulldown connected to the package pin. connection combine to achieve the desired voltage level. and 20-kΩ pulldown provide the optimal voltage levels for Table 1. 4–Level Control Pin Settings LEVEL SETTING 3.3-V MODE 2.5-V MODE 0 Tie 1 kΩ to GND 0.10 V 0.08 V R Tie 20 kΩ to GND 1/3 × VIN 1/3 × VDD Float Float (leave pin open) 2/3 × VIN 2/3 × VDD 1 Tie 1 kΩ to VIN or VDD VIN – 0.05 V VDD – 0.04 V 9.3.1 Typical 4-Level Input Thresholds • Level 1 - 2 = 0.2 × VIN or VDD • Level 2 - 3 = 0.5 × VIN or VDD • Level 3 - 4 = 0.8 × VIN or VDD To minimize the start-up current associated with the integrated 2.5-V regulator, TI recommends using the 1-kΩ pullup and pulldown resistors. If several 4-level inputs require the same setting, it is possible to combine two or more 1-kΩ resistors into a single lower value resistor. As an example; combining two inputs with a single 500-Ω resistor is a good way to save board space. 12 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 DS125BR401 www.ti.com SNLS419D – JULY 2012 – REVISED MAY 2015 9.4 Device Functional Modes 9.4.1 Pin Control Mode When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically adjusted per Table 3. For PCIe applications, the RXDET pins provides automatic and manual control for input termination (50 Ω or >50 kΩ). MODE setting is also pin controllable with pin selections (PCIe Gen-1, PCIe Gen-2, auto detect, and PCIe Gen-3). The receiver electrical idle detect threshold is also adjustable through the SD_TH pin. 9.4.2 SMBUS Mode When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (MODE, RXDET and SD_TH) remain active unless their respective registers are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low (pin mode). On power up and when ENSMB is driven low all registers are reset to their default state. If PWDN is asserted while ENSMB is high, the registers retain their current state. Equalization settings accessible through the pin controls were chosen to meet the needs of most high speed applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the SMBus registers. Each input has a total of 256 possible equalization settings. System Management Bus (SMBus) and Configuration Registers show the 16 setting when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-emphasis levels are set by registers. 9.5 Programming 9.5.1 PCIe Signal Integrity When using the DS125BR401 in PCIe Gen-3 systems, there are specific signal integrity settings to ensure signal integrity margin. The settings were optimized by extensive testing. Contact your field representative for more information regarding the testing completed to achieve these settings. For tuning the in the downstream direction (from CPU to EP). • EQ: use the guidelines outlined in Table 2. • De-Emphasis: use the guidelines outlined in Table 3. • VOD: use the guidelines outlined in Table 3. For tuning in the upstream direction (from EP to CPU). • EQ: use the guidelines outlined in Table 2. • De-Emphasis: – For trace lengths < 15 in set to –3.5 dB – For trace lengths > 15 in set to –6 dB • VOD: set to 900 mV Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 13 DS125BR401 SNLS419D – JULY 2012 – REVISED MAY 2015 www.ti.com Programming (continued) Table 2. Equalizer Settings LEVEL EQA1 EQB1 EQA0 EQB EQ – 8 bits [7:0] dB at 1.5 GHz dB at 2.5 GHz dB at 4 GHz dB at 6 GHz SUGGESTED USE (1) 1 0 0 0000 0000 = 0x00 2.5 3.5 3.8 3.1 FR4 < 5-inch trace 2 0 R 0000 0001 = 0x01 3.8 5.4 6.7 6.7 FR4 5- to 10-inch trace 3 0 Float 0000 0010 = 0x02 5 7 8.4 8.4 FR4 10-inch trace 4 0 1 0000 0011 = 0x03 5.9 8 9.3 9.1 FR4 15- to 20-inch trace 5 R 0 0000 0111 = 0x07 7.4 10.3 12.8 13.7 FR4 20- to 30-inch trace 6 R R 0001 0101 = 0x15 6.9 10.2 13.9 16.2 FR4 25- to 30-inch trace 7 R Float 0000 1011 = 0x0B 9 12.4 15.3 15.9 FR4 25- to 30-inch trace 8 R 1 0000 1111 = 0x0F 10.2 13.8 16.7 17 8-m, 30-AWG cable > 8-m cable (1) 14 9 Float 0 0101 0101 = 0x55 8.5 12.6 17.5 20.7 10 Float R 0001 1111 = 0x1F 11.7 16.2 20.3 21.8 11 Float Float 0010 1111 = 0x2F 13.2 18.3 22.8 23.6 12 Float 1 0011 1111 = 0x3F 14.4 19.8 24.2 24.7 13 1 0 1010 1010 = 0xAA 14.4 20.5 26.4 28 14 1 R 0111 1111 = 0x7F 16 22.2 27.8 29.2 15 1 Float 1011 1111 = 0xBF 17.6 24.4 30.2 30.9 16 1 1 1111 1111 = 0xFF 18.7 25.8 31.6 31.9 Cable and FR4 lengths are for reference only. FR4 lengths based on a 100-Ω differential stripline with 5-mil traces and 8-mil trace separation. Optimal EQ setting should be determined through simulation and prototype verification. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DS125BR401 DS125BR401 www.ti.com SNLS419D – JULY 2012 – REVISED MAY 2015 Table 3. Output Voltage and De-Emphasis Settings LEVEL DEMA1 DEMB1 DEMA0 DEMB0 VOD Vp-p DEM dB (1) INNER AMPLITUDE Vp-p SUGGESTED USE (2) 1 0 0 0.8 0 0.8 FR4