DS15BR400EVK/NOPB

DS15BR400EVK Quad LVDS Buffer/Repeater with Preemphasis Evaluation Kit User Manual August 2006 Rev 0.3 DS15BR400 Evaluation Board User Manual Overview DS15BR400 is a four channel LVDS Buffer/Repeater, featuring pre-emphasis with maximum pre-emphasis gain of approximately 6 dB at 750 MHz. The device has internal 100-ohm resistors on both, the inputs and outputs, to improve performance and minimize board size. It utilizes LVDS technology for low power, high-speed and superior noise immunity. The purpose of this document is to familiarize you with the DS15BR400 Evaluation Board (DS15BR400EVK), suggest the test setup procedures and instrumentation, and to guide you through some typical measurements that will demonstrate the performance of the device. Description Figure 1 below represents the top layer drawing of the board with the silkscreen annotations. It is a four by four inch six layer printed circuit board (PCB) that has a single-device layout capable of demonstrating performance and all functions of the DS15BR400. Figure 1: DS15BR400 Evaluation Board - Top View 2 DS15BR400 Evaluation Board User Manual All LVDS inputs and outputs are accessible through SMA connectors and suitable for connections to 50-ohm instrumentation. The power can be applied using banana plugs. The control pins, PWDN* and PEM pins, are connected to 2-position switches. Test Setup Procedure The following is a recommended test setup procedure for the device evaluation. Figure 2 depicts a typical setup and instrumentation used for the device evaluation. 1. Apply the power to the device (3.3V typical) between VDD and VSS banana plug receptacles, observe the value of ICC, and compare it with the expected value (refer to the datasheet) to ensure that the device is functional. 2. Select I/O pairs you want to evaluate. For example, let’s say that we want to evaluate the IN0 to OUT0 signal path of the DS15BR400. The setup instructions that follow are based on this selection. 3. Connect a signal source (i.e. signal generator or an LVDS driver) to the IN0 inputs on the board and adjust the signal parameters (VOH, VOL, VCM) so that they comply with the device input recommendations. 4. Enable the DS15BR400 by setting PWDN* to high on CON1. Optionally, you may turn the preemphasis on for this output by setting PEM to “H” position on CON2. 5. Connect the OUT0 outputs to an oscilloscope and view the output signals with an oscilloscope with the bandwidth of at least 3 GHz. DS15BR400EVK SIGNAL GENERATOR OR BERT TX IN0+ OUT0+ IN0- OUT0- Figure 2. Typical Test Setup 3 OSCILLOSCOPE OR SERIAL BERT RX DS15BR400 Evaluation Board User Manual Figure 3 and 4 show an output eye diagram obtained using the DS15BR400EVK setup as in figure 2. The input was 400mV in amplitude with 1.2 V common mode voltage 1.5 Gbps NRZ PRBS-23. Figure 3. DS15BR400– Output Eye Diagram, Pre-emphasis OFF Figure 4. DS15BR400 – Output Eye Diagram, Pre-emphasis On 4 DS15BR400 Evaluation Board User Manual Figures 5 and 6 show the eye diagrams obtained at 2 Gbps with NRZ PRBS-23. Figure 5. DS15BR400– Output Eye Diagram, Pre-emphasis OFF Figure 6. DS15BR400 – Output Eye Diagram, Pre-emphasis On 5 DS15BR400 Evaluation Board User Manual Bill Of Materials DS15BR400 APPLICATION EVALUATION BOARD Revised: May 21, 2006 Item Part Type 1 CONN 2 CONN 3 CAP 4 CAP 5 CAP Part Number 50F1460 Mfg Description Qty ANY HEADER3X1 2 CON1,CON2 NEWARK JACK, Banana Plug Receptacle 2 CON3,CON4 ANY 0.01 F,±10%, 0603 2 C1,C4 ANY  1 C2 ANY 0.1µF, ±10%, 0603 1 C3 F, ±10%,0603 Ref Des 6 CAP ANY 22µF, ±10%, 7343 1 C5 7 RES ANY 100 Ohm 4 R1-R4 NEWARK SMA, 50 Ohm, End Launch 16 SMA1-SMA16 NAT 2 GHz 4 Channel Buffer/Repeater 1 U1 8 CONN 9 IC 99F6798 PCB Stack Up 6 Notes IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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