DS15BR400, DS15BR401
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SNLS224G – AUGUST 2006 – REVISED APRIL 2013
DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis
Check for Samples: DS15BR400, DS15BR401
FEATURES
DESCRIPTION
•
The DS15BR400/DS15BR401 are four channel LVDS
buffer/repeaters capable of data rates of up to 2
Gbps. High speed data paths and flow-through pinout
minimize internal device jitter and simplify board
layout, while pre-emphasis overcomes ISI jitter
effects from lossy backplanes and cables. The
differential inputs interface to LVDS, and Bus LVDS
signals such as those on TI's 10-, 16-, and 18- bit
Bus LVDS SerDes, as well as CML and LVPECL.
The differential inputs and outputs of the DS15BR400
are internally terminated with 100Ω resistors to
improve performance and minimize board space. The
DS15BR401 does not have input termination
resistors. The repeater function is especially useful
for boosting signals for longer distance transmission
over lossy cables and backplanes.
1
2
•
•
•
•
•
•
•
DC to 2 Gbps Low Jitter, High Noise Immunity,
Low Power Operation
6 dB of Pre-emphasis Drives Lossy
Backplanes and Cables
LVDS/CML/LVPECL Compatible Input, LVDS
Output
On-chip 100 Ω output termination, optional 100
Ω Input Termination
15 kV ESD Protection on LVDS Inputs and
Outputs
Single 3.3V Supply
Industrial -40 to +85°C Temperature Range
Space Saving WQFN-32 or TQFP-48 Packages
APPLICATIONS
•
•
•
Cable Extension Applications
Signal Repeating and Buffering
Digital Routers
The DS15BR400/DS15BR401 are powered from a
single 3.3V supply and consume 578 mW (typ). They
operate over the full -40°C to +85°C industrial
temperature range and are available in space saving
WQFN-32 and TQFP-48 packages.
Typical Application
LVDS I/O
FPGA or ASIC
Cable or Backplane
LVDS I/O
FPGA or ASIC
DS15BR400
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DS15BR400, DS15BR401
SNLS224G – AUGUST 2006 – REVISED APRIL 2013
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Block and Connection Diagrams
PEM
PWDN
PEM
Pre-emphasis
and Control
PWDN
Pre-emphasis
and Control
IN0+
OUT0+
IN0+
OUT0+
IN0-
OUT0-
IN0-
OUT0-
IN1+
OUT1+
IN1+
OUT1+
IN1-
OUT1-
IN1-
OUT1-
IN2+
OUT2+
IN2+
OUT2+
IN2-
OUT2-
IN2-
OUT2-
IN3+
OUT3+
IN3+
OUT3+
IN3-
OUT3-
IN3-
OUT3-
14
47
OUT0-
IN1+
15
46
OUT1+
IN1-
16
45
OUT1-
GND
17
44
GND
GND
18
43
GND
IN2+
19
42
OUT2+
IN2-
20
41
OUT2-
IN3+
21
40
OUT3+
IN3-
22
39
OUT3-
GND
23
38
GND
GND
24
37
GND
VDD
PEM
N/C
4
3
2
1
IN0- 10
31 OUT0-
IN1+ 11
30 OUT1+
DAP
(GND)
IN1- 12
29 OUT1-
IN2+ 13
28 OUT2+
IN2- 14
27 OUT2-
IN3+ 15
26 OUT3+
IN3- 16
25 OUT318
19 20
N/C
N/C
N/C
N/C
VDD
VDD
N/C
N/C
VDD
VDD
N/C
N/C
5
32 OUT0+
17
Figure 3. TQFP Pinout - Top View
Package Number PFB0048A
6
IN0+ 9
25 26 27 28 29 30 31 32 33 34 35 36
N/C
7
21 22 23
24
N/C
IN0-
8
N/C
OUT0+
N/C
48
VDD
1
VDD
2
VDD
N/C
3
VDD
PEM
4
GND
VDD
5
N/C
VDD
6
VDD
VDD
7
13
N/C
N/C
8
IN0+
Figure 2. DS15BR401 Block Diagram
PWDN
VDD
12 11 10 9
GND
GND
VDD
VDD
PWDN
Figure 1. DS15BR400 Block Diagram
Figure 4. WQFN Pinout - Top View
Package Number RTV0032A
PIN DESCRIPTIONS
Pin
Name
TQFP Pin
Number
WQFN Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS
IN0+
IN0−
13
14
9
10
I, LVDS
Channel 0 inverting and non-inverting differential inputs.
IN1+
IN1−
15
16
11
12
I, LVDS
Channel 1 inverting and non-inverting differential inputs.
IN2+
IN2−
19
20
13
14
I, LVDS
Channel 2 inverting and non-inverting differential inputs.
IN3+
IN3−
21
22
15
16
I, LVDS
Channel 3 inverting and non-inverting differential inputs.
2
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PIN DESCRIPTIONS (continued)
Pin
Name
TQFP Pin
Number
WQFN Pin
Number
I/O, Type
Description
DIFFERENTIAL OUTPUTS
OUT0+
OUT0−
48
47
32
31
O, LVDS
Channel 0 inverting and non-inverting differential outputs.
(1)
OUT1+
OUT1−
46
45
30
29
O, LVDS
Channel 1 inverting and non-inverting differential outputs.
(1)
OUT2+
OUT2−
42
41
28
27
O, LVDS
Channel 2 inverting and non-inverting differential outputs.
(1)
OUT3+
OUT3-
40
39
26
25
O, LVDS
Channel 3 inverting and non-inverting differential outputs.
(1)
DIGITAL CONTROL INTERFACE
PWDN
12
8
I, LVTTL
A logic low at PWDN activates the hardware power down mode (all channels).
PEM
2
2
I, LVTTL
Pre-emphasis Control Input (affects all Channels)
VDD
3, 4, 5, 7, 10,
11, 28, 29, 32,
33
3, 4, 6, 7, 20,
21
I, Power
VDD = 3.3V, ±10%
GND
8, 9, 17, 18, 23,
24, 37, 38, 43,
44
I, Ground
Ground reference for LVDS and CMOS circuitry. For the WQFN package, the
DAP is used as the primary GND connection to the device in addition to the pin
numbers listed. The DAP is the exposed metal contact at the bottom of the
WQFN-32 package. It should be connected to the ground plane with at least 4
vias for optimal AC and thermal performance.
N/C
1,6, 25, 26, 27,
30, 31, 34, 35,
36
POWER
(1)
(2)
5
(2)
1, 17,
18,19,22, 23,
24
No Connect
The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15BR400 and
DS15BR401 are optimized for point-to-point backplane and cable applications.
Note that for the WQFN package the GND is connected thru the DAP on the back side of the WQFN package in addition to the actual
pin numbers listed.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1)
Supply Voltage (VDD)
−0.3V to +4.0V
CMOS Input Voltage
−0.3V to (VDD+0.3V)
LVDS Receiver Input Voltage
−0.3V to (VDD+0.3V)
LVDS Driver Output Voltage
−0.3V to (VDD+0.3V)
LVDS Output Short Circuit Current
+40 mA
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature (Solder, 4sec)
260°C
Max Pkg Power Capacity @ 25°C
TQFP
WQFN
1.64W
4.16W
Thermal Resistance (θJA)
TQFP
WQFN
76°C/W
30°C/W
Package Derating above +25°C
TQFP
WQFN
13.2mW/°C
33.3mW/°C
ESD Last Passing Voltage
HBM, 1.5kΩ, 100pF
8 kV
LVDS pins to GND only
15 kV
EIAJ, 0Ω, 200pF
250V
Charged Device Model
(1)
1000V
Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI
does not recommend operation of products outside of recommended operation conditions.
Recommended Operating Conditions
Supply Voltage (VDD)
3.0V to 3.6V
(1)
0V to VDD
Output Voltage (VO)
0V to VDD
Input Voltage (VI)
Operating Temperature (TA)
−40°C to +85°C
Industrial
(1)
VID max < 2.4V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(1)
Max
Units
LVCMOS DC SPECIFICATIONS (PWDN, PEM)
VIH
High Level Input Voltage
2.0
VDD
V
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = VDD = 3.6V (PWDN pin)
−10
+10
µA
IIHR
High Level Input Current
VIN = VDD = 3.6V (PEM pin)
40
200
µA
IIL
Low Level Input Current
VIN = VSS, VDD = 3.6V
−10
+10
µA
CIN1
LVCMOS Input Capacitance
Any Digital Input Pin to VSS
VCL
Input Clamp Voltage
ICL = −18 mA, VDD = 0V
(1)
4
−1.5
5.5
pF
−0.8
V
Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(1)
Max
Units
0
100
mV
LVDS INPUT DC SPECIFICATIONS (INn±)
VTH
Differential Input High
Threshold (2)
VCM = 0.8V to 3.55V,
VDD = 3.6V
VTL
Differential Input Low
Threshold (2)
VCM = 0.8V to 3.55V,
VDD = 3.6V
VID
Differential Input Voltage
VCM = 0.8V to 3.55V, VDD = 3.6V
VCMR
Common Mode Voltage Range VID = 150 mV, VDD = 3.6V
CIN2
LVDS Input Capacitance
IN+ or IN− to VSS
IIN
Input Current
VIN = 3.6V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
−100
0
mV
100
2400
mV
0.05
3.55
V
−10
+10
µA
−10
+10
µA
500
mV
35
mV
1.475
V
35
mV
3.0
pF
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
VOD
Differential Output Voltage,
0% Pre-emphasis (2)
ΔVOD
Change in VOD between
Complementary States
RL = 100Ω external resistor between OUT+ and OUT−
Figure 5
250
360
−35
(3)
VOS
Offset Voltage
ΔVOS
Change in VOS between
Complementary States
1.05
1.18
COUT
LVDS Output Capacitance
OUT+ or OUT− to VSS
2.5
IOS
Output Short Circuit Current
OUT+ or OUT− Short to GND
−21
−40
mA
OUT+ or OUT− Short to VDD
6
40
mA
175
215
mA
20
200
µA
170
250
ps
170
250
ps
1.0
2.0
ns
1.0
2.0
ns
|tPLHD–tPHLD|
10
60
ps
Difference in propagation delay (tPLHD or tPHLD) among all
output channels.
25
75
ps
550
ps
−35
pF
SUPPLY CURRENT (Static)
ICC
Supply Current
All inputs and outputs enabled and active, terminated with
differential load of 100Ω between OUT+ and OUT-. PEM = L
ICCZ
Supply Current - Power Down
Mode
PWDN = L, PEM = L
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT
Differential Low to High
Transition Time (4)
tHLT
Differential High to Low
Transition Time (4)
tPLHD
Differential Low to High
Propagation Delay
tPHLD
Differential High to Low
Propagation Delay
tSKD1
Pulse Skew
tSKCC
Output Channel to Channel
Skew (4)
tSKP
Part to Part Skew
(2)
(3)
(4)
(4)
(4)
Use an alternating 1 and 0 pattern at 200 Mbps, measure
between 20% and 80% of VOD.
Figure 6 , Figure 8
Use an alternating 1 and 0 pattern at 200 Mbps, measure at
50% VOD between input to output.
Figure 6 , Figure 7
Common edge, parts at same temp and VCC
Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
tJIT
Parameter
Conditions
Jitter (0% Pre-emphasis)
RJ - Alternating 1 and 0 at 750 MHz
(5)
DJ - K28.5 Pattern, 1.5 Gbps
Min
(6)
(7)
TJ - PRBS 223-1 Pattern, 1.5 Gbps
(8)
Typ
(1)
Max
Units
0.5
1.5
ps
14
30
ps
14
31
ps
tON
LVDS Output Enable Time
Time from PWDN to OUT± change from TRI-STATE to active.
Figure 9, Figure 10
20
µs
tOFF
LVDS Output Disable Time
Time from PWDN to OUT± change from active to TRI-STATE.
Figure 9, Figure 10
12
ns
(5)
(6)
(7)
(8)
Jitter is not production tested, but ensured through characterization on a sample basis.
Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = VID = 500 mV, input common mode voltage = VICM = 1.2V, 50% duty cycle at 750 MHz, tr = tf = 50 ps
(20% to 80%).
Deterministic Jitter, or DJ, is a peak to peak value. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500 mV,
input common mode voltage = VICM = 1.2V, K28.5 pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%). The K28.5 pattern is repeating bit
streams of (0011111010 1100000101).
Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = VID = 500 mV, input common mode voltage = VICM = 1.2V, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50
ps (20% to 80%).
DC Test Circuits
1/4 DS15BR400
VOH
OUT+
IN+
Power Supply
R
D
RL
Power Supply
IN-
OUTVOL
Figure 5. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
1/4 DS15BR400
OUT+
IN+
R
Signal Generator
IN-
D
RL
OUT-
Figure 6. Differential Driver AC Test Circuit
Figure 7. Propagation Delay Timing Diagram
6
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Figure 8. LVDS Output Transition Times
1/4 DS15BR400
Power Supply
OUT+
IN+
R
D
RL/ 2
1.2V
Power Supply
IN-
OUT-
RL/ 2
PWDN
Pulse Generator
50:
Figure 9. Enable/Disable Time Test Circuit
Figure 10. Enable/Disable Time Diagram
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APPLICATION INFORMATION
INTERNAL TERMINATIONS
The DS15BR400 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω
resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the
device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to
minimize the output return loss and does not take the place of the 100 ohm termination at the inputs to the
receiving device. The integrated terminations improve signal integrity and decrease the external component
count resulting in space savings. The DS15BR401 has 100Ω output terminations only.
OUTPUT CHARACTERISTICS
The output characteristics of the DS15BRB400/DS15BR401 have been optimized for point-to-point backplane
and cable applications, and are not intended for multipoint or multidrop signaling.
POWERDOWN MODE
The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all
input and output buffers and internal bias circuitry are powered off. When exiting powerdown mode, there is a
delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS
Output Switching Characteristics.
Upon asserting the power down function (PWDN = Low), and if the Pre-emphasis feature is enable, it is possible
for the driver output to source current for a short amount of time lifting the output common mode to VDD. To
prevent this occurrence, a load discharge pull down path can be used on either output (1 kΩ to ground
recommended). Alternately, a commonly deployed external failsafe network will also provide this path (see
INPUT FAILSAFE BIASING). The occurrence of this is application dependant, and parameters that will effect if
this is of concern include: AC coupling, use of the powerdown feature, presence of the discharge path, presence
of the failsafe biasing, the usage of the pre-emphasis feature, and input characteristics of the downstream LVDS
Receiver.
PRE-EMPHASIS
Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. One pin is used to select the
pre-emphasis level for all outputs, off or on. The pre-emphasis boost is approximately 6 dB at 750 MHz.
Table 1. Pre-emphasis Control Selection Table
PEM
Pre-Emphasis
0
Off
1
On
INPUT FAILSAFE BIASING
Failsafe biasing of the LVDS link should be considered if the downstream Receiver is ON and enabled when the
source is in TRI-STATE, powered off, or removed. This will set a valid known input state to the active receiver.
This is accomplished by using a pull up resistor to VDD on the ‘plus’ line, and a pull down resistor to GND on the
‘minus’ line. Resistor values are in the 750 Ohm to several kΩ range. The exact value depends upon the desired
common mode bias point, termination resistor(s) and desired input differential voltage setting. Please refer to
application note AN-1194 “Failsafe Biasing of LVDS interfaces” (SNLA051) for more information and a general
discussion.
DECOUPLING
Each power or ground lead of the DS15BR400 should be connected to the PCB through a low inductance path.
For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally, via
placement is immediately adjacent to the pin to avoid adding trace inductance. Placing power plane closer to the
top of the board reduces effective via length and its associated inductance.
8
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Bypass capacitors should be placed close to VDD pins. Small physical size capacitors, such as 0402, X7R,
surface mount capacitors should be used to minimize body inductance of capacitors. Each bypass capacitor is
connected to the power and ground plane through vias tangent to the pads of the capacitor. An X7R surface
mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30 MHz or so, X7R
capacitors behave as low impedance inductors. To extend the operating frequency range to a few hundred MHz,
an array of different capacitor values like 100 pF, 1 nF, 0.03 µF, and 0.1 µF are commonly used in parallel. The
most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2–3
mils. With a 2 mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.
The center dap of the WQFN package housing the DS15BR400 should be connected to a ground plane through
an array of vias. The via array reduces the effective inductance to ground and enhances the thermal
performance of the WQFN package.
INPUT INTERFACING
The DS15BR400 and DS15BR401 accept differential signals and allow simple AC or DC coupling. With a wide
common mode range, the DS15BR400 and DS15BR401 can be DC-coupled with all common differential drivers
(i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common
differential drivers. Note that the DS15BR400 inputs are internally terminated with a 100Ω resistor while the
DS15BR401 inputs are not, therefore the latter requires external input termination.
LVDS
Driver
DS15BR400
Receiver
100: Differential T-Line
OUT+
IN+
100:
IN-
OUT-
Figure 11. Typical LVDS Driver DC-Coupled Interface to DS15BR400 Input
CML3.3V or CML2.5V
Driver
VCC
50:
DS15BR400
Receiver
100: Differential T-Line
50:
OUT+
IN+
100:
IN-
OUT-
Figure 12. Typical CML Driver DC-Coupled Interface to DS15BR400 Input
LVPECL
Driver
OUT+
100: Differential T-Line
LVDS
Receiver
IN+
100:
OUT150-250:
IN150-250:
Figure 13. Typical LVPECL Driver DC-Coupled Interface to DS15BR400 Input
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OUTPUT INTERFACING
The DS15BR400 and DS15BR401 output signals that are compliant to the LVDS standard. Their outputs can be
DC-coupled to most common differential receivers. Figure 14 illustrates typical DC-coupled interface to common
differential receivers and assumes that the receivers have high impedance inputs. While most differential
receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to
check respective receiver's data sheet prior to implementing the suggested interface implementation.
DS15BR400
Driver
Differential
Receiver
100: Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100:
100:
IN-
OUT-
Figure 14. Typical DS15BR400 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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Typical Performance Characteristics
Total Jitter vs. Ambient Temperature
30
250
25
TOTAL JITTER (ps)
POWER SUPPLY CURRENT (mA)
Power Supply Current vs. Data Rate
300
200
150
VCC = 3.3V
100
VID = 500 mV
VCM = 1.2V
NRZ PRBS-23
50
TA =25°C
0
0
0.4
0.8
1.2
1.6
20
15
VCC = 3.3V
10
VID = 500 mV
5
VCM = 1.2V
NRZ PRBS-23
1.5 Gbps
0
-40
2.0
-20
DATA RATE (Gbps)
80
100
Data Rate vs. Cable Length (0.25 UI Criteria)
2.5
VCC = 3.3V
NRZ PRBS-23
Jitter = 0.25 UI
2.0
DATA RATE (Gbps)
TOTAL JITTER (ps)
60
Total Jitter vs. Data Rate
20
15
0
1.0
40
Figure 16.
25
5
20
Figure 15.
30
10
0
TEMPERATURE (°C)
VCC = 3.3V
VID = 500 mV
VCM = 1.2V
NRZ PRBS-23
TA = 25°C
1.2
1.4
TA = 25 °C
CAT5e
1.5
PEM
ON
PEM
OFF
1.0
0.5
1.6
1.8
0
2.0
1
DATA RATE (Gbps)
10
20
30
40
CABLE LENGTH (m)
Figure 17.
Figure 18.
(1)
Data Rate vs. Cable Length (0.5 UI Criteria)
2.5
VCC = 3.3V
NRZ PRBS-23
Jitter = 0.5 UI
DATA RATE (Gbps)
2.0
TA = 25°C
CAT5e
1.5
PEM
OFF
PEM
ON
1.0
0.5
0
1
10
20
30
40
CABLE LENGTH (m)
Figure 19.
(1)
(1)
Data presented in this graph was collected using the DS15BR400EVK, a pair of RJ-45 to SMA adapter boards and various length
Belden 1700a cables. The maximum data rate was determined based on total jitter (0.25 UI criteria) measured after the cable. The total
jitter was a peak to peak value measured with a histogram including 3000 window hits.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15BR400 DS15BR401
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11
DS15BR400, DS15BR401
SNLS224G – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15BR400 DS15BR401
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS15BR400TSQ
NRND
WQFN
RTV
32
1000
Non-RoHS
& Green
Call TI
Level-3-260C-168 HR
-40 to 85
5R400SQ
DS15BR400TSQ/NOPB
ACTIVE
WQFN
RTV
32
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
5R400SQ
DS15BR400TVS
NRND
TQFP
PFB
48
250
Non-RoHS
& Green
Call TI
Level-3-260C-168 HR
-40 to 85
DS15BR
400TVS
DS15BR400TVS/NOPB
ACTIVE
TQFP
PFB
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS15BR
400TVS
DS15BR400TVSX/NOPB
ACTIVE
TQFP
PFB
48
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS15BR
400TVS
DS15BR401TSQ/NOPB
ACTIVE
WQFN
RTV
32
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
5R401SQ
DS15BR401TVS/NOPB
ACTIVE
TQFP
PFB
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS15BR
401TVS
DS15BR401TVSX/NOPB
ACTIVE
TQFP
PFB
48
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
DS15BR
401TVS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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