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DS250DF410
SNLS456D – MARCH 2016 – REVISED OCTOBER 2019
DS250DF410 25 Gbps Multi-Rate 4-Channel Retimer
1 Features
2 Applications
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Quad-channel multi-rate retimer with integrated
signal conditioning
All channels lock independently from 20.2752 to
25.8 Gbps (including sub-rates such as 10.3125
Gbps, 12.5 Gbps, and more)
Ultra-low latency: 10 MHz, sinusoidal (1)
10
mVpp
TrampVDD
VDD supply ramp time, from 0V to 2.375V
150
TJ
Operating junction temperature
-40
110
ºC
TA
Operating ambient temperature
-40
85 (2)
ºC
VIO2.5V
2.5 V I/O voltage (LVCMOS, CMOS and Analog)
2.375
2.625
V
VIO3.3V,INT_N
Open Drain LVCMOS I/O voltage (INT_N)
3.6
V
VIO3.3V
Open Drain LVCMOS I/O voltage (SDA, SDC)
3.6
V
(1)
(2)
8
2.375
μs
Steps must be taken to ensure the combined AC plus DC supply noise meets the specified VDD supply voltage limits.
Steps must be taken to ensure the operating junction temperature range and ambient temperature stay-in-lock range (TEMPLOCK+,
TEMPLOCK-) are met. Refer to Electrical Characteristics for more details concerning TEMPLOCK+ and TEMPLOCK-.
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Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: DS250DF410
DS250DF410
www.ti.com
SNLS456D – MARCH 2016 – REVISED OCTOBER 2019
7.4 Thermal Information
DS250DF410
THERMAL METRIC (1)
CONDITIONS/ASSUMPTIONS (2)
FC/CSP (ABM)
UNIT
101 PINS
RθJA
Junction-to-ambient thermal resistance
4-Layer JEDEC Board
34.2
10-Layer 8-in x 6-in Board
16.7
20-Layer 8-in x 6-in Board
15.6
30-Layer 8-in x 6-in Board
14.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
4-Layer JEDEC Board
7.8
°C/W
RθJB
Junction-to-board thermal resistance
4-Layer JEDEC Board
13.7
°C/W
4-Layer JEDEC Board
0.004
10-Layer 8-in x 6-in Board
0.004
20-Layer 8-in x 6-in Board
0.004
30-Layer 8-in x 6-in Board
0.004
4-Layer JEDEC Board
13.0
10-Layer 8-in x 6-in Board
11.7
20-Layer 8-in x 6-in Board
11.5
30-Layer 8-in x 6-in Board
11.3
Junction-to-top characterization parameter
ΨJT
Junction-to-board characterization parameter
ΨJB
(1)
(2)
°C/W
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
No heat sink or airflow was assumed for these estimations. Depending on the application, a heat sink, faster airflow, and/or reduced
ambient temperature (
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