DS36954
www.ti.com
SNLS077C – JULY 1998 – REVISED APRIL 2013
DS36954 Quad Differential Bus Transceiver
Check for Samples: DS36954
FEATURES
DESCRIPTION
•
•
•
The DS36954 is a low power, quad EIA-485
differential bus transceiver especially suited for high
speed, parallel, multipoint, I/O bus applications. A
compact 20-pin surface mount PLCC or SOIC
package provides high transceiver integration and a
very small PC board footprint.
1
2
•
•
•
Pinout for SCSI Interface
Compact 20-Pin PLCC or SOIC Package
Meets EIA-485 Standard for Multipoint Bus
Transmission
Greater than 60 mA Source/Sink Currents
Thermal Shutdown Protection
Glitch-Free Driver Outputs on Power Up and
Down
Propagation delay skew between devices is specified
to aid in parallel interface designs—limits on
maximum and minimum delay times are verified.
Five devices can implement a complete SCSI initiator
or target interface. Three transceivers in a package
are pinned out for data bus connections. The fourth
transceiver, with the flexibility provided by its
individual enables, can serve as a control bus
transceiver.
Connection Diagram
Logic Diagram
See Package Number FN (S-PQCC-J20)
See Package Number DW (R-PDSO-G20)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
DS36954
SNLS077C – JULY 1998 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Supply Voltage
7V
Control Input Voltage
VCC + 0.5V
Driver Input Voltage
VCC + 0.5V
−10V to +15V
Driver Output Voltage/Receiver Input Voltage
Receiver Output Voltage
5.5V
Continuous Power Dissipation @ +25°C
FN Package
1.73W
DW Package
1.73W
Derate FN Package
13.9 mW/°C above +25°C
Derate DW Package
13.7 mW/°C above +25°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature (Soldering 4 Sec.)
(1)
260°C
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply
that the devices should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
If Military/Aerospace specified devices are required, please contact the Texas Instrument Sales Office/ Distributors for availability and
specifications.
(2)
Recommended Operating Conditions
Supply Voltage, VCC
Bus Voltage
Operating Free Air Temperature (TA)
Electrical Characteristics
Min
Max
Units
4.75
5.25
V
−7
+12
V
0
+70
°C
(1) (2)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER CHARACTERISTICS
VODL
Differential Driver Output Voltage (Full IL = 60 mA
Load)
VCM = 0V
1.5
1.9
V
VOD
Differential Driver Output Voltage
(Termination Load)
RL = 100Ω (EIA-422)
2.0
2.25
V
RL = 54Ω (EIA-485)
1.5
2.0
ΔIVODI
Change in Magnitude of Driver
Differential Output Voltage for
Complementary Output States
RL = 54 or 100Ω
VOC
Driver Common Mode Output Voltage RL = 54Ω (Figure 1 ) (EIA-485)
ΔIVOCI
Change in Magnitude of Common
Mode Output Voltage
(3)
VOH
Output Voltage High
IOH = −55 mA
VOL
Output Voltage Low
IOL = 55 mA
VIH
Input Voltage High
VIL
Input Voltage Low
VCL
Input Clamp Voltage
(1)
(2)
(3)
(4)
2
(3)
(Figure 1 ) (EIA-422/485)
(4)
(Figure 1 ) (EIA-422/485)
2.7
V
0.2
V
3.0
V
0.2
V
3.2
1.4
V
1.7
2.0
ICL = −18 mA
V
V
0.8
V
−1.5
V
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
All typicals are given for VCC = 5V and TA = 25°C.
Δ IVODI and Δ IVOCI are changes in magnitude of VOD and VOC, respectively, that occur when the input changes state.
In EIA Standards EIA-422 and EIA-485, VOC, which is the average of the two output voltages with respect to ground, is called output
offset voltage, VOS .
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Electrical Characteristics (1)(2) (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified
Symbol
Parameter
Conditions
IIH
Input High Current
VIN = 2.4V
(5)
IIL
Input Low Current
VIN = 0.4V
(5)
IOSC
Driver Short-Circuit Output Current
(6)
Min
Typ
Max
Units
20
μA
−20
μA
VO = −7V (EIA-485)
−130
−250
mA
VO = 0V (EIA-422)
−90
−150
mA
VO = +12V (EIA-485)
130
250
mA
−15
−28
−75
mA
20
μA
2.4
3.0
RECEIVER CHARACTERISTICS
(6)
IOSR
Short Circuit Output Current
VO = 0V
IOZ
TRI-STATE Output Current
VO = 0.4V to 2.4V
VOH
Output Voltage High
VID = 0.2V, IOH = 0.4 mA
VOL
Output Voltage Low
VID = −0.2V, IOL = 4 mA
0.35
0.5
V
VTH
Differential Input High Threshold
Voltage
VO = VOH, IO = −0.4 mA (EIA-422/485)
0.03
0.2
V
VTL
Differential Input Low Threshold
Voltage (7)
VO = VOL, IO = 4.0 mA (EIA-422/485)
VHST
Hysteresis
(8)
VCM = 0V
V
−0.2
0
−0.03
V
35
60
mV
DRIVER AND RECEIVER CHARACTERISTICS
VIH
Enable Input Voltage High
VIL
Enable Input Voltage Low
VCL
Enable Input Clamp Voltage
IIN
Line Input Current
IING
Line Input Current
IIH
(9)
(9)
Enable Input Current High
IIL
Enable Input Current Low
2.0
V
0.8
ICL = −18 mA
V
−1.5
V
Other Input = 0V
DE/RE = 0.8V
DE4 = 0.8V
VI = +12V
0.5
1.0
mA
VI = −7V
−0.45
−0.8
mA
Other Input = 0V
DE/RE and DE4 = 2V
VCC = 3.0V
TA = +25°C
VI = +12V
1.0
mA
−0.8
mA
VIN = 2.4V
DE/RE
VCC = 3.0V
1
40
μA
VCC = 4.75V
1
VI = −7V
μA
VCC = 5.25V
1
40
μA
VIN = 2.4V
DE4 or RE4
VCC = 3.0V
1
20
μA
VCC = 5.25V
1
20
μA
VIN = 0.8V
DE/RE
VCC = 3.0V
−6
−40
μA
VCC = 4.75V
−12
VCC = 5.25V
−14
−40
μA
VCC = 3.0V
−3
−20
μA
−7
VIN = 0.8V
DE4 or RE4
μA
−20
μA
ICCD
Supply Current
(10)
No Load, DE/RE and DE4 = 2.0V
75
90
mA
ICCR
Supply Current
(10)
No Load, DE/RE and RE4 = 0.8V
50
70
mA
(5)
(6)
(7)
(8)
(9)
(10)
VCC = 5.25V
IIH and IIL include driver input current and receiver TRI-STATE leakage current on DR(1–3).
Short one output at a time.
Threshold parameter limits specified as an algebraic value rather than by magnitude.
Hysteresis defined as VHST = V TH − VTL.
IIN includes the receiver input current and driver TRI-STATE leakage current.
Total package supply current.
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DS36954
SNLS077C – JULY 1998 – REVISED APRIL 2013
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Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER SINGLE-ENDED CHARACTERISTICS
tPZH
Output Enable Time to High Level
(Figure 6 )
35
40
ns
tPZL
Output Enable Time to Low Level
RL = 110Ω
(Figure 8 )
25
40
ns
tPHZ
Output Disable Time to High Level
(Figure 6 )
15
25
ns
tPLZ
Output Disable Time to Low Level
(Figure 8 )
35
40
ns
13
16
ns
9
15
19
ns
9
12
19
ns
3
6
ns
9
14
19
ns
9
13
19
ns
1
3
ns
15
22
ns
20
30
ns
DRIVER DIFFERENTIAL CHARACTERISTICS
tr, tf
Rise and Fall Time
tPLHD
Differential Propagation
tPHLD
Delays
tSKD
|tPLHD − tPHLD| Diff. Skew
(2)
RL = 54Ω
CL = 50 pF
CD = 15 pF
(Figure 3 Figure 4
(1)
)
RECEIVER CHARACTERISTICS
tPLHD
Differential Propagation Delays
tPHLD
CL = 15 pF
VCM = 2.0V
(Figure 10 )
tSKD
|tPLHD − tPHLD| Diff. Receiver Skew
tPZH
Output Enable Time to High Level
tPZL
Output Enable Time to Low Level
tPHZ
Output Disable Time from High Level
20
30
ns
tPLZ
Output Disable Time from Low Level
17
25
ns
(1)
(2)
4
CL = 15 pF
(Figure 15 )
Propagation Delay Timing for Calculations of Driver Differential Propagation Delays
Differential propagation delays are calculated from single-ended propagation delays measured from driver input to the 20% and 80%
levels on the driver outputs (Figure 16) .
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SNLS077C – JULY 1998 – REVISED APRIL 2013
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD and VOC (3)
Figure 2. Receiver VOH and VOL
(2)
(1)
(1)
The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf <
6.0 ns, ZO = 50Ω
(2)
CL includes probe and stray capacitance.
Figure 3. Driver Differential Propagation Delay Load Circuit
(1)
(1)
Differential propagation delays are calculated from single-ended propagation delays measured from driver input to the
20% and 80% levels on the driver outputs (Figure 16).
Figure 4. Driver Differential Propagation Delays and Transition Times
(3)
CL includes probe and stray capacitance.
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(2)
(1)
S1 to OA for DI = 3V
S1 to OB for DI = 0V
(1)
The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf <
6.0 ns, ZO = 50Ω.
(2)
CL includes probe and stray capacitance.
Figure 5.
Figure 6. Driver Enable and Disable Timing (tPZH, t PHZ)
(1)
(2)
S1 to OA for DI = 0V
S1 to OB for DI = 3V
(1)
The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf <
6.0 ns, ZO = 50Ω.
(2)
CL includes probe and stray capacitance.
Figure 7.
6
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SNLS077C – JULY 1998 – REVISED APRIL 2013
Figure 8. Driver Enable and Disable Timing (tPZL, t PLZ)
(1)
(2)
(1)
The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf <
6.0 ns, ZO = 50Ω.
(2)
CL includes probe and stray capacitance.
Figure 9.
Figure 10. Receiver Differential Propagation Delay Timing
(1)
(4)
(3)
(2)
(1)
The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf <
6.0 ns, ZO = 50Ω.
(2)
CL includes probe and stray capacitance.
(3)
Diodes are 1N916 or equivalent.
(4)
On transceivers 1–3 the driver is loaded with receiver input conditions when DE/RE is high. Do not exceed the
package power dissipation limit when testing.
Figure 11.
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DS36954
SNLS077C – JULY 1998 – REVISED APRIL 2013
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S1 1.5V
S2 Open
S3 Closed
Figure 12.
S1 −1.5V
S2 Closed
C3 Open
Figure 13.
S1 1.5V
S2 Closed
C3 Closed
Figure 14.
S1 −1.5V
S2 Closed
C3 Closed
Figure 15. Receiver Enable and Disable Timing
8
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DS36954
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SNLS077C – JULY 1998 – REVISED APRIL 2013
Tra, Trb, Tfa and Tfb are propagation delay measurements to the 20% and 80% levels.
TCP = Crossing Point
Figure 16. Propagation Delay Timing for Calculations of Driver Differential Propagation Delays
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DS36954
SNLS077C – JULY 1998 – REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
•
10
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
TBD
Call TI
Call TI
0 to 70
DS36954
M
(4/5)
DS36954M
NRND
SOIC
DW
20
DS36954M/NOPB
ACTIVE
SOIC
DW
20
36
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 70
DS36954
M
DS36954MX/NOPB
ACTIVE
SOIC
DW
20
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 70
DS36954
M
DS36954VX
NRND
PLCC
FN
20
TBD
Call TI
Call TI
0 to 70
DS36954V
DS36954VX/NOPB
ACTIVE
PLCC
FN
20
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2A-250C-4
WEEK
0 to 70
DS36954V
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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2-Oct-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS36954MX/NOPB
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
10.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.3
3.25
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS36954MX/NOPB
SOIC
DW
20
1000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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• DALLAS, TEXAS 75265
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