DS38EP100SDX/NOPB

DS38EP100 www.ti.com SNLS278C – JULY 2007 – REVISED APRIL 2013 DS38EP100 1 to 5 Gbps, Power-Saver Equalizer for Backplanes and Cables Check for Samples: DS38EP100 FEATURES DESCRIPTION • • • • • TI’s Power-saver equalizer compensates for transmission medium losses and minimizes mediuminduced deterministic jitter. Performance is ensured over the full range of 1 to 5 Gbps. The DS38EP100 requires no power to operate. The equalizer operates anywhere in the data path to minimize media-induced deterministic jitter in both FR4 and cable applications. Symmetric I/O structures support full duplex or half duplex applications. Linear compensation is provided independent of line coding or protocol. The device is ideal for both bi-level and multi-level signaling. 1 2 • • • • • • • • 1 to 5 Gbps Operation No Power or Ground Required Equalization Effective Anywhere in Data Path Equalizes CML, LV-PECL, LVDS Signals Symmetric I/O Structures Provide Equal Boost for Bi-directional Operation 7 dB Maximum Boost Code Independent, 8b/10b or Scrambled Supports Both Bi-level and Multi-level Signaling Extends Reach Over Backplanes and Cables Compatible with PCI-Express Gen1 and Gen2 Compatible with XAUI Operates in Series with Existing Active Equalizer Easy to Handle 6 Pin WSON The equalizer is available in a 6 pin leadless WSON package with a space saving 2.2 mm X 2.5 mm footprint. This tiny package provides maximum flexibility in placement and routing of the Power-saver equalizer. Simplified Application Diagram LINE CARD Tx/Rx DS38EP100 IOA+ IOB+ IOA- IOB- ZDiff = 100: SWITCH CARD Rx/Tx PASSIVE BACKPLANE/CABLE INTERCONNECT DS38EP100 Tx/Rx IOA+ IOB+ IOA- IOB- ZDiff = 100: ZDiff = 100: Rx/Tx NOTE The DS38EP100 provides the flexibility of passing the data from either side of the device. It can be placed anywhere in the data path.. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated DS38EP100 SNLS278C – JULY 2007 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS Pin Name Pin Number I/O, Type Description High Speed Differential I/O IOAIOA+ 3 1 I/O Symmetric differential I/O. IOBIOB+ 4 6 I/O Symmetric differential I/O. NC Exposed Pad 2, 5 DAP N/A Reserved. Do not connect. Pin Diagram IOA+ NC IOA- 1 2 3 DAP - NC 6 5 4 IOB+ NC IOB- 2.2mm × 2.5mm 6-Pin WSON Package Bottom View These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) INPUT/OUTPUT (IOA+ and IOB+) or (IOA- and IOB-) +2V (IOA+ and IOA-) or (IOB+ and IOB-) +4V (IOA+ and IOB-) or (IOA- and IOB+) +4V Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature Soldering, 4 sec +260°C ESD Rating HBM, 1.5 kΩ, 100 pF (1) (2) 1.3kV “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Recommended Operating Conditions Operating Temperature Bit Rate 2 Min Typ Max −40 25 +85 °C 5 Gbps 1 Submit Documentation Feedback Units Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 DS38EP100 www.ti.com SNLS278C – JULY 2007 – REVISED APRIL 2013 Electrical Characteristics (1) Over recommended operating conditions unless other specified. All parameters are ensured by test, statistical analysis or design. Symbol VIN Parameter Conditions (3) (3) (4) (5) (2) Max Units 1000 3600 mVp-p See Equalization 2.5 GHz relative to 100MHz 6 dB RLI Differential input return loss 100 MHz – 2.5 GHz, with fixture's effect deembedded 15 dB RLO Differential output return loss 100 MHz – 2.5 GHz, with fixture's effect deembedded. IOA+,or IOB+ = static high. 15 dB RIN Input Impedance Differential across IOA+ and IOA-, or IOB+ and IOB-, ZLOAD = 100Ω 100 Ω RO Output Impedance Differential across IOA+ and IOA-, or IOB+ and IOB-, ZSOURCE = 100Ω 100 Ω Through Response Relative to ideal load, see Figure 2 for setup R1 Resistance IOA+ to IOA- and IOB+ to IOB- No load, high impedance on all ports R2 Resistance IOA+ to IOB+ and IOA- to IOB- No load, high impedance on all ports R3 Resistance IOA+ to IOB- and IOA- to IOB+ No load, high impedance on all ports (IOA/IOB or IOB/IOA) (2) Typ Input voltage swing DC Gain (1) Min DJ1 Residual deterministic jitter DJ2 Residual deterministic jitter DJ3 Residual deterministic jitter DJ4 Residual deterministic jitter Z LOAD = 100Ω 2.5 Gbps, 40 in of 6mil microstrip FR4 See (4) 3.125 Gbps, 40 in of 6mil microstrip FR4 See (4) (5) 3.8 Gbps, 40 in of 6mil microstrip FR4 See (4) (5) 5 Gbps, 30 in of 6mil microstrip FR4 See (4) See Figure 3 and Table 1 for limits 150 Ω 50 Ω 150 Ω 0.4 0.1 UIp-p 0.1 0.15 UIp-p 0.1 0.15 UIp-p 0.1 UIp-p The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms, TA = +25 degC, and at the Recommended Operating Conditions at the time of product characterization and are not ensured. Differential signal to Equalizer, measured at the input to a transmission line, see point A of Figure 1. The transmission line is Z0 = 100Ω, 6-mil, microstrip in FR4 material. Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1). Test pattern: PRBS- 7 . Specification is ensured by characterization and is not tested in production. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 3 DS38EP100 SNLS278C – JULY 2007 – REVISED APRIL 2013 www.ti.com Test Setup Diagrams A B C Test Board FR4 Test Channel 0 in < L < 40 in Signal Source Oscilloscope DS38EP100 = Edge-Mounted SMA Connector Figure 1. Transient Test Setup Diagram d 0.5 in DUAL 50: MICROSTRIP LINE d 0.5 in DUAL 50: MICROSTRIP LINE VNA Source VNA Detector DS38EP100 = Edge-Mounted SMA Connector Figure 2. Frequency Response Test Circuit Typical Equalizer Transfer Function 0 -1 -2 S21 (dB) -3 -4 -5 -6 -7 -8 -9 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (GHz) Figure 3. Typical Equalizer Transfer Function 4 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 DS38EP100 www.ti.com SNLS278C – JULY 2007 – REVISED APRIL 2013 Table 1. Typical Through Response Frequency (GHz) DS38EP100 Attenuation Typ (dB) 0.1 -7.98 0.5 -5.93 1 -3.53 1.5 -2.25 2 -1.58 3 -1.14 4 -1.26 5 -1.54 6 -1.99 7 -2.62 8 -3.26 9 -3.61 10 -4.26 Block Diagram Z3 IOA+ Z1 A Z1 IOB+ B Z2 IOA- Z1 Z1 IOB- Z3 Figure 4. Simplified Block Diagram APPLICATION INFORMATION DS38EP100 DEVICE DESCRIPTION The DS38EP100 Power-Saver equalizer is a passive network circuit composed of resistive, capacitive, and inductive components (See Figure 4). A differential bridged T-network compensates for the transmission medium losses and minimizes medium-induced deterministic jitter with FR4 and cables. The equalizer attenuates low frequency signals and is a bandpass filter at the resonant frequency. The response is linear and symmetric. I/O TERMINATIONS The DS38EP100 I/O impedance is 100Ω differential. The equalizer is designed for 100Ω-balanced differential signals and is not intended for single-ended transmission. LINEAR COMPENSATION The unique linear compensation feature of the DS38EP100 combined with the tiny package allows maximum flexibility in placement. The equalizer can be placed anywhere in the data path and will provide the same compensation at the receiving circuit. (See Simplified Application Diagram) SYMMETRIC I/O STRUCTURES The symmetry of the passive equalization network allows bi-directional operation. Signals receive equal compensation regardless of the direction of data flow. (See Figure 4). Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 5 DS38EP100 SNLS278C – JULY 2007 – REVISED APRIL 2013 www.ti.com PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS AND NO CONNECT PADS The differential I/Os must have a controlled differential impedance of 100Ω. It is preferable to route all differential lines exclusively on one layer of the board. The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. Differential signals should be routed away from other signals and noise sources on the printed circuit board. Pin 2, Pin 5, and the center DAP have to be left as a no connect. Therefore, do not connect the landing pads of these pins to the power or ground plane. See AN-1187 (SNOA401) for additional information on the WSON package. 0.5 0.5 0.4 0.4 2.5 Gbps 5 Gbps Unequalized 0.3 DJ (UI) DJ (UI) TYPICAL PERFORMANCE CHARACTERISTICS 3.8 Gbps 0.2 Equalized 0.1 0.3 Unequalized 0.2 1.5 Gbps 0.1 Equalized 0 0 10 20 30 40 50 0 60 0 10 FR4 LENGTH (in) Figure 5. Residual Deterministic Jitter vs. FR4 Length 1 20 30 40 50 60 FR4 LENGTH (in) Figure 6. Residual Deterministic Jitter vs. FR4 Length 1 Unequalized 0.8 0.8 EYE HEIGHT (V) EYE HEIGHT (V) Unequalized 0.6 3.8 Gbps 0.4 5 Gbps 0.2 0 10 20 30 40 50 1.5 Gbps 0.4 60 FR4 LENGTH (in) 0 Equalized 0 10 20 30 40 50 60 FR4 LENGTH (in) Figure 7. Eye Height vs. FR4 Length 6 2.5 Gbps 0.2 Equalized 0 0.6 Figure 8. Eye Height vs. FR4 Length Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 DS38EP100 www.ti.com SNLS278C – JULY 2007 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Typical Eye Diagrams — Includes Transmitter Setup, Interconnect, and Device Total Jitter Figure 9. Unequalized Signal (40in FR4, 2.5Gbps, PRBS7) Figure 10. Equalized Signal (40in FR4, 2.5Gbps, PRBS7) Figure 11. Equalized Signal (Zoom) (40in FR4, 2.5Gbps, PRBS7) Figure 12. Unequalized Signal (40in FR4, 3.125Gbps, PRBS7) Figure 13. Equalized Signal (40in FR4, 3.125Gbps, PRBS7) Figure 14. Equalized Signal (Zoom) (40in FR4, 3.125Gbps, PRBS7) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 7 DS38EP100 SNLS278C – JULY 2007 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 8 Figure 15. Unequalized Signal (40in FR4, 3.8Gbps, PRBS7) Figure 16. Equalized Signal (40in FR4, 3.8Gbps, PRBS7) Figure 17. Equalized Signal (Zoom) (40in FR4, 3.8Gbps, PRBS7) Figure 18. Unequalized Signal (30in FR4, 4.25Gbps, PRBS7) Figure 19. Equalized Signal (30in FR4, 4.25Gbps, PRBS7) Figure 20. Equalized Signal (Zoom) (30in FR4, 4.25Gbps, PRBS7) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 DS38EP100 www.ti.com SNLS278C – JULY 2007 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Figure 21. Unequalized Signal (30in FR4, 5Gbps, PRBS7) Figure 22. Equalized Signal (30in FR4, 5Gbps, PRBS7) Figure 23. Equalized Signal (Zoom) (30in FR4, 5Gbps, PRBS7) Figure 24. Unequalized Signal (34in Tyco XAUI Backplane, 3.125Gbps, PRBS7) Figure 25. Equalized Signal (34in Tyco XAUI Backplane, 3.125Gbps, PRBS7) Figure 26. Equalized Signal (Zoom) (34in Tyco XAUI Backplane, 3.125Gbps, PRBS7) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 9 DS38EP100 SNLS278C – JULY 2007 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10 Figure 27. Unequalized Signal (5m 28AWG HDMI Cable, 3.4Gbps, PRBS7) Figure 28. Equalized Signal (5m 28AWG HDMI Cable, 3.4Gbps, PRBS7) Figure 29. Equalized Signal (Zoom) (5m 28AWG HDMI Cable, 3.4Gbps, PRBS7) Figure 30. Unequalized Signal (10m 26AWG HDMI Cable, 2.25Gbps, PRBS7) Figure 31. Equalized Signal (10m 26AWG HDMI Cable, 2.25Gbps, PRBS7) Figure 32. Equalized Signal (Zoom) (10m 26AWG HDMI Cable, 2.25Gbps, PRBS7) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 DS38EP100 www.ti.com SNLS278C – JULY 2007 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Figure 33. Unequalized Signal (10m 24AWG PCIe Cable, 2.5Gbps, PRBS7) Figure 34. Equalized Signal (10m 24AWG PCIe Cable, 2.5Gbps, PRBS7) Figure 35. Equalized Signal (Zoom) (10m 24AWG PCIe Cable, 2.5Gbps, PRBS7) Figure 36. Unequalized Signal (10m 24AWG PCIe Cable, 5Gbps, PRBS7) Figure 37. Equalized Signal (10m 24AWG PCIe Cable, 5Gbps, PRBS7) Figure 38. Equalized Signal (Zoom) (10m 24AWG PCIe Cable, 5Gbps, PRBS7) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 11 DS38EP100 SNLS278C – JULY 2007 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: DS38EP100 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS38EP100SD/NOPB ACTIVE WSON NGF 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 38S (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of