DS90C032
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SNLS094D – JUNE 1998 – REVISED APRIL 2013
DS90C032 LVDS Quad CMOS Differential Line Receiver
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FEATURES
DESCRIPTION
•
•
TheDS90C032 is a quad CMOS differential line
receiver designed for applications requiring ultra low
power dissipation and high data rates. The device
supports data rates in excess of 155.5 Mbps (77.7
MHz) and uses Low Voltage Differential Signaling
(LVDS) technology.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
>155.5 Mbps (77.7 MHz) switching rates
Accepts small swing (350 mV) differential
signal levels
Ultra low power dissipation
600 ps maximum differential skew (5V, 25°C)
6.0 ns maximum propagation delay
Industrial operating temperature range
Military operating temperature range option
Available in surface mount packaging (SOIC)
and (LCCC)
Pin compatible with DS26C32A, MB570
(PECL), and 41LF (PECL)
Supports OPEN input fail-safe
Supports short and terminated input fail-safe
with the addition of external failsafe biasing
Compatible with IEEE 1596.3 SCI LVDS
standard
Conforms to ANSI/TIA/EIA-644 LVDS standard
Available to Standard Microcircuit Drawing
(SMD) 5962-95834
TheDS90C032 accepts low voltage (350 mV)
differential input signals and translates them to
CMOS (TTL compatible) output levels. The receiver
supports a TRI-STATE function that may be used to
multiplex outputs. The receiver also supports OPEN,
shorted, and terminated (100Ω) input Failsafe with
the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
TheDS90C032
and
companion
line
driver
(DS90C031) provide a new alternative to high power
pseudo-ECL devices for high speed point-to-point
interface applications.
Connection Diagram
Dual-In-Line
Figure 1. See Package Number D (R-PDSO-G16)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
DS90C032
SNLS094D – JUNE 1998 – REVISED APRIL 2013
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Functional Diagram and Truth Table
Receiver
ENABLES
OUTPUT
ROUT
EN
EN*
RIN+ − RIN−
L
H
X
Z
VID ≥ 0.1V
H
VID ≤ −0.1V
L
Full Fail-safe
OPEN/SHORT or
Terminated
H
All other combinations of
ENABLE inputs
2
INPUTS
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
−0.3V to +6V
Supply Voltage (VCC)
Input Voltage (RIN+, RIN−)
−0.3V to (VCC +0.3V)
Enable Input Voltage
−0.3V to (VCC +0.3V)
(EN, EN*)
−0.3V to (VCC +0.3V)
Output Voltage (ROUT)
Maximum Package Power Dissipation at +25°C
D Package
1025 mW
NAJ Package
1830 mW
Derate D Package
8.2 mW/°C above +25°C
Derate NAJ Package
12.2 mW/°C above +25°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range Soldering (4 seconds)
+260°C
Maximum Junction Temperature (DS90C032T)
+150°C
Maximum Junction Temperature (DS90C032E)
+175°C
ESD Ratings
≥ 3500V
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0 Ω, 200 pF)
(1)
(2)
≥ 250V
"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
Recommended Operating Conditions (1) (2)
Min
Typ
Max
Units
Supply Voltage (VCC)
+4.5
+5.0
+5.5
V
Receiver Input Voltage
GND
Operating Free Air Temperature (TA)
(1)
(2)
2.4
V
DS90C032T
−40
+25
+85
°C
DS90C032E
−55
+25
+125
°C
"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
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Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
Symbol
Parameter
Conditions
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
IIN
Input Current
VCM = +1.2V
VIN = +2.4V
Pin
Min
RIN+,
RIN−
−100
VCC = 5.5V
VIN = 0V
VOH
IOH = −0.4 mA, VID = +200 mV
Output High Voltage
IOH = −0.4 mA, Input
terminated
ROUT
DS90C032T
VOL
Output Low Voltage
IOL = 2 mA, VID = −200 mV
IOS
Output Short Circuit Current
Enabled, VOUT = 0V
IOZ
Output TRI-STATE Current
Disabled, VOUT = 0V or VCC
VIH
Input High Voltage
VIL
Input Low Voltage
II
Input Current
VCL
Input Clamp Voltage
ICL = −18 mA
ICC
No Load Supply Current, Receivers
Enabled
EN, EN* = VCC or GND, Inputs DS90C032T
Open
DS90C032E
ICCZ
(1)
(1)
EN,
EN*
No Load Supply Current, Receivers
Disabled
Typ
Max
Units
+100
mV
mV
−10
±1
+10
µA
−10
±1
+10
µA
3.8
4.9
V
3.8
4.9
V
0.07
0.3
V
−15
−60
−100
mA
−10
±1
+10
µA
2.0
V
−10
±1
−1.5
−0.8
VCC
0.8
V
+10
µA
V
3.5
10
mA
3.5
11
mA
EN, EN* = 2.4 or 0.5, Inputs Open
3.7
11
mA
EN = GND, EN* = VCC, Inputs
Open
DS90C032T
3.5
10
mA
DS90C032E
3.5
11
mA
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
Switching Characteristics
VCC = +5.0V, TA = +25°C, DS90C032T (1) (2) (3) (4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1.5
3.40
5.0
ns
1.5
3.48
5.0
ns
0
80
600
ps
0
0.6
1.0
ns
0.5
2.0
ns
0.5
2.0
ns
10
15
ns
10
15
ns
Enable Time Z to High
4
10
ns
Enable Time Z to Low
4
10
ns
tPHLD
Differential Propagation Delay High to Low
tPLHD
Differential Propagation Delay Low to High
tSKD
Differential Skew |tPHLD − tPLHD|
tSK1
Channel-to-Channel Skew
tTLH
Rise Time
tTHL
Fall Time
tPHZ
Disable Time High to Z
tPLZ
Disable Time Low to Z
tPZH
tPZL
(1)
(2)
(3)
(4)
4
CL = 5 pF,
VID = 200 mV,
See Figure 2 and Figure 3
(3)
RL = 2 kΩ,
CL = 10 pF,
See Figure 4 and Figure 5
All typical values are given for: VCC = +5.0V, TA = +25°C.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns
for EN or EN*.
Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
CL includes probe and jig capacitance.
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Switching Characteristics
VCC = +5.0V ± 10%, TA = −40°C to +85°C, DS90C032T (1) (2) (3) (4) (5)
Symbol
Parameter
tPHLD
Differential Propagation Delay High to Low
tPLHD
Differential Propagation Delay Low to High
tSKD
Differential Skew |tPHLD − tPLHD|
tSK1
Channel-to-Channel Skew
Conditions
CL = 5 pF,
VID = 200 mV,
See Figure 2 and Figure 3
(3)
Min
Typ
Max
Units
1.0
3.40
6.0
ns
1.0
3.48
6.0
ns
0
0.08
1.2
ns
0
0.6
1.5
ns
(4)
tSK2
Chip to Chip Skew
5.0
ns
tTLH
Rise Time
0.5
2.5
ns
tTHL
Fall Time
0.5
2.5
ns
tPHZ
Disable Time High to Z
10
20
ns
tPLZ
Disable Time Low to Z
10
20
ns
tPZH
Enable Time Z to High
4
15
ns
tPZL
Enable Time Z to Low
4
15
ns
(1)
(2)
(3)
(4)
(5)
RL = 2 kΩ,
CL = 10 pF,
See Figure 4 and Figure 5
All typical values are given for: VCC = +5.0V, TA = +25°C.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns
for EN or EN*.
Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
CL includes probe and jig capacitance.
Switching Characteristics
VCC = +5.0V ± 10%, TA = −55°C to +125°C, DS90C032E (1) (2) (3) (4) (5) (6)
Symbol
Parameter
Min
Typ
Max
Units
1.0
3.40
8.0
ns
1.0
3.48
8.0
ns
0
0.08
3.0
ns
0
0.6
3.0
ns
7.0
ns
10
20
ns
10
20
ns
Enable Time Z to High
4
20
ns
Enable Time Z to Low
4
20
ns
tPHLD
Differential Propagation Delay High to Low
tPLHD
Differential Propagation Delay Low to High
tSKD
Differential Skew |tPHLD − tPLHD|
tSK1
Channel-to-Channel Skew
tSK2
Chip to Chip Skew
tPHZ
Disable Time High to Z
tPLZ
Disable Time Low to Z
tPZH
tPZL
(1)
(2)
(3)
(4)
(5)
(6)
Conditions
CL = 20 pF,
VID = 200 mV,
See Figure 2 and Figure 3
(3)
(4)
RL = 2 kΩ,
CL = 10 pF,
See Figure 4 and Figure 5
All typical values are given for: VCC = +5.0V, TA = +25°C.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns
for EN or EN*.
Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
CL includes probe and jig capacitance.
For DS90C032E propagation delay measurements are from 0V on the input waveform to the 50% point on the output (ROUT).
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Parameter Measurement Information
Figure 2. Receiver Propagation Delay and Transition Time Test Circuit
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
CL includes load and test jig capacitance.
S1 = VCC for tPZL and tPLZ measurements.
S1 = GND for tPZH and tPHZ measurements.
Figure 4. Receiver TRI-STATE Delay Test Circuit
Figure 5. Receiver TRI-STATE Delay Waveforms
6
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TYPICAL APPLICATION
Figure 6. Point-to-Point Application
APPLICATIONS INFORMATION
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 6. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of mid-stream connectors, cable stubs, and other impedance discontinuities as well as ground
shifting, noise margin limits, and total termination loading must be taken into account.
The DS90C032 differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V commonmode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The
driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be
the result of a ground potential difference between the driver's ground reference and the receiver's ground
reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins
should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground),
exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages.
Receiver Fail-Safe
The LVDS receiver is a high-gain high-speed device that amplifies a small differential signal (20mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source or sink a small amount of current, providing failsafe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver inputs.
1. Open Input Pins. TheDS90C032 is a quad receiver device, and if an application requires only 1, 2, or 3
receivers, the unused channel inputs should be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high-value pullup and pulldown resistors to set the output
to a HIGH state. This internal circuitry ensures a HIGH stable output state for open inputs.
2. Terminated Input. TheDS90C032 requires external failsafe biasing for terminated input failsafe.
Terminated input failsafe is the case of a receiver that has a 100Ω termination across its inputs and the
driver is in the following situations. Unplugged from the bus, or the driver output is in TRI-STATE or in poweroff condition. The use of external biasing resistors provide a small bias to set the differential input voltage
while the line is un-driven, and therefore the receiver output will be in HIGH state. If the driver is removed
from the bus but the cable is still present and floating, the unplugged cable can become a floating antenna
that can pick up noise. The LVDS receiver is designed to detect very small amplitude and width signals and
recover them to standard logic levels. Thus, if the cable picks up more than 10mV of differential noise, the
receiver may respond. To insure that any noise is seen as common-mode and not differential, a balanced
interconnect and twisted pair cables is recommended, as they help to ensure that noise is coupled common
to both lines and rejected by the receivers.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of the device (1.2V ±1V). It is only supported with inputs shorted
and no external common-mode voltage applied.
4. Operation in environment with greater than 10mV differential noise.
TI recommends external failsafe biasing on its LVDS receivers for a number of system level and signal
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quality reasons. First, only an application that requires failsafe biasing needs to employ it. Second, the
amount of failsafe biasing is now an application design parameter and can be custom tailored for the specific
application. In applications in low noise environments, they may choose to use a very small bias if any. For
applications with less balanced interconnects and/or in high noise environments they may choose to boost
failsafe further. TIs LVDS Owner’s Manual provides detailed calculations for selecting the proper failsafe
biasing resistors. Third, the common-mode voltage is biased by the resistors during the un-driven state. This
is selected to be close to the nominal driver offset voltage (VOS). Thus when switching between driven and
un-driven states, the common-mode modulation on the bus is held to a minimum.
For additional Failsafe Biasing information, please refer to Application Note AN-1194 (SNLA051) for more
detail.
The footprint of the DS90C032 is the same as the industry standard 26LS32 Quad Differential (RS-422)
Receiver.
Pin Descriptions
8
Pin No. (SOIC)
Name
Description
2, 6, 10, 14
RIN+
Non-inverting receiver input pin
1, 7, 9, 15
RIN−
Inverting receiver input pin
3, 5, 11, 13
ROUT
Receiver output pin
4
EN
Active high enable pin, OR-ed with EN*
12
EN*
Active low enable pin, OR-ed with EN
16
VCC
Power supply pin, +5V ± 10%
8
GND
Ground pin
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Typical Performance Characteristics
Output High Voltage vs
Power Supply Voltage
Output High Voltage vs
Ambient Temperature
5.5
TA = 25 °C
VID = 200 mV
VOH ± Output High Voltage (V)
VOH ± Output High Voltage (V)
6
5
4
4.5
4.75
5
5.25
VCC = 5V
VID = 200 mV
5
4.5
±40
5.5
VCC ± Power Supply Voltage (V)
±15
35
60
85
TA ± Ambient Temperature (°C)
Figure 7.
Figure 8.
Output Low Voltage vs
Power Supply Voltage
Output Low Voltage vs
Ambient Temperature
200
200
TA = 25°C
VID = ±200 mV
VOL ± Output Low Voltage (mV)
VOL ± Output Low Voltage (mV)
10
100
VCC = 5V
VID = ±200 mV
100
0
4.5
4.75
5
5.5
5.25
VCC ± Power Supply Voltage (V)
Figure 9.
0
±40
±15
10
35
60
85
TA ± Ambient Temperature (°C)
Figure 10.
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Typical Performance Characteristics (continued)
Output Short Circuit Current
vs Ambient Temperature
±100
IOS ± Output Short Circuit Current (mA)
IOS ± Output Short Circuit Current (mA)
Output Short Circuit Current
vs Power Supply Voltage
TA = 25°C
VOUT = 0V
±80
±60
±40
±20
0
4.5
4.75
5
5.25
±100
VCC = 5V
VOUT = 0V
±80
±60
±40
±20
0
±40
5.5
3
Differential Propagation Delay
vs
Power Supply Voltage
Differential Propagation Delay
vs Ambient Temperature
TA = 25°C
Freq = 65 MHz
VID = 200 mV
CL = 5 pF
tPHLD
2
1
4.75
5
5.5
5.25
VCC ± Power Supply Voltage (V)
Figure 13.
10
60
Figure 12.
tPLHD
4.5
35
85
TA ± Ambient Temperature (°C)
5
4
10
Figure 11.
tPLHD, tPHLD ± Differential Propagation Delay (ns)
tPLHD, tPHLD ± Differential Propagation Delay (ns)
VCC ± Power Supply Voltage (V)
±15
5
VCC = 5V
Freq = 65 MHz
VID = 200 mV
CL = 5 pF
4
tPLHD
3
tPHLD
2
1
±40
±15
10
35
60
85
TA ± Ambient Temperature (°C)
Figure 14.
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Typical Performance Characteristics (continued)
Differential Skew vs
Power Supply Voltage
Differential Skew vs
Ambient Temperature
1
TA = 25°C
Freq = 65 MHz
VID = 200 mV
CL = 5 pF
0.8
tSKD ± Differential Skew (ns)
tSKD ± Differential Skew (ns)
1
0.6
0.4
0.2
0
4.5
4.75
5
0.8
0.6
0.4
0.2
0
±40
5.5
5.25
VCC = 5V
Freq = 65 MHz
VID = 200 mV
CL = 5 pF
±15
35
60
85
TA ± Ambient Temperature (°C)
VCC ± Power Supply Voltage (V)
Figure 15.
Figure 16.
Transition Time vs
Power Supply Voltage
Transition Time vs
Ambient Temperature
1
1
TA = 25°C
Freq = 65 MHz
tTLH, tTHL ± Transition Time (ns)
tTLH, tTHL ± Transition Time (ns)
10
0.8
tTLH
0.6
tTHL
0.4
0.2
VCC = 5V
Freq = 65 MHz
0.8
0.6
tTHL
0.4
tTLH
0.2
0
0
4.5
4.75
5
5.5
5.25
VCC ± Power Supply Voltage (V)
Figure 17.
±40
±15
10
35
60
85
TA ± Ambient Temperature (°C)
Figure 18.
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DS90C032TM
NRND
SOIC
D
16
48
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
-40 to 85
DS90C032TM
DS90C032TM/NOPB
ACTIVE
SOIC
D
16
48
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS90C032TM
DS90C032TMX
NRND
SOIC
D
16
2500
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
-40 to 85
DS90C032TM
DS90C032TMX/NOPB
ACTIVE
SOIC
D
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
DS90C032TM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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