DS90CR483A, DS90CR484A
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SNLS291A – APRIL 2008 – REVISED APRIL 2013
DS90CR483A / DS90CR484A 48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz
Check for Samples: DS90CR483A, DS90CR484A
FEATURES
1
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Up to 5.38 Gbits/sec Bandwidth
33 MHz to 112 MHz Input Clock Support
LVDS SER/DES Reduces Cable and Connector
Size
Pre-emphasis Reduces Cable Loading Effects
DC Balance Data Transmission Provided by
Transmitter Reduces ISI Distortion
Cable Deskew of +/−1 LVDS Data Bit Time (up
to 80 MHz Clock Rate)
5V Tolerant TxIN and Control Input Pins
Flow Through Pinout for Easy PCB Design
+3.3V Supply Voltage
Transmitter Rejects Cycle-to-Cycle Jitter
Conforms to ANSI/TIA/EIA-644-1995 LVDS
Standard
Both Devices are Available in 100 Lead TQFP
Package
DESCRIPTION
The DS90CR483A transmitter converts 48 bits of
CMOS/TTL data into eight LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a ninth LVDS link. Every cycle of the
transmit clock 48 bits of input data are sampled and
transmitted. The DS90CR484A receiver converts the
LVDS data streams back into 48 bits of CMOS/TTL
data. At a transmit clock frequency of 112MHz, 48
bits of TTL data are transmitted at a rate of 672Mbps
per LVDS data channel. Using a 112MHz clock, the
data throughput is 5.38Gbit/s (672Mbytes/s).
The multiplexing of data lines provides a substantial
cable reduction. Long distance parallel single-ended
buses typically require a ground wire per active signal
(and have very limited noise rejection capability).
Thus, for a 48-bit wide data and one clock, up to 98
conductors are required. With this Channel Link
chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This
provides an 80% reduction in cable width, which
provides a system cost savings, reduces connector
physical size and cost, and reduces shielding
requirements due to the cables' smaller form factor.
The 48 CMOS/TTL inputs can support a variety of
signal combinations. For example, 6 8-bit words or 5
9-bit (byte + parity) and 3 controls.
The DS90CR483A/DS90CR484A chipset is improved
over prior generations of Channel Link devices and
offers higher bandwidth support and longer cable
drive with three areas of enhancement. To increase
bandwidth, the maximum clock rate is increased to
112 MHz and 8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user
selectable pre-emphasis feature that provides
additional output current during transitions to
counteract cable loading effects. Optional DC
balancing on a cycle-to-cycle basis, is also provided
to reduce ISI (Inter-Symbol Interference). With preemphasis and DC balancing, a low distortion eyepattern is provided at the receiver end of the cable. A
cable deskew capability has been added to deskew
long cables of pair-to-pair skew of up to +/−1 LVDS
data bit time (up to 80 MHz Clock Rate). These three
enhancements allow cables 5+ meters in length to be
driven.
The chipset is an ideal means to solve EMI and cable
size problems associated with wide, high speed TTL
interfaces.
For more details, please refer to the Applications
Information section of this datasheet.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
DS90CR483A, DS90CR484A
SNLS291A – APRIL 2008 – REVISED APRIL 2013
www.ti.com
Generalized Block Diagrams
Generalized Transmitter Block Diagram
Generalized Receiver Block Diagram
2
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR483A DS90CR484A
DS90CR483A, DS90CR484A
www.ti.com
SNLS291A – APRIL 2008 – REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
−0.3V to +4V
Supply Voltage (VCC)
−0.3V to +5.5V
CMOS/TTL Input Voltage
LVCMOS/TTL Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage
−0.3V to +3.6V
LVDS Driver Output Voltage
−0.3V to +3.6V
LVDS Output Short Circuit Duration
Continuous
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 4 sec.)
100L TQFP
Maximum Package Power Dissipation Capacity @ 25°C 100
TQFP Package
DS90CR483ANEZ
Package Derating
DS90CR483A
ESD Rating
DS90CR484A
(1)
(2)
+260°C
2.3W
DS90CR484ANEZ
2.3W
DS90CR483ANEZ
18.1mW/°C above +25°C
DS90CR484ANEZ
18.1mW/°C above +25°C
(HBM, 1.5kΩ, 100pF)
> 6 kV
(EIAJ, 0Ω, 200pF)
> 300 V
(HBM, 1.5kΩ, 100pF)
> 2 kV
(EIAJ, 0Ω, 200pF)
> 200 V
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Min
Nom
Max
Units
Supply Voltage (VCC)
3.0
3.3
3.6
V
Operating Free Air Temperature (TA)
−10
+25
+70
°C
2.4
V
100
mVp-p
112
MHz
Receiver Input Range
0
Supply Noise Voltage
Input Clock (TX)
33
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR483A DS90CR484A
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DS90CR483A, DS90CR484A
SNLS291A – APRIL 2008 – REVISED APRIL 2013
www.ti.com
Electrical Characteristics (1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ (2)
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VIL
Low Level Input Voltage
GND
VOH
High Level Output Voltage IOH = −0.4 mA
VOL
Low Level Output Voltage
IOL = 2 mA
VCL
Input Clamp Voltage
ICL = −18 mA
IIN
Input Current
VIN = 0.4V, 2.5V or VCC
IOH = −2mA
IOS
Output Short Circuit
Current
2.7
3.3
2.7
2.85
−15
VIN = GND
V
0.8
V
V
V
0.1
0.3
V
−0.79
−1.5
V
+1.8
+15
µA
−120
mA
450
mV
35
mV
0
VOUT = 0V
µA
LVDS DRIVER DC SPECIFICATIONS
|VOD|
Differential Output Voltage RL = 100Ω
ΔVOD
Change in VOD between
Complimentary Output
States
VOS
Offset Voltage
ΔVOS
Change in VOS between
Complimentary Output
States
IOS
Output Short Circuit
Current
VOUT = 0V, RL = 100Ω
IOZ
Output TRI-STATE
Current
PD = 0V, VOUT = 0V or VCC
250
1.125
345
1.25
1.375
V
35
mV
−3.5
−5
mA
±1
±10
µA
+100
mV
LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Input High
Threshold
VTL
Differential Input Low
Threshold
IIN
Input Current
VCM = +1.2V
−100
mV
VIN = +2.4V, VCC = 3.6V
±10
µA
VIN = 0V, VCC = 3.6V
±10
µA
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply
Current
Worst Case
ICCTZ
Transmitter Supply
Current
Power Down
RL = 100Ω, CL = 5 pF,
BAL = High,
Worst Case Pattern
(Figure 1 Figure 2)
f = 33 MHz
91.4
140
mA
f = 66 MHz
106
160
mA
f = 112 MHz
155
210
mA
5
50
µA
f = 33 MHz
125
150
mA
f = 66 MHz
200
210
mA
f = 112 MHz
250
280
mA
20
100
µA
PD = Low
Driver Outputs in TRI-STATE during power down Mode
RECEIVER SUPPLY CURRENT
ICCRW
ICCRZ
(1)
(2)
4
Receiver Supply Current
Worst Case
Receiver Supply Current
Power Down
CL = 8 pF, BAL = High,
Worst Case Pattern
See (Figure 1 Figure 3)
PD = Low
Receiver Outputs stay low during power down mode.
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VTH, VTL, VOD and ΔVOD).
Typical values are given for VCC = 3.3V and T A = +25°C.
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR483A DS90CR484A
DS90CR483A, DS90CR484A
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SNLS291A – APRIL 2008 – REVISED APRIL 2013
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Units
TCIT
TxCLK In Transition Time (Figure 4)
1.0
2.0
3.0
ns
TCIP High
TxCLK In Period, PLLSEL = High Gear (Figure 5)
8.928
T
26.3
ns
TCIP Low
TxCLK In Period, PLLSEL = Low Gear (Figure 5)
25
T
30.3
ns
TCIH
TxCLK In High Time (Figure 5)
0.35T
0.5T
0.65T
ns
TCIL
TxCLK In Low Time (Figure 5)
0.35T
0.5T
0.65T
ns
TXIT
TxIN Transition Time
6.0
ns
1.5
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
LLHT
LHLT
Typ
Max
Units
LVDS Low-to-High Transition Time, (Figure 2),
PRE = 0.75V (disabled)
Parameter
Min
0.14
0.7
ns
LVDS Low-to-High Transition Time, (Figure 2),
PRE = Vcc (max)
0.11
0.6
ns
LVDS High-to-Low Transition Time, (Figure 2),
PRE = 0.75V (disabled)
0.16
0.8
ns
LVDS High-to-Low Transition Time, (Figure 2),
PRE = Vcc (max)
0.11
0.7
ns
TBIT
Transmitter Bit Width
TPPOS
Transmitter Pulse Positions Normalized
TJCC
Transmitter Jitter - Cycle-to-Cycle (1)
TCCS
TxOUT Channel to Channel Skew
40
TSTC
TxIN Setup to TxCLK IN, (Figure 5)
2.5
THTC
TxIN Hold to TxCLK IN, (Figure 5)
0
TPDL
Transmitter Propagation Delay - Latency, (Figure 7)
TPLLS
TPDD
(1)
1/7 TCIP
f = 33 to 70 MHz
−250
f = 70 to 112 MHz
−200
1.5(TCIP)+3.72
ns
0
+250
ps
0
+200
ps
50
100
ps
ps
ns
ns
1.5(TCIP)+4.4
1.5(TCIP)+6.24
ns
Transmitter Phase Lock Loop Set, (Figure 9)
10
ms
Transmitter Powerdown Delay, (Figure 11)
100
ns
TJCC is a function of input clock quality and also PLLVCC noise. At 112MHz operation, with a +/−300ps input impulse at a 2us rate,
TJCC has been measured to be in the 70-80ps range (B
DS90CR483AVJDX/NOPB
ACTIVE
TQFP
NEZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 70
DS90CR483AVJD
>B
DS90CR484AVJD/NOPB
ACTIVE
TQFP
NEZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 70
DS90CR484AVJD
>B
DS90CR484AVJDX/NOPB
ACTIVE
TQFP
NEZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 70
DS90CR484AVJD
>B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of