DS90LV001TM

DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DS90LV001 800 Mbps LVDS Buffer Check for Samples: DS90LV001 FEATURES DESCRIPTION • • • • • • The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like. 1 2 • • • • Single +3.3 V Supply LVDS Receiver Inputs Accept LVPECL Signals TRI-STATE Outputs Receiver Input Threshold < ±100 mV Fast Propagation Delay of 1.4 ns (Typ) Low Jitter 800 Mbps Fully Differential Data Path 100 ps (Typ) of pk-pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps Compatible with ANSI/TIA/EIA-644-A LVDS Standard 8 pin SOIC and Space Saving (70%) WSON Package Industrial Temperature Range The DS90LV001, available in the WSON package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance. A wide input DS90LV001 to LVPECL as well device to also translator. dynamic range will allow the receive differential signals from as LVDS sources. This will allow the fill the role of an LVPECL-LVDS An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE. The DS90LV001 is offered in two package options, an 8 pin WSON and SOIC. Connection Diagram Figure 1. Top View See Package Number D (R-PDSO-G8), NGK0008A Block Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2013, Texas Instruments Incorporated DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) −0.3V to (VCC + 0.3V) LVCMOS/LVTTL Input Voltage (EN) LVDS Receiver Input Voltage (IN+, IN−) −0.3V to +4V LVDS Driver Output Voltage (OUT+, OUT−) −0.3V to +4V LVDS Output Short Circuit Current Continuous Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.) +260°C D Package Maximum Package Power Dissipation at 25°C ESD Ratings (1) 726 mW Derate D Package 5.8 mW/°C above +25°C NGK Package 2.44 W Derate NGK Package 19.49 mW/°C above +25°C (HBM, 1.5kΩ, 100pF) ≥2.5kV (EIAJ, 0Ω, 200pF) ≥250V “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Recommended Operating Conditions Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature 2 Min Typ Max Units 3.0 3.3 3.6 V 0 −40 Submit Documentation Feedback +25 VCC V +85 °C Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (1) (2) Symbol Parameter Conditions Min Typ Max Units V LVCMOS/LVTTL DC SPECIFICATIONS (EN) VIH High Level Input Voltage 2.0 VCC VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = 3.6V or 2.0V, VCC = 3.6V +20 μA IIL Low Level Input Current VIN = GND or 0.8V, VCC = 3.6V VCL Input Clamp Voltage ICL = −18 mA +7 ±1 ±10 μA −0.6 −1.5 V 325 450 mV 20 mV 1.375 V 20 mV ±10 μA LVDS OUTPUT DC SPECIFICATIONS (OUT) VOD Differential Output Voltage ΔVOD Change in Magnitude of VOD for Complimentary Output States RL = 100Ω Figure 2 and Figure 3 250 VOS Offset Voltage ΔVOS Change in Magnitude of VOS for Complimentary Output States IOZ Output TRI-STATE Current EN = 0V, VOUT = VCC or GND IOFF Power-Off Leakage Current VCC = 0V, VOUT = 3.6V or GND ±1 ±10 μA IOS Output Short Circuit Current (3) EN = VCC, VOUT+ and VOUT− = 0V −16 −24 mA IOSD Differential Output Short Circuit Current (3) EN = VCC, VOD = 0V −7 −12 mA 0 +100 mV RL = 100Ω Figure 2 1.080 1.19 ±1 LVDS RECEIVER DC SPECIFICATIONS (IN) VTH Differential Input High Threshold VTL Differential Input Low Threshold VCM = +0.05V, +1.2V or +3.25V VCMR Common Mode Voltage Range VID = 100mV, VCC = 3.3V IIN Input Current VIN = +3.0V −100 0.05 Change in Magnitude of IIN mV 3.25 V ±1 ±10 μA ±1 ±10 μA 1 6 μA VIN = 0V 1 6 μA VCC = 3.6V or 0V VIN = 0V ΔIIN 0 VIN = +3.0V VCC = 3.6V or 0V SUPPLY CURRENT ICCD Total Supply Current EN = VCC, RL = 100Ω, CL = 5 pF 47 70 mA ICCZ TRI-STATE Supply Current EN = 0V 22 35 mA (1) (2) (3) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 3 DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (1) Symbol Parameter Conditions Typ Max Units 1.0 1.4 2.0 ns 1.0 1.4 2.0 ns tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD1 Pulse Skew |tPLHD − tPHLD| (2) (3) 20 200 ps tSKD3 Part to Part Skew (2) (4) 0 60 ps tSKD4 Part to Part Skew (2) (5) tLHT Rise Time (2) tHLT Fall Time (2) tPHZ Disable Time (Active High to Z) tPLZ Disable Time (Active Low to Z) tPZH Enable Time (Z to Active High) tPZL Enable Time (Z to Active Low) tDJ LVDS Data Jitter, Deterministic (Peak-to-Peak) (6) VID = 300mV; PRBS = 223 − 1 data; VCM = 1.2V at 800Mbps (NRZ) tRJ LVDS Clock Jitter, Random (6) VID = 300mV; VCM = 1.2V at 400MHz clock (1) (2) (3) (4) (5) (6) 4 RL = 100Ω, CL = 5pF Figure 4 and Figure 5 Min RL = 100Ω, CL = 5pF Figure 4 and Figure 6 RL = 100Ω, CL = 5pF Figure 7 and Figure 8 400 ps 200 320 450 ps 200 310 450 ps 3 25 ns 3 25 ns 25 45 ns 25 45 ns 100 135 ps 2.2 3.5 ps All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and temperature) range. tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. The parameters are ensured by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test equipment setup: HP8133A (pattern pulse generator), 5 feet of RG142B cable with DUT test board and HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with RG142B cable exhibit a tDJ = 21ps and tRJ = 1.8ps. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DC Test Circuits Figure 2. Differential Driver DC Test Circuit Figure 3. Differential Driver Full Load DC Test Circuit AC Test Circuits and Timing Diagrams Figure 4. LVDS Output Load Figure 5. Propagation Delay Low-to-High and High-to-Low Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 5 DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Figure 6. LVDS Output Transition Time Figure 7. TRI-STATE Delay Test Circuit Figure 8. Output active to TRI-STATE and TRI-STATE to active output time 6 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DS90LV001 Pin Descriptions (SOIC and WSON) Pin Name Pin # Input/Output Description GND 1 P Ground IN − 2 I Inverting receiver LVDS input pin IN+ 3 I Non-inverting receiver LVDS input pin NC 4 VCC 5 P No Connect Power Supply, 3.3V ± 0.3V. OUT+ 6 O Non-inverting driver LVDS output pin OUT - 7 O Inverting driver LVDS output pin EN 8 I Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in TRISTATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL levels. DAP NA NA Die Attach Pad or DAP (WSON Package only). The DAP is NOT connected to the device GND nor any other pin. It is still recommended to connect the DAP to a GND plane of a PCB for enhenced heat dissipation. TYPICAL APPLICATIONS Backplane Stub-Hider Application Cable Repeater Application Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 7 DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION MODE OF OPERATION The DS90LV001 can be used as a "stub-hider." In many systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on the individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns and PCB designs often make it difficult to make the stubs as short as the designer would like. The DS90LV001, available in the WSON package, can improve system performance by allowing the receiver to be placed very close to the main transmission line either on the backplane itself or very close to the connector on the card. Longer traces to the LVDS receiver may be placed after the DS90LV001. This very small WSON package is a 75% space savings over the SOIC package. INPUT FAILSAFE The receiver inputs of the DS90LV001 do not have internal failsafe biasing. For point-to-point and multidrop applications with a single source, failsafe biasing may not be required. When the driver is off, the link is in-active. If failsafe biasing is required, this can be accomplished with external high value resistors. Using the equations in the LVDS Owner"s Manual Chapter 4, the IN+ should be pull to VCC (3.3V) with 20kΩ and the IN− should be pull to GND with 12kΩ. This provides a slight positive differential bias, and sets a known HIGH state on the link with a minimum amount of distortion. PCB LAYOUT AND POWER SYSTEM BYPASS Circuit board layout and stack-up for the DS90LV001 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the DS90LV001 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. 8 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. There are more common practices which should be followed when designing PCBs for LVDS signaling. Please see application note AN-1108 for guidelines. In addition, application note AN-1187 has additional information specifically related to WSON recommendations. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 9 DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Typical Performance Curves 10 Output High Voltage vs Power Supply Voltage Output Low Voltage vs Power Supply Voltage Figure 9. Figure 10. Output Short Circuit Current vs Power Supply Voltage Differential Output Short Circuit Current vs Power Supply Voltage Figure 11. Figure 12. Output TRI-STATE Current vs Power Supply Voltage Offset Voltage vs Power Supply Voltage Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 Typical Performance Curves (continued) Differential Output Voltage vs Power Supply Voltage Differential Output Voltage vs Load Resistor Figure 15. Figure 16. Power Supply Current vs Frequency Power Supply Current vs Power Supply Voltage Figure 17. Figure 18. TRI-STATE Power Supply Current vs Power Supply Voltage Differential Transition Voltage vs Power Supply Voltage Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 11 DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Typical Performance Curves (continued) 12 Differential Propagation Delay vs Power Supply Voltage Differential Propagation Delay vs Ambient Temperature Figure 21. Figure 22. Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature Figure 23. Figure 24. Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 Typical Performance Curves (continued) Differential Propagation Delay vs Differential Input Voltage Differential Propagation Delay vs Common-Mode Voltage Figure 27. Figure 28. Peak-to-Peak Output Jitter at VCM = 0.4V vs Differential Input Voltage Peak-to-Peak Output Jitter at VCM = 2.9V vs Differential Input Voltage Figure 29. Figure 30. Peak-to-Peak Output Jitter at VCM = 1.2V vs Differential Input Voltage Peak-to-Peak Output Jitter at VCM = 1.2V vs Ambient Temperature Figure 31. Figure 32. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 13 DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision D (April 2013) to Revision E • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV001 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS90LV001TLD NRND WSON NGK 8 1000 Non-RoHS & Green Call TI Level-1-235C-UNLIM -40 to 85 001 DS90LV001TLD/NOPB ACTIVE WSON NGK 8 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 001 DS90LV001TLDX/NOPB ACTIVE WSON NGK 8 4500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 001 DS90LV001TM NRND SOIC D 8 95 Non-RoHS & Green Call TI Level-1-235C-UNLIM -40 to 85 LV001 TM DS90LV001TM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LV001 TM DS90LV001TMX NRND SOIC D 8 2500 Non-RoHS & Green Call TI Level-1-235C-UNLIM -40 to 85 LV001 TM DS90LV001TMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LV001 TM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of