DS90LV110TMTC

DS90LV110T www.ti.com SNOS522I – JANUARY 2001 – REVISED APRIL 2013 DS90LV110T 1 to 10 LVDS Data/Clock Distributor Check for Samples: DS90LV110T FEATURES DESCRIPTION • • DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-topoint interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz. 1 2 • • • • • • • • • • Low jitter 800 Mbps fully differential data path 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps Single +3.3 V Supply Less than 413 mW (typ) total power dissipation Balanced output impedance Output channel-to-channel skew is 35ps (typ) Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load. LVDS receiver inputs accept LVPECL signals Fast propagation delay of 2.8 ns (typ) Receiver input threshold < ±100 mV 28 lead TSSOP package Conforms to ANSI/TIA/EIA-644 LVDS standard The DS90LV110 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATE by use of the enable pin. For more details, please refer to the APPLICATION INFORMATION section of this datasheet. Connection Diagram Order Number DS90LV110TMTC PW0028A Package 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2013, Texas Instruments Incorporated DS90LV110T SNOS522I – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Block Diagram Figure 1. Block Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VDD-VSS) −0.3V to (VCC + 0.3V) LVCMOS/LVTTL Input Voltage (EN) LVDS Receiver Input Voltage (IN+, IN−) −0.3V to +4V LVDS Driver Output Voltage (OUT+, OUT−) −0.3V to +4V Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering, 4 sec.) +260°C Maximum Package Power Dissipation at 25°C 28 Lead TSSOP 2.115 W Package Derating 28 Lead TSSOP 16.9 mW/°C above +25°C θJA (4-Layer, 2 oz. Cu, JEDEC) 28 Lead TSSOP 59.1 °C/Watt ESD Rating: (HBM, 1.5kΩ, 100pF) > 4 kV (EIAJ, 0Ω, 200pF) (1) 2 > 250 V “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be verified. They are not meant to imply that the device should be operated at these limits. Electrical Characteristics provides conditions for actual device operation. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T DS90LV110T www.ti.com SNOS522I – JANUARY 2001 – REVISED APRIL 2013 Recommended Operating Conditions Supply Voltage (VDD - VSS) Min Typ Max Units 3.0 3.3 3.6 V Receiver Input Voltage 0 Operating Free Air Temperature -40 +25 VDD V +85 °C Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ (1) Max Units V LVCMOS/LVTTL DC SPECIFICATIONS (EN) VIH High Level Input Voltage 2.0 VDD VIL Low Level Input Voltage VSS 0.8 V IIH High Level Input Current VIN = 3.6V or 2.0V; VDD = 3.6V ±20 μA IIL Low Level Input Current VIN = 0V or 0.8V; VDD = 3.6V ±7 ±20 μA VCL Input Clamp Voltage ICL = −18 mA −0.8 −1.5 V mV ±7 LVDS OUTPUT DC SPECIFICATIONS (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10) VOD Differential Output Voltage RL = 100Ω 250 320 450 ΔVOD Change in VOD between Complimentary Output States RL = 100Ω, VDD = 3.3V, TA = 25°C 260 320 425 mV 35 |mV| VOS Offset Voltage 1.375 V ΔVOS Change in VOS between Complimentary Output States IOZ Output TRI-STATE Current EN = 0V, VOUT = VDD or GND 35 |mV| ±1 ±10 μA IOFF Power-Off Leakage Current ISA,ISB Output Short Circuit Current VDD = 0V; VOUT = 3.6V or GND ±1 ±10 μA VOUT+ OR VOUT− = 0V or VDD 12 24 |mA| ISAB Both Outputs Shorted VOUT+ = VOUT− 6 12 |mA| 0 +100 mV (2) 1.125 (3) 1.25 LVDS RECEIVER DC SPECIFICATIONS (IN) VTH Differential Input High Threshold VTL Differential Input Low Threshold VCM = +0.05V or +1.2V or +3.25V, VDD = 3.3V −100 VCMR Common Mode Voltage Range VID = 100mV, VDD = 3.3V 0.05 IIN Input Current VIN = +3.0V, VDD = 3.6V or 0V VIN = 0V, VDD = 3.6V or 0V 0 mV 3.25 V ±1 ±10 μA ±1 ±10 μA RL = 100Ω, CL = 5 pF, 400 MHz, EN = High 125 195 mA No Load, 400 MHz, EN = High 80 125 mA EN = Low 15 29 mA SUPPLY CURRENT ICCD Total Supply Current ICCZ TRI-STATE Supply Current (1) (2) (3) All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. VOS is defined as (VOH + VOL) / 2. Only one output can be shorted at a time. Don't exceed the package absolute maximum rating. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T 3 DS90LV110T SNOS522I – JANUARY 2001 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 390 550 ps 390 550 ps TLHT Output Low-to-High Transition Time, 20% to 80%, Figure 5 (1) THLT Output High-to-Low Transition Time, 80% to 20%, Figure 5 (1) TDJ LVDS Data Jitter, Deterministic (Peak-toPeak) (2) TRJ LVDS Clock Jitter, Random TPLHD Propagation Low to High Delay, Figure 6 2.2 2.8 TPHLD Propagation High to Low Delay, Figure 6 2.2 TSKEW Pulse Skew |TPLHD - TPHLD| TCCS Output Channel-to-Channel Skew, Figure 7 TPHZ Disable Time (Active to TRI-STATE) High to Z, Figure 2 TPLZ Disable Time (Active to TRI-STATE) Low to Z, Figure 2 TPZH Enable Time (TRI-STATE to Active) Z to High, Figure 2 TPZL Enable Time (TRI-STATE to Active) Z to Low, Figure 2 7.0 (1) (2) (2) VID = 300mV; PRBS=223-1 data; VCM = 1.2V at 800 Mbps (NRZ) 145 ps VID = 300mV; VCM = 1.2V at 400 MHz clock 2.8 ps (1) (1) 3.6 ns 2.8 3.6 ns 20 340 ps 35 91 ps 3.0 6.0 ns 1.8 6.0 ns 10.0 23.0 ns 23.0 ns The parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and temperature) range. The measurement used the following equipment and test setup: HP8133A pattern/pulse generator), 5 feet of RG-142 cable with DUT test board and HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with the RG-142 cable exhibit a TDJ = 26ps and TRJ = 1.3 ps AC TIMING DIAGRAMS Figure 2. Output active to TRI-STATE and TRI-STATE to active output time 4 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T DS90LV110T www.ti.com SNOS522I – JANUARY 2001 – REVISED APRIL 2013 Figure 3. LVDS Driver TRI-STATE Circuit Figure 4. LVDS Output Load Figure 5. LVDS Output Transition Time Figure 6. Propagation Delay Low-to-High and High-to-Low Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T 5 DS90LV110T SNOS522I – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Figure 7. Output 1 to 10 Channel-to-Channel Skew APPLICATION INFORMATION Input Fail-Safe The receiver inputs of the DS90LV110 do not have internal fail-safe biasing. For point-to-point and multi-drop applications with a single source, fail-safe biasing may not be required. When the driver is off, the link is inactive. If fail-safe biasing is required, this can be accomplished with external high value resistors. The IN+ should be pull to Vcc with 10kΩ and the IN− should be pull to Gnd with 10kΩ. This provides a slight positive differential bias, and sets a known HIGH state on the link with a minimum amount of distortion. See AN-1194(SNLA051) for additional information. LVDS Inputs Termination The LVDS Receiver input must have a 100Ω termination resistor placed as close as possible across the input pins. Unused Control Inputs The EN control input pin has internal pull down device. If left open, the 10 outputs will default to TRI-STATE. Expanding the Number of Output Ports To expand the number of output ports, more than one DS90LV110 can be used. Total propagation delay through the devices should be considered to determine the maximum expansion. Adding more devices will increase the output jitter due to each pass. PCB Layout and Power System Bypass Circuit board layout and stack-up for the DS90LV110 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the DS90LV110 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. 6 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T DS90LV110T www.ti.com SNOS522I – JANUARY 2001 – REVISED APRIL 2013 The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. There are more common practices which should be followed when designing PCBs for LVDS signaling. Please see Application Note: AN-1108(SNLA008) for additional information. Multi-Drop Applications Figure 8. Multi-Drop Applications Point-to-Point Distribution Applications Figure 9. Point-to-Point Distribution Applications Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T 7 DS90LV110T SNOS522I – JANUARY 2001 – REVISED APRIL 2013 www.ti.com For applications operating at data rate greater than 400Mbps, a point-to-point distribution application should be used. This improves signal quality compared to multi-drop applications due to no stub PCB trace loading. The only load is a receiver at the far end of the transmission line. Point-to-point distribution applications will have a wider LVDS bus lines, but data rate can increase well above 400Mbps due to the improved signal quality. PIN DESCRIPTIONS Pin Name # of Pin Input/Output Description IN+ 1 I Non-inverting LVDS input IN - 1 I Inverting LVDS input OUT+ 10 O Non-inverting LVDS Output OUT - 10 O Inverting LVDS Output EN 1 I This pin has an internal pull-down when left open. A logic low on the Enable puts all the LVDS outputs into TRI-STATE and reduces the supply current. VSS 3 P Ground (all ground pins must be tied to the same supply) VDD 2 P Power Supply (all power pins must be tied to the same supply) INPUT INTERFACING The DS90LV110 accepts differential signals and allow simple AC or DC coupling. With a wide common mode range, the DS90LV110 can be DC-coupled with all common differential drivers (that is, LVPECL, LVDS, CML). Figure 10, Figure 11, and Figure 12 illustrate typical DC-coupled interface to common differential drivers. LVDS Driver DS90LV110 Receiver 100: Differential T-Line OUT+ IN+ 100: IN- OUT- Figure 10. Typical LVDS Driver DC-Coupled Interface to DS90LV110 Input CML3.3V or CML2.5V Driver VCC 50: DS90LV110 Receiver 50: OUT+ 100: Differential T-Line IN+ 100: IN- OUT- Figure 11. Typical CML Driver DC-Coupled Interface to DS90LV110 Input 8 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T DS90LV110T www.ti.com SNOS522I – JANUARY 2001 – REVISED APRIL 2013 LVPECL Driver OUT+ 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 12. Typical LVPECL Driver DC-Coupled Interface to DS90LV110 Input OUTPUT INTERFACING The DS90LV110 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to most common differential receivers. Figure 13 illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. DS90LV110 Driver OUT+ Differential Receiver 100: Differential T-Line IN+ CML or LVPECL or LVDS 100: IN- OUT- Figure 13. Typical DS90LV110 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T 9 DS90LV110T SNOS522I – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics 10 Output Voltage (VOD) vs. Resistive Load (RL) Peak-to-Peak Output Jitter at VCM = +0.4V vs. VID Peak-to-Peak Output Jitter at VCM = +1.2V vs. VID Peak-to-Peak Output Jitter at VCM = +2.9V vs. VID Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T DS90LV110T www.ti.com SNOS522I – JANUARY 2001 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision H (April 2013) to Revision I • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 1 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: DS90LV110T 11 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS90LV110TMTC NRND TSSOP PW 28 48 Non-RoHS & Green Call TI Level-3-235C-168 HR -40 to 85 DS90LV 110TMTC DS90LV110TMTC/NOPB ACTIVE TSSOP PW 28 48 RoHS & Green SN Level-3-260C-168 HR -40 to 85 DS90LV 110TMTC DS90LV110TMTCX/NOPB ACTIVE TSSOP PW 28 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 DS90LV 110TMTC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of