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DS90UB913A-Q1
ZHCSEW6F – MAY 2013 – REVISED JANUARY 2020
DS90UB913A-Q1 25MHz 至 100MHz 10/12 位 FPD-Link III 串行器
1 特性
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1
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3 说明
符合AEC-Q100 车规认证
– 器件温度等级 2：环境工作温度范围为 -40℃ 至
+105℃
25MHz 至 100MHz 输入像素时钟支持
可编程数据有效载荷：
– 10 位有效载荷，高达 100MHz
– 12 位有效载荷，高达 75MHz
连续低延迟双向控制接口通道，带有 I2C 接口，支
持 400kHz 传输速率
嵌入式时钟具有 DC 均衡编码，用于支持 AC 耦合
互连
可驱动长达 15m 的同轴电缆或 20m 的屏蔽双绞线
电缆
稳健的同轴电缆供电 (PoC) 运行
4 个专用通用输入/输出
串行器上提供 1.8V、2.8V 或 3.3V 兼容并行输入
1.8V 单电源
符合 ISO 10605 和 IEC 61000-4-2 ESD 标准
小尺寸串行器 (5mm × 5mm)
•
•
凭借德州仪器 (TI) 的嵌入式时钟技术，可在单一差分
对上进行透明的全双工通信，从而运载不对称的双向控
制通道信息。这个单个串行数据流通过消除并行数据与
时钟路径间的偏差，简化了印刷电路板 (PCB) 走线和
电缆上的宽数据总线传输。这样，通过限制数据路径的
宽度，大大节省了系统成本，相应地减少了 PCB 层
数、电缆宽度以及连接器尺寸和引脚数量。内部 DC
均衡编码/解码用于支持 AC 耦合互连。
器件信息(1)
器件型号
DS90UB913A-Q1
2 应用
•
DS90UB913A-Q1 器件提供一个具有高速正向通道和
双向控制通道的 FPD-Link III 接口，用来实现单一同轴
电缆或差分对上的数据传输。DS90UB913A-Q1 器件
的高速正向通道和双向控制通道数据路径上均包含差分
信令。串行器/解串器对主要用于电子控制单元 (ECU)
中成像器与视频处理器的连接。该器件非常适用于驱动
需要高达 12 位像素深度、2 个同步信号以及双向控制
通道总线的视频数据。
汽车
– 环视系统 (SVS)
– 前置摄像头 (FC)
– 后视摄像头 (RVC)
– 传感器融合
– 驾驶员监视摄像头 (DMS)
– 远距卫星雷达、ToF 和激光雷达传感器
安防和监控
机器视觉 应用
封装
WQFN (32)
封装尺寸（标称值）
5.00mm × 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
Parallel
Data In
10 or 12
Parallel
Data Out
10 or 12
FPD-Link III
2
Megapixel
Imager/Sensor
HSYNC,
VSYNC
2
DS90UB913AQ1
4
GPO
2
Bidirectional
Control Bus
Serializer
Bidirectional
Control Channel
DS90UB914AQ1
HSYNC,
VSYNC
4
DSP, FPGA/
µ-Processor/
ECU
GPIO
2
Deserializer
Bidirectional
Control Bus
Copyright © 2016, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS443
DS90UB913A-Q1
ZHCSEW6F – MAY 2013 – REVISED JANUARY 2020
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
5
5
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Recommended Serializer Timing For PCLK .......... 11
AC Timing Specifications (SCL, SDA) - I2CCompatible ............................................................... 12
7.8 Bidirectional Control Bus DC Timing Specifications
(SCL, SDA) - I2C-Compatible ................................. 12
7.9 Timing Diagrams ..................................................... 13
7.10 Serializer Switching Characteristics...................... 15
7.11 Typical Characteristics .......................................... 16
8
Detailed Description ............................................ 17
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
17
17
18
21
26
30
Application and Implementation ........................ 37
9.1 Application Information............................................ 37
9.2 Typical Applications ................................................ 39
10 Power Supply Recommendations ..................... 43
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 45
12 器件和文档支持 ..................................................... 47
12.1
12.2
12.3
12.4
12.5
12.6
文档支持................................................................
接收文档更新通知 .................................................
支持资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
47
47
47
47
47
47
13 机械、封装和可订购信息 ....................................... 47
4 修订历史记录
Changes from Revision E (September 2018) to Revision F
Page
•
Clarified GPO2 description by removing statement about leaving pin open if unused ......................................................... 6
•
Added register 0x27[5] to register map ............................................................................................................................... 35
•
Fixed missing register 0x29 typo ......................................................................................................................................... 36
•
Added maximum power up timing constraint between VDD_n and PDB ........................................................................... 37
•
Added recommended software programming steps if VDD_n to PDB maximum power up timing constraint can not
be met .................................................................................................................................................................................. 38
Changes from Revision D (October 2016) to Revision E
Page
•
Added recommendation to ensure GPO2 is low when PDB goes high ................................................................................ 6
•
Added Power Over Coax supply noise to the recommended operating conditions table ...................................................... 8
•
Clarified PCLK clock frequency range and added external clock input frequency range ...................................................... 8
•
Added strap pin input current specification for MODE and IDX pins .................................................................................... 9
•
Updated TJIT1 PCLK input jitter in the external oscillator mode ........................................................................................... 11
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Added clarification on MODE pin description in PCLK from imager mode ......................................................................... 22
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Updated pullup and pulldown resistor to R1 and R2 in MODE pin configuration diagram ................................................... 22
•
Updated the MODE setting values to ratio ........................................................................................................................... 23
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Updated pullup and pulldown resistor for IDX to R3 and R4 in the diagram......................................................................... 28
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Updated IDX setting values to ratio ..................................................................................................................................... 28
•
Updated register "TYPE" column per legend ...................................................................................................................... 30
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Added type and default value to the reserved register bits that were missing this information .......................................... 30
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Added that register 0x00[7:1] does not auto update IDX strapped address ....................................................................... 30
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Added description for 0x05 bits 1 and 0 (TX_MODE_12b and TX_MODE_10b) ............................................................... 32
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Clarified description on PDB pin usage during power up .................................................................................................... 37
2
版权 © 2013–2020, Texas Instruments Incorporated
DS90UB913A-Q1
www.ti.com.cn
ZHCSEW6F – MAY 2013 – REVISED JANUARY 2020
•
Added paragraph to explain setting registers if GPO2 state is not determined when PDB goes high ............................... 37
•
Added GPO2 to suggested power-up sequencing diagram ................................................................................................ 37
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Added timing constraint for PDB to GPO2 delay ................................................................................................................ 38
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Revised coax connection diagram to include pulldown resistor for GPO2 ......................................................................... 40
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Revised STP connection diagram to include pulldown resistor for GPO2 .......................................................................... 42
Changes from Revision C (April 2016) to Revision D
Page
•
Added back channel line rate = 5.5 MHz as test condition; also added footnote for clarification between MHz and
Mbps distinction. ................................................................................................................................................................... 10
•
Removed 'ns' unit from specifications referencing period in units of T. ............................................................................... 11
•
Updated test condition specs for jitter bandwidth regarding tJIT0, tJIT1, and tJIT2. .................................................................. 11
•
Added input external oscillator frequency range for pin/freq. .............................................................................................. 11
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Added parameter for typical external oscillator frequency stability. ..................................................................................... 11
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Added test conditions to tJIND, tJINR, and tJINT. ....................................................................................................................... 15
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Added DOUT± as measured output pins for jitter parameters. ............................................................................................ 15
•
Added note (6) for "Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter
transfer from serializer input". .............................................................................................................................................. 15
•
Added jitter tolerance curve for typical system IJT configuration with DS90UB913A linked to DS90UB914A. .................. 16
•
Added device functional mode table for external oscillator operation with example XCLKIN = 48MHz. ............................ 21
Changes from Revision B (December 2014) to Revision C
Page
•
将文档拆分为有关器件 DS90UB913A-Q1 和 DS90UB914A-Q1 的两个独立文档 .................................................................. 1
•
已修改汽车 特性 .................................................................................................................................................................... 1
•
Updated pin description for DIN to include active/inactive outputs corresponding to MODE setting..................................... 5
•
Added pin description to GPO pins to leave open if unused. ................................................................................................ 6
•
Changed Air Discharge ESD Rating (IEC61000-4-2: RD = 330 Ω, CS = 150 pF) to minimum ±25000 V. .......................... 7
•
Added RTV text to Thermal Information table ........................................................................................................................ 8
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Added GPO[3:0] typical pin capacitances. ............................................................................................................................ 9
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Changed Differential Output Voltage minimum specification. ............................................................................................... 9
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Changed Single-Ended Output Voltage minimum specification............................................................................................. 9
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Added Back Channel Differential Input Voltage minimum specification............................................................................... 10
•
Added Back Channel Single-Ended Input Voltage minimum specification. ......................................................................... 10
•
Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=100 MHz, 10-bit mode to typical
value of 65 mA; value is currently 54 mA............................................................................................................................. 10
•
Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=75 MHz, 12-bit high freq mode to
typical value of 64 mA; value is currently 54 mA.................................................................................................................. 10
•
Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=50 MHz, 12-bit low freq mode to
typical value of 63 mA; value is currently 54 mA. ............................................................................................................... 10
•
Updated frequency ranges for MODE settings and also revised with correct maximum clock periods. Added footnote
and nominal clock period to be in terms of 'T'. (5) .................................................................................................................. 11
•
Deleted Revised jitter freq. test conditions to be > f/20 and also updated typical values for tjit0and tjit2. ............................. 11
•
Updated VOL Output Low Level row with revised IOL currents and max VOL voltages, dependent upon VDDIO voltage. ...... 12
•
Updated Figure 2 title to state ‘“Worst-Case” Test Pattern for Power Consumption’. ......................................................... 13
•
Added footnote that states the following: “UI – Unit Interval is equivalent to one serialized data bit width. The UI
scales with PCLK frequency.” Add below calculations to footnote. 12-bit LF mode 1 UI = 1 / ( PCLK_Freq. x 28 ) 12bit HF mode 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 ) 10-bit mode 1 UI = 1 / ( PCLK_Freq. /2 x 28 ) ..................................... 15
•
Updated frequency requirements for 10-bit and 12-bit HF modes. 10-bit mode – 50 MHz to 100 MHz; 12-bit HF
版权 © 2013–2020, Texas Instruments Incorporated
3
DS90UB913A-Q1
ZHCSEW6F – MAY 2013 – REVISED JANUARY 2020
www.ti.com.cn
mode – 37.5 MHz to 75 MHz; 12-bit LF mode (no change) – 25 MHz to 50 MHz. ............................................................ 17
•
Updated register 0x01[1] default value to be “0”. ................................................................................................................. 30
•
Changed GPO0 Enable for 0x0D[4] to GPO1 Enable.......................................................................................................... 33
•
Added Inject Forward Channel Error Register 0x2D. ........................................................................................................... 36
•
Updated power up sequencing information and timing diagram. ........................................................................................ 37
•
Added description specifying that the voltage applied on VDDIO (1.8 V, 3.3 V) or VDD_n (1.8 V) should be at the input
pin – any board level DC drop should be compensated. .................................................................................................... 43
•
Added 913A EVM layout example image. ........................................................................................................................... 46
Changes from Revision A (June 2013) to Revision B
Page
•
已添加 数据表流程和版面布局，以符合全新 TI 标准。已添加以下部分：器件比较表；处理额定值；应用和实施；电
源相关建议；布局；器件和文档支持；机械、封装和订购信息............................................................................................... 1
•
Added additional thermal characteristics................................................................................................................................ 8
•
Changed typo in Vout test condition from RL=500Ω to RL=50Ω. .......................................................................................... 9
•
Changed Figure 6 to use VODp-p and to clarify difference between STP and Coax .............................................................. 14
•
Added Internal Oscillator section to Device Functional Modes ............................................................................................ 23
•
Added reference to Power over Coax Application report ..................................................................................................... 37
•
Added power up sequencing information and timing diagram. ............................................................................................ 37
4
Copyright © 2013–2020, Texas Instruments Incorporated
DS90UB913A-Q1
www.ti.com.cn
ZHCSEW6F – MAY 2013 – REVISED JANUARY 2020
5 Device Comparison Table
PART NUMBER
FPD-III FUNCTION
PACKAGE
TRANSMISSION MEDIA
PCLK FREQUENCY
DS90UB913Q-Q1
Serializer
WQFN RTV (32)
STP
10 to 100 MHz
DS90UB913A-Q1
Serializer
WQFN RTV (32)
Coax or STP
25 to 100 MHz
6 Pin Configuration and Functions
DIN[1]
16
15
14
13
12
11
10
VDDPLL
PDB
DIN[8]
DAP = GND
DS90UB913A-Q1
Serializer
2
3
4
5
6
7
VSYNC
PCLK
SCL
SDA
ID[x]
RES
8
MODE
1
HSYNC
32
26
VDDT
27
DOUT-
28
DOUT+
9
GPO[2]/
CLKOUT
DIN[2]
17
29
18
30
19
GPO[3]/
CLKIN
DIN[3]
DIN[0]
DIN[4]
20
25
21
VDDCML
VDDD
DIN[11]
22
GPO[0]
DIN[7]
DIN[10]
23
GPO[1]
DIN[6]
DIN[9]
24
31
VDDIO
DIN[5]
32-Pin WQFN
Package RTV
Top View
Pin Functions: DS90UB913A-Q1 Serializer
PIN
NAME
I/O
NO.
DESCRIPTION
LVCMOS PARALLEL INTERFACE
19,20,21,22,
23,24,26,27,
29,30,31,32
Inputs,
LVCMOS
w/ pulldown
Parallel Data Inputs. For 10-bit MODE, parallel inputs DIN[0:9] are active. DIN[10:11] are
inactive and should not be used. Any unused inputs (including DIN[10:11]) should be No
Connect. For 12-bit MODE (HF or LF), parallel inputs DIN[0:11] are active. Any unused
inputs should be No Connect.
1
Input,
LVCMOS
w/ pulldown
Horizontal SYNC Input. Note: HS transition restrictions: 1. 12-bit Low-Frequency mode: No
HS restrictions (raw) 2. 12-bit High-Frequency mode: No HS restrictions (raw) 3. 10-bit
mode: HS restricted to no more than one transition per 10 PCLK cycles. Leave open if
unused.
VSYNC
2
Input,
LVCMOS
w/ pulldown
Vertical SYNC Input. Note: VS transition restrictions: 1. 12-bit Low-Frequency mode: No VS
restrictions (raw) 2. 12-bit High-Frequency mode: No VS restrictions (raw) 3. 10-bit HighFrequency mode: VS restricted to no more than one transition per 10 PCLK cycles. Leave
open if unused.
PCLK
3
Input,
LVCMOS
w/ pulldown
Pixel Clock Input Pin. Strobe edge set by TRFB control register 0x03[0].
DIN[0:11]
HSYNC
Copyright © 2013–2020, Texas Instruments Incorporated
5
DS90UB913A-Q1
ZHCSEW6F – MAY 2013 – REVISED JANUARY 2020
www.ti.com.cn
Pin Functions: DS90UB913A-Q1 Serializer (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
GENERAL PURPOSE OUTPUT (GPO)
GPO[1:0]
GPO[2]/
CLKOUT
GPO[3]/
CLKIN
16,15
17
18
Output,
LVCMOS
General-purpose output pins can be configured as outputs; used to control and respond to
various commands. GPO[1:0] can be configured to be the outputs for input signals coming
from GPIO[1:0] pins on the Deserializer or can be configured to be outputs of the local
register on the Serializer. Leave open if unused.
Output,
LVCMOS
GPO[2] pin can be configured to be the output for input signal coming from the GPIO[2] pin
on the Deserializer or can be configured to be the output of the local register on the
Serializer. It can also be configured to be the output clock pin when the DS90UB913A-Q1
device is used in the External Oscillator mode. See Device Functional Modes section for a
detailed description of External Oscillator Mode. It is recommended to pull GPO2 to GND
with a minimum 40-kΩ resistor to ensure GPO2=LOW when PDB transitions from LOW to
HIGH.
GPO[3] can be configured to be the output for input signals coming from the GPIO[3] pin on
the Deserializer or can be configured to be the output of the local register setting on the
Input/Output,
Serializer. It can also be configured to be the input clock pin when the DS90UB913A-Q1
LVCMOS
Serializer is working with an external oscillator. See Device Functional Modes section for a
detailed description of External Oscillator Mode. Leave open if unused.
BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE
SCL
4
Input/Output, Clock line for the bidirectional control bus communication
Open Drain SCL requires an external pullup resistor to VDDIO.
SDA
5
Input/Output, Data line for the bidirectional control bus communication
Open Drain SDA requires an external pullup resistor to VDDIO.
MODE
8
Input, analog
ID[x]
6
Device ID Address Select
Input, analog The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor (RID) to
Ground and 10-kΩ pullup to 1.8 V rail. See Table 6.
Device Mode Select
Resistor (Rmode) to Ground and 10-kΩ pullup to 1.8 V rail. MODE pin on the Serializer can
be used to select whether the system is running off the PCLK from the imager or an external
oscillator. See details in Table 2.
CONTROL AND CONFIGURATION
PDB
9
Input,
LVCMOS
w/ pulldown
RES
7
Input,
LVCMOS
w/ pulldown
Power Down Mode Input Pin
PDB = H, Serializer is enabled and is ON.
PDB = L, Serializer is in Power Down mode. When the Serializer is in Power Down, the PLL
is shutdown, and IDD is minimized. Programmed control register data is NOT retained and
reset to default values.
Reserved
This pin MUST be tied LOW.
FPD–Link III INTERFACE
DOUT+
13
Input/Output, Non-inverting differential output, bidirectional control channel input. The interconnect must be
CML
AC Coupled with a 0.1-µF capacitor.
DOUT-
12
Inverting differential output, bidirectional control channel input. The interconnect must be AC
Input/Output, Coupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect, a
CML
0.047-µF AC coupling capacitor should be placed in series with a 50Ω resistor before
terminating to GND.
POWER AND GROUND (1)
VDDPLL
10
Power,
Analog
PLL Power, 1.8 V ±5%.
VDDT
11
Power,
Analog
Tx Analog Power, 1.8 V ±5%.
VDDCML
14
Power,
Analog
CML & Bidirectional Channel Driver Power, 1.8 V ±5%.
VDDD
28
Power,
Digital
Digital Power, 1.8 V ±5%.
VDDIO
25
Power,
Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.
VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%.
(1)
6
See Power-Up Requirements and PDB Pin.
Copyright © 2013–2020, Texas Instruments Incorporated
DS90UB913A-Q1
www.ti.com.cn
ZHCSEW6F – MAY 2013 – REVISED JANUARY 2020
Pin Functions: DS90UB913A-Q1 Serializer (continued)
PIN
NAME
NO.
VSS
DAP
I/O
Ground, DAP
DESCRIPTION
DAP must be grounded. DAP is the large metal contact at the bottom side, located at the
center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply Voltage – VDD_n (VDDPLL, VDDT, VDDCML, VDDD)
−0.3
2.5
V
Supply Voltage – VDDIO
−0.3
4.0
V
LVCMOS Input Voltage
−0.3
VDDIO + 0.3
V
CML Driver I/O Voltage – (VDD_n)
-0.3
VDD_n + 0.3
V
150
°C
150
°C
Junction Temperature
−65
Storage temperature range, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 3B
Charged device model (CDM), per AEC
Q100-011
CDM ESD Classification Level C6
V(ESD)
Electrostatic
discharge
(IEC 61000-4-2)
RD = 330 Ω, Cs = 150pF
(ISO10605)
RD = 330 Ω, Cs = 150/330 pF
RD = 2 KΩ, Cs = 150/330 pF
(1)
UNIT
±8000
Corner pins (1, 8, 9, 16, 17, 24,
25, 32)
±1000
Other pins
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±25000
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±7000
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±15000
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
±8000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
1.71
1.8
1.89
V
1.71
1.8
1.89
VDDIO= 3.3 V
3
3.3
3.6
VDDIO= 2.8 V
2.52
2.8
3.08
Supply Voltage (VDD_n)
VDDIO= 1.8 V
LVCMOS Supply Voltage
Supply Noise
(1)
(1)
VDD_n = 1.8 V
25
VDDIO = 1.8 V
25
VDDIO = 3.3 V
50
V
mVp-p
Supply noise testing was done with minimum capacitors (as shown on Figure 36, Figure 32 on the PCB. A sinusoidal signal is AC
coupled to the VDD_n (1.8 V) supply with amplitude = 25 mVp-p measured at the device VDD_n pins. Bit error rate testing of input to the
Ser and output of the Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the
other hand shows no error when the noise frequency is less than 750 kHz.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
Power-Over-Coax Supply
Noise
UNIT
10
mVp-p
ƒ = 1 KHz - 50 MHz
Measured differentially between DOUT+ and DOUT(coax mode only)
10
mVp-p
–40
10-bit mode
External Clock Input
Frequency to GPO3
MAX
ƒ = 30 Hz - 1 KHz, trise > 100 µs
Measured differentially between DOUT+ and DOUT–
(coax mode only)
Operating Free Air Temperature (TA)
PCLK Clock Frequency
NOM
25
105
°C
50
100
MHz
12-bit HF mode
37.5
75
MHz
12-bit LF mode
25
50
MHz
10-bit mode
25
50
MHz
12-bit HF mode
25
50
MHz
12-bit LF mode
25
50
MHz
7.4 Thermal Information
DS90UB913A-Q1
THERMAL METRIC (1)
RTV (WQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
34.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
8.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.4
°C/W
RθJB
Junction-to-board thermal resistance
23.4
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
8.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
7.5 Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 3.3 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 3 V to 3.6 V
2
VIN
V
VIL
Low Level Input
Voltage
VIN = 3 V to 3.6 V
GND
0.8
V
IIN
Input Current
VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V
–20
20
µA
VOH
High Level Output
Voltage
VDDIO = 3 V to 3.6 V, IOH = −4 mA
2.4
VDDIO
V
VOL
Low Level Output
Voltage
VDDIO = 3 V to 3.6 V, IOL = 4 mA
GND
0.4
V
IOS
Output Short Circuit
Current
VOUT = 0 V
Serializer
GPO Outputs
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDDIO
Serializer
GPO Outputs
(1)
(2)
(3)
8
±1
–15
–20
mA
20
µA
The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
verified.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD which are differential voltages.
Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
Copyright © 2013–2020, Texas Instruments Incorporated
DS90UB913A-Q1
www.ti.com.cn
ZHCSEW6F – MAY 2013 – REVISED JANUARY 2020
Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
CGPO
Pin Capacitance
TEST CONDITIONS
MIN
GPO [3:0]
TYP
MAX
1.5
UNIT
pF
LVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 1.71 V to 1.89 V
0.65 VIN
VIN
VIL
Low Level Input
Voltage
VIN = 1.71 V to 1.89 V
GND
0.35 VIN
IIN
Input Current
VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V
VOH
High Level Output
Voltage
VDDIO = 1.71 V to 1.89 V, IOH = −4 mA
VOL
Low Level Output
Voltage
VDDIO = 1.71 V to 1.89 V IOL = 4 mA
IOS
Output Short Circuit
Current
VOUT = 0 V
Serializer
GPO Outputs
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDDIO
Serializer
GPO Outputs
CGPO
Pin Capacitance
GPO [3:0]
IIN-STRAP
Strap pin input current VIN = 0 V to VDD_n
V
–20
±1
20
µA
VDDIO - 0.45
VDDIO
V
GND
0.45
V
–11
-20
mA
20
µA
1
µA
1.5
-1
pF
LVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 2.52 V to 3.08 V
0.7 VIN
VIN
VIL
Low Level Input
Voltage
VIN = 2.52 V to 3.08 V
GND
0.3 VIN
IIN
Input Current
VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V
VOH
High Level Output
Voltage
VDDIO = 2.52 V to 3.08 V, IOH = −4 mA
VOL
Low Level Output
Voltage
VDDIO =2.52 V to 3.08V IOL = 4 mA
IOS
Output Short Circuit
Current
VOUT = 0 V
Serializer
GPO Outputs
IOZ
TRI-STATE Output
Current
PDB = 0 V,
VOUT = 0 V or VDDIO
Serializer
GPO Outputs
CGPO
Pin Capacitance
GPO [3:0]
V
–20
±1
20
µA
VDDIO - 0.4
VDDIO
V
GND
0.4
V
–11
–20
mA
20
1.5
µA
pF
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
VOD
Differential Output
Voltage
RL = 100 Ω (Figure 6), Back Channel Disabled
640
824
VOUT
Single-Ended Output
Voltage
RL = 50 Ω (Figure 6), Back Channel Disabled
320
412
ΔVOD
Differential Output
Voltage Unbalance
RL = 100 Ω
VOS
Output Offset Voltage
RL = 100 Ω (Figure 6)
ΔVOS
Offset Voltage
Unbalance
RL = 100 Ω
IOS
Output Short Circuit
Current
DOUT+ = 0 V or DOUT– = 0 V
Differential Internal
Termination
Resistance
Differential across DOUT+ and DOUT–
Single-ended
Termination
Resistance
DOUT+ or DOUT–
RT
mV
1
50
VDD_n VOD/2
1
V
50
–26
80
100
mV
mV
mA
120
Ω
Copyright © 2013–2020, Texas Instruments Incorporated
40
50
60
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Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
VID-BC
VIN-BC
Back Channel
Differential Input
Voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
260
mV
130
mV
Back Channel Frequency = 5.5 MHz (4)
Back Channel SingleEnded Input Voltage
SERIALIZER SUPPLY CURRENT
Serializer (Tx)
RL = 100 Ω
VDD_n Supply Current WORST CASE pattern
(includes load current) (Figure 2)
IDDT
Serializer (Tx)
RL = 100 Ω
VDD_n Supply Current RANDOM PRBS-7
(includes load current) pattern
IDDT
IDDIOT
IDDTZ
IDDIOTZ
(4)
10
Serializer (Tx)
RL = 100 Ω
VDDIO Supply Current WORST CASE pattern
(includes load current) (Figure 2)
Serializer (Tx) Supply
Current Power Down
PDB = 0V; All other
LVCMOS Inputs = 0 V
Serializer (Tx) VDDIO
PDB = 0V; All other
Supply Current Power
LVCMOS Inputs = 0 V
Down
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 100 MHz, 10-bit
mode
Default Registers
61
80
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 75 MHz, 12-bit
high frequency mode
Default Registers
61
80
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 50 MHz, 12-bit
low frequency mode
Default Registers
61
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 100 MHz, 10-bit
mode
Default Registers
65
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 75 MHz, 12-bit
high frequency mode
Default Registers
64
VDD_n = 1.89 V
VDDIO = 3.6 V
f = 50 MHz, 12-bit
low frequency mode
Default Registers
63
VDDIO = 1.89 V
f = 75 MHz, 12-bit
high frequency mode
Default Registers
1.5
VDDIO = 3.6 V
f = 75 MHz, 12-bit
high frequency
mode Default
Registers
mA
mA
80
mA
3
mA
5
8
VDDIO=1.89 V
Default Registers
300
1000
µA
VDDIO = 3.6 V
Default Registers
300
1000
µA
VDDIO = 1.89 V
Default Registers
15
100
µA
VDDIO = 3.6 V
Default Registers
15
100
µA
The back channel frequency (MHz) listed is the frequency of the internal clock used to generate the encoded back channel data stream.
The data rate (Mbps) of the encoded back channel stream is the back channel frequency divided by 2.
Copyright © 2013–2020, Texas Instruments Incorporated
DS90UB913A-Q1
www.ti.com.cn
ZHCSEW6F – MAY 2013 – REVISED JANUARY 2020
7.6 Recommended Serializer Timing For PCLK (1)
(2)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN / FREQ
10-bit mode
50 MHz – 100 MHz
tTCP
Transmit Clock Period
12-bit high frequency mode
37.5 MHz - 75MHz
12-bit low frequency mode
25 MHz - 50MHz
MIN
NOM
MAX
10
T
20
ns
13.33
T
26.67
ns
20
T
40
ns
tTCIH
Transmit Clock
Input High Time
0.4T
0.5T
0.6T
tTCIL
Transmit Clock
Input Low Time
0.4T
0.5T
0.6T
0.05T
0.25T
0.3T
0.05T
0.25T
0.3T
0.05T
0.25T
0.3T
10-bit mode
50 MHz – 100 MHz
tCLKT
PCLK Input Transition Time 12-bit high frequency mode
(Figure 7)
37.5 MHz - 75MHz
12-bit low frequency mode
25 MHz - 50MHz
tJIT0
PCLK Input Jitter
(PCLK from imager
mode) (3)
LPF = ƒ/20, CDR PLL Loop BW
= ƒ/15, BER = 1E-10
tJIT1
PCLK Input Jitter
(External Oscillator
mode) (3)
LPF = ƒ/20, CDR PLL Loop BW
= ƒ/15, BER = 1E-10
tJIT2
External Oscillator Jitter (3)
LPF = ƒ/20, CDR PLL Loop BW
= ƒ/15, BER = 1E-10
ΔOSC
External Oscillator
Frequency Stability
(1)
(2)
(3)
(4)
(5)
ƒPCLK = 25 –
100 MHz (4)
ƒPCLK = 25 –
100 MHz (4)
0.3
UI
0.3
UI
1T
ƒOSC = 25 –
50 MHz (5)
ƒOSC = 25 –
50 MHz (5)
UNIT
±50
ppm
Recommended Input Timing Requirements are input specifications and not tested in production.
T is the period of the PCLK.
Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
ƒPCLK denotes input PCLK frequency to the device.
ƒOSC denotes input external oscillator frequency to the device (GPO3/CLKIN).
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7.7 AC Timing Specifications (SCL, SDA) - I2C-Compatible
Over recommended supply and temperature ranges unless otherwise specified. (Figure 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Standard Mode
100
kHz
Fast Mode
400
kHz
RECOMMENDED INPUT TIMING REQUIREMENTS
fSCL
SCL Clock Frequency
tLOW
SCL Low Period
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
tHIGH
SCL High Period
tHD:STA
Hold time for a start or a repeated start
condition
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Set Up time for a start or a repeated
start condition
Standard Mode
4.7
µs
Fast Mode
0.6
tSU:STA
tHD:DAT
tSU:DAT
Data Hold Time
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tBUF
Bus Free time between Stop and Start
tr
tf
SCL & SDA Rise Time
SCL & SDA Fall Time
µs
Standard Mode
0
3.45
µs
Fast Mode
0
900
ns
Standard Mode
250
ns
Fast Mode
100
ns
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
1000
ns
Fast Mode
300
ns
Standard Mode
300
ns
Fast Mode
300
ns
7.8 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible (1)
Over recommended supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VDDIO
V
RECOMMENDED INPUT TIMING REQUIREMENTS
VIH
Input High Level
SDA and SCL
0.7*VDDIO
VIL
Input Low Level
SDA and SCL
GND
VHY
Input Hysteresis
VOL
Output Low Level (2)
IIN
Input Current
tR
SDA Rise Time-READ
tF
SDA Fall Time-READ
CIN
(1)
(2)
12
0.3*VDDIO
>50
SDA, VDDIO = 1.8 V, IOL= 0.9 mA
0
0.36
SDA, VDDIO = 3.3 V, IOL= 1.6 mA
0
0.4
SDA or SCL, VIN= VDDIO OR GND
SDA, RPU = 10 kΩ, Cb ≤ 400 pF
(Figure 1)
SDA or SCL
−10
V
mV
10
V
µA
430
ns
20
ns
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