Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
DS90UB926Q-Q1
SNLS422D – JULY 2012 – REVISED AUGUST 2017
DS90UB926Q-Q1 5- to 85-MHz, 24-Bit Color FPD-Link III Deserializer With Bidirectional
Control Channel
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
– Device HBM ESD Classification Level 3B
– Device CDM ESD Classification Level C6
– Device MM ESD Classification Level M3
Bidirectional Control Interface Channel Interface
With I2C-Compatible Serial Control Bus
Supports High-Definition (720p) Digital Video
Format
RGB888 + VS, HS, DE and Synchronized I2S
Audio Supported
5- to 85-MHz PCLK Supported
Single 3.3-V Operation With 1.8-V or 3.3-V
Compatible LVCMOS I/O Interface
AC-Coupled STP Interconnect up to 10 Meters
Parallel LVCMOS Video Outputs
I2C-Compatible Serial Control Bus for
Configuration
DC-Balanced and Scrambled Data With
Embedded Clock
Adaptive Cable Equalization
Supports Repeater Application
@ SPEED Link BIST Mode and LOCK Status Pin
Image Enhancement (White Balance and
Dithering) and Internal Pattern Generation
EMI Minimization (SSCG and EPTO)
Low Power Modes Minimize Power Dissipation
Backward-Compatible With FPD-Link II
Automotive Display for Navigation
Rear Seat Entertainment Systems
Automotive Drive Assistance
Automotive Megapixel Camera Systems
3 Description
The DS90UB926Q-Q1 deserializer, in conjunction
with the DS90UB925Q-Q1 serializer, provides a
complete digital interface for concurrent transmission
of high-speed video, audio, and control data for
automotive display and image-sensing applications.
This chipset translates a parallel RGB video interface
into a single-pair high-speed serialized interface. The
serial bus scheme, FPD-Link III, supports full duplex
of high-speed forward data transmission and lowspeed backchannel communication over a single
differential link. Consolidation of video data and
control over a single differential pair reduces the
interconnect size and weight, while also eliminating
skew issues and simplifying system design.
The DS90UB926Q-Q1 deserializer recovers the RGB
data, three video control signals, and four
synchronized I2S audio signals. The device extracts
the clock from a high-speed serial stream. An output
LOCK pin provides the link status if the incoming data
stream is locked, without the use of a training
sequence or special SYNC patterns, as well as a
reference clock.
Device Information(1)
PART NUMBER
DS90UB926Q-Q1
PACKAGE
WQFN (60)
BODY SIZE (NOM)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Display System Diagram
VDDIO
VDD33
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RGB Digital Display Interface
VDDIO
VDD33
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
DOUT+
SCL
SDA
IDx
RIN+
DOUT-
RIN-
100: STP Cable
DS90UB925Q
Serializer
PDB
I2S AUDIO
(STEREO)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
3
MODE_SEL
INTB
DAP
PDB
OSS_SEL
OEN
MODE_SEL
DS90UB926Q
Deserializer
SCL
SDA
IDx
LOCK
PASS
3
INTB_IN
RGB Display
720p
24-bit color depth
I2S AUDIO
(STEREO)
MCLK
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB926Q-Q1
SNLS422D – JULY 2012 – REVISED AUGUST 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
1
1
1
2
4
5
8
Absolute Maximum Ratings ..................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 9
DC Electrical Characteristics .................................... 9
AC Electrical Characteristics................................... 11
DC and AC Serial Control Bus Characteristics....... 12
Timing Requirements .............................................. 12
Timing Requirements for the Serial Control Bus .... 13
Switching Characteristics ...................................... 13
Timing Diagrams ................................................... 14
Typical Characteristics .......................................... 17
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2
8.3
8.4
8.5
8.6
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
18
18
31
35
36
Application and Implementation ........................ 48
9.1 Application Information............................................ 48
9.2 Typical Application .................................................. 49
10 Power Supply Recommendations ..................... 51
10.1 Power Up Requirements and PDB Pin ................. 51
11 Layout................................................................... 52
11.1 Layout Guidelines ................................................. 52
11.2 Layout Examples................................................... 54
12 Device and Documentation Support ................. 55
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
55
55
13 Mechanical, Packaging, and Orderable
Information ........................................................... 55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (February 2017) to Revision D
Page
•
Reverted all previous MLCK content changes made in Revision C back to Revision B........................................................ 1
•
Deleted the disable I2S jitter cleaner note.............................................................................................................................. 6
Changes from Revision B (January 2015) to Revision C
Page
•
Changed pin 60 from MCLK to RES2 ................................................................................................................................... 5
•
Changed MCLK to RES2 ....................................................................................................................................................... 6
•
Added note to disable I2S jitter cleaner ................................................................................................................................ 6
•
Changed MCLK to RES2 ....................................................................................................................................................... 6
•
Deleted reference to MCLK in this section ............................................................................................................................ 9
•
Deleted reference to MCLK in this section .......................................................................................................................... 13
•
Deleted reference to MCLK .................................................................................................................................................. 28
•
Changed MCLK section ....................................................................................................................................................... 28
•
Changed MCLK columns of Audio Interface Frequencies table ......................................................................................... 28
•
Changed the values in columns 2 through 5 in Configuration Select (MODE_SEL) table................................................... 32
•
Changed the values in columns 2 to 5 in Serial Control Bus Addresses for IDx table ........................................................ 35
•
Changed register reference to MCLK .................................................................................................................................. 45
•
Changed Typical Display System Diagram (removed reference to MCLK) ........................................................................ 49
•
Changed wording of Power Up Requirements and PDB Pin subsection and added Power-Up Sequence graphic............ 51
2
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
DS90UB926Q-Q1
www.ti.com
SNLS422D – JULY 2012 – REVISED AUGUST 2017
Changes from Revision A (April 2013) to Revision B
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
Changes from Original (July 2012) to Revision A
Page
•
Corrected typo in table “DC and AC Serial Control Bus Characteristics” from VDDIO to VDD33, added “Note: BIST
is not available in backwards compatible mode.”, added Recommended FRC settings table, changed entire layout
of Data Sheet to TI format, added to Absolute Maximum Rating section, note (3): The maximum limit (VDDIO +0.3V)
does not apply to the PDB pin during the transition to the power down state (PDB transitioning from HIGH to LOW),
deleted derate from Maximum Power Dissipation Capacity at 25°C...................................................................................... 4
•
"Note: BIST is not available in backwards compatible mode." ............................................................................................. 26
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
3
DS90UB926Q-Q1
SNLS422D – JULY 2012 – REVISED AUGUST 2017
www.ti.com
5 Description (continued)
The DS90UB926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB,
video control, and audio data.
An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG)
and enhanced progressive turnon (EPTO) features.
4
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
DS90UB926Q-Q1
www.ti.com
SNLS422D – JULY 2012 – REVISED AUGUST 2017
6 Pin Configuration and Functions
ROUT3 / R3
ROUT4 / R4
ROUT5 / R5
ROUT6 / R6
ROUT7 / R7
LOCK
OEN
36
35
34
33
32
31
40
37
ROUT1 / R1 / GPIO1
41
38
ROUT0 / R0 / GPIO0
42
ROUT2 / R2
PASS
43
VDDIO
RES1
44
39
I2S_DA / GPO_REG6
BISTEN
45
NKB Package
60-Pin WQFN With Exposed Thermal Pad
Top View
OSS_SEL
46
30
I2S_WC / GPO_REG7
RES0
47
29
VDD33_B
VDD33_A
48
28
ROUT8 / G0 / GPIO2
RIN+
49
27
ROUT9 / G1 / GPIO3
RIN-
50
26
ROUT10 / G2
CMF
51
25
ROUT11 / G3
CMLOUTP
52
24
VDDIO
CMLOUTN
53
TOP VIEW
23
ROUT12 / G4
NC
54
DAP = GND
22
ROUT13 / G5
CAPR12
55
21
ROUT14 / G6
IDx
56
20
ROUT15 / G7
CAPP12
57
19
ROUT16 / B0 / GPO_REG4
CAPI2S
58
18
ROUT17 / B1 / GPO_REG5 / I2S_DB
PDB
59
17
ROUT18 / B2
MCLK
60
16
BISTC / INTB_IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GPO_REG8 / I2S_CLK
SDA
SCL
CAPL12
PCLK
DE
VS
HS
B7 / ROUT23
B6 / ROUT22
B5 / ROUT21
B4 / ROUT20
VDDIO
B3 / ROUT19
MODE_SEL
DS90UB926Q-Q1
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
5
DS90UB926Q-Q1
SNLS422D – JULY 2012 – REVISED AUGUST 2017
www.ti.com
Pin Functions
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
ROUT[23:0] /
R[7:0],
G[7:0], B[7:0]
41, 40, 39, 37,
36, 35, 34, 33,
28, 27, 26, 25, O, LVCMOS
23, 22, 21, 20, with pulldown
19, 18, 17, 14,
12, 11, 10, 9
Parallel Interface Data Output Pins
Leave open if unused.
ROUT0 / R0 can optionally be used as GPIO0 and ROUT1 / R1 can optionally be used as
GPIO1.
ROUT8 / G0 can optionally be used as GPIO2 and ROUT9 / G1 can optionally be used as
GPIO3.
ROUT16 / B0 can optionally be used as GPO_REG4 and ROUT17/ B1 can optionally be
used as I2S_DB / GPO_REG5.
HS
8
Horizontal Sync Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
O, LVCMOS Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
with pulldown when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs.
See Table 11
VS
7
Vertical Sync Output Pin
O, LVCMOS
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
with pulldown
is 130 PCLKs.
DE
6
Data Enable Output Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
O, LVCMOS Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
with pulldown when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs.
See Table 11
PCLK
5
O, LVCMOS Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 11
with pulldown
1, 30, 45
Digital Audio Interface Data Output Pins
O, LVCMOS Leave open if unused
with pulldown I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
I2S_CLK,
I2S_WC,
I2S_DA
MCLK
60
O, LVCMOS I2S Master Clock Output
with pulldown x1, x2, or x4 of I2S_CLK Frequency
OPTIONAL PARALLEL INTERFACE
18
Second Channel Digital Audio Interface Data Output pin at 18–bit color mode and set by
O, LVCMOS MODE_SEL or configuration register
with pulldown Leave open if unused
I2S_B can optionally be used as BI or GPO_REG5.
GPIO[3:0]
27, 28, 40, 41
Standard General Purpose IOs.
I/O,
Available only in 18-bit color mode, and set by MODE_SEL or configuration register. See
LVCMOS
Table 11
with pulldown Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG[8:
4]
1, 30, 45, 18,
19
O, LVCMOS General Purpose Outputs and set by configuration register. See Table 11
with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
I2S_DB
INTB_IN
16
Input,
Interrupt Input
LVCMOS
Shared with BISTC
with pulldown
OPTIONAL PARALLEL INTERFACE
PDB
59
Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
I, LVCMOS Refer to Power Up Requirements and PDB Pin.
with pulldown PDB = L, device is powered down.
When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE,
the PLL is shutdown and IDD is minimized. .
OEN
31
Input,
Output Enable Pin
LVCMOS
See Table 8
with pulldown
OSS_SEL
46
Input,
Output Sleep State Select Pin
LVCMOS
See Table 8
with pulldown
6
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
DS90UB926Q-Q1
www.ti.com
SNLS422D – JULY 2012 – REVISED AUGUST 2017
Pin Functions (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
MODE_SEL
15
I, Analog
Device Configuration Select. See Table 9
IDx
56
I, Analog
I2C Serial Control Bus Device ID Address Select
External pullup to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pullup and pulldown resistor to create a voltage divider.
See Figure 23
SCL
3
I/O,
LVCMOS
Open-Drain
I2C Clock Input / Output Interface
Must have an external pullup to VDD33, DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
SDA
2
I/O,
LVCMOS
Open-Drain
I2C Data Input / Output Interface
Must have an external pullup to VDD33, DO NOT FLOAT.
Recommended pullup: 4.7 kΩ.
BISTEN
44
BIST Enable Pin
I, LVCMOS
0: BIST Mode is disabled.
with pulldown
1: BIST Mode is enabled.
BISTC
16
BIST Clock Select
I, LVCMOS
Shared with INTB_IN
with pulldown
0: PCLK; 1: 33 MHz
LOCK
32
LOCK Status Output Pin
O, LVCMOS 0: PLL is unlocked, ROUT[23:0]/RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states
with pulldown are controlled by OEN. May be used as Link Status or Display Enable
1: PLL is Locked, outputs are active
PASS
42
PASS Output Pin
O, LVCMOS 0: One or more errors were detected in the received payload
with pulldown 1: ERROR FREE Transmission
Leave Open if unused. Route to test point (pad) recommended
STATUS
FPD-LINK III SERIAL INTERFACE
RIN+
49
I, LVDS
True Input.
The interconnection should be AC-coupled to this pin with a 0.1-μF capacitor.
RIN-
50
I, LVDS
Inverting Input.
The interconnection should be AC-coupled to this pin with a 0.1-μF capacitor.
CMLOUTP
52
O, LVDS
True CML Output
Monitor point for equalized differential signal
CMLOUTN
53
O, LVDS
Inverting CML Output
Monitor point for equalized differential signal
CMF
51
POWER AND GROUND
VDD33_A,
VDD33_B
Analog
Common Mode Filter. Connect 0.1-μF capacitor to GND
(1)
Power to on-chip regulator 3 V – 3.6 V. Requires 4.7 µF to GND at each VDD pin.
48, 29
Power
VDDIO
13, 24, 38
Power
LVCMOS I/O Power 1.8 V ±5% OR 3 V – 3.6 V. Requires 4.7 µF to GND at each VDDIO
pin.
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPR12,
CAPP12,
CAPI2S
55, 57, 58
CAP
CAPL12
4
CAP
54
NC
43.47
GND
Decoupling capacitor connection for on-chip regulator. Requires a 4.7 µF to GND at each
CAP pin.
Decoupling capacitor connection for on-chip regulator. Requires two 4.7 µF to GND at this
CAP pin.
OTHERS
NC
RES[1:0]
(1)
No connect. This pin may be left open or tied to any level.
Reserved - tie to Ground.
The VDD (VDD33 and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise.
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
7
DS90UB926Q-Q1
SNLS422D – JULY 2012 – REVISED AUGUST 2017
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
See (1) (2) (3) (4)
MIN
MAX
UNIT
Supply voltage – VDD33
−0.3
4
V
Supply voltage – VDDIO
−0.3
4
V
LVCMOS I/O voltage
−0.3
(VDDIO + 0.3)
V
Deserializer input voltage
−0.3
2.75
V
Junction temperature
Maximum power dissipation
capacity at 25°C
150
°C
RθJA
31
°C/W
RθJC
2.4
°C/W
150
°C
−65
Storage temperature, Tstg
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum limit (VDDIO + 0.3 V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning from
HIGH to LOW).
For soldering specifications: see product folder at www.ti.com and Absolute Maximum Ratings for Soldering (SNOA549).
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
±8000
Charged-device model (CDM), per AEC Q100-011
±1250
Machine model
±250
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
Air Discharge (Pin 49 and 50)
Contact Discharge (Pin 49 and 50)
±8000
(ISO1060SN5), RD = 330 Ω
CS = 150 pF
Air Discharge (Pin 49 and 50)
±15000
Contact Discharge (Pin 49 and 50)
±8000
(ISO10605), RD = 2 kΩ
CS = 150 and 330 pF
Air Discharge (Pin 49 and 50)
±15000
Contact Discharge (Pin 49 and 50)
±8000
UNIT
±15000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Supply voltage (VDD33)
LVCMOS supply voltage (VDDIO)
Operating free air
MAX
UNIT
3
3.3
3.6
V
3
3.3
3.6
V
Connect VDDIO to 1.8 V and use 1.8-V IOs
1.71
1.8
1.89
V
−40
25
105
°C
85
MHz
100
mVP-P
temperature (TA)
5
Supply noise (1)
8
NOM
Connect VDDIO to 3.3 V and use 3.3-V IOs
PCLK frequency
(1)
MIN
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies
with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no
error when the noise frequency is less than 50 MHz.
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
DS90UB926Q-Q1
www.ti.com
SNLS422D – JULY 2012 – REVISED AUGUST 2017
7.4 Thermal Information
DS90UB926Q-Q1
THERMAL METRIC (1)
NKB (WQFN)
UNIT
60 PINS
RθJA
Junction-to-ambient thermal resistance
26.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
8.1
°C/W
RθJB
Junction-to-board thermal resistance
5.2
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
5.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
7.5 DC Electrical Characteristics
over recommended operating supply and temperature ranges unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(2) (3)
MIN
TYP
MAX
UNIT
LVCMOS I/O DC SPECIFICATIONS
VIH
High Level Voltage
VDDIO = 3 to 3.6 V
2
VIL
Low Level Input
VDDIO = 3 to 3.6 V
IIN
Input Current
VIN = 0 V or VDDIO = 3 to 3.6 V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
PDB
VDDIO = 1.71 to 1.89 V
VDDIO = 3 to 3.6 V
IIN
VOH
VOL
Input Current
High Level Output Voltage
Low Level Output Voltage
VDDIO = 1.71 to 1.89 V
VIN = 0 V or
VDDIO
IOH = −4 mA
IOL = 4 mA
VDDIO = 3
to 3.6 V
µA
2
VDDIO
0.65 ×
VDDIO
VDDIO
GND
0.8
GND
0.35 ×
VDDIO
VDDIO = 1.7
to 1.89 V
−10
±1
10
VDDIO = 3 to
3.6 V
2.4
VDDIO
VDDIO –
0.45
VDDIO
GND
0.4
GND
0.35
VDDIO = 3 to
3.6 V
VDDIO = 1.7
to 1.89 V
VOUT = 0 V
IOZ
Tri-state Output Current
VOUT = 0 V or VDDIO, PDB = L
(3)
V
10
10
VDDIO = 1.7
to 1.89 V
V
0.8
±1
Output Short Circuit Current
(2)
OEN, OSS_SEL,
BISTEN, BISTC /
INTB_IN,
GPIO[3:0]
±1
−10
IOS
(1)
GND
–10
VDDIO = 3 to 3.6 V
VDDIO
V
V
μA
ROUT[23:0], HS,
VS, DE, PCLK,
LOCK, PASS,
MCLK, I2S_CLK,
I2S_WC, I2S_DA,
I2S_DB,
GPO_REG[8:4]
V
V
−60
−10
mA
10
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25°C, and at the Recommended Operating Conditions at the
time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
9
DS90UB926Q-Q1
SNLS422D – JULY 2012 – REVISED AUGUST 2017
www.ti.com
DC Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS
VTH
Differential Threshold High
Voltage
VTL
Differential Threshold Low
Voltage
VCM
Differential Common-mode
Voltage
RT
Internal Termination Resistor Differential
50
VCM = 2.5 V
(Internal VBIAS)
−50
mV
mV
RIN+, RIN–
1.8
80
100
V
120
Ω
CML MONITOR DRIVER OUTPUT DC SPECIFICATIONS
VODp-p
Differential Output Voltage
CMLOUTP,
CMLOUTN
RL = 100 Ω
360
mVp-p
SUPPLY CURRENT
IDD1
IDDIO1
IDD2
IDDIO2
Supply Current
(includes load current)
f = 85 MHz
VDD33= 3.6 V
VDD33
CL = 12 pF,
Checker Board
VDDIO= 3.6 V
VDDIO
Pattern (Figure 1)
VDDIO = 1.89 V
125
145
110
118
60
75
Supply Current
(includes load current)
f = 85MHz
VDD33 = 3.6 V VDD33
CL = 4 pF
Checker Board
VDDIO = 3.6 V
VDDIO
Pattern (Figure 1)
VDDIO = 1.89 V
125
145
75
85
50
65
90
115
Supply Current Sleep Mode
Without Input
Serial Stream
3
5
2
3
IDDS
IDDIOS
VDD33 = 3.6 V
VDDIO = 1.89 V
IDDZ
IDDIOZ
10
VDDIO = 3.6 V
Supply Current Power Down
VDD33
VDDIO
PDB = L, All
VDD33 = 3.6 V VDD33
LVCMOS inputs
V
= 3.6 V
are floating or tied DDIO
VDDIO
VDDIO = 1.89 V
to GND
Submit Documentation Feedback
2
10
0.05
10
0.05
10
mA
mA
mA
mA
mA
mA
mA
mA
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
DS90UB926Q-Q1
www.ti.com
SNLS422D – JULY 2012 – REVISED AUGUST 2017
7.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(2) (3)
MIN
TYP
MAX
UNIT
GPIO BIT RATE
Forward Channel Bit Rate
BR
Back Channel Bit Rate
See (4) (5)
f = 5 to 85
MHz,
GPIO[3:0]
0.25 × f
Mbps
>50
>75
kbps
0.3
0.4
UI
200
300
mV
800
ns
CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS
EW
Differential Output Eye Opening
Width (6)
EH
Differential Output Eye Height
RL = 100 Ω,
Jitter Freq > f / 40 (Figure 2) (4) (5)
CMLOUTP,
CMLOUTN,
f = 85 MHz
BIST MODE
tPASS
BIST PASS Valid Time
BISTEN = H (Figure 8) (4) (5)
PASS
SSCG MODE
fDEV
Spread Spectrum Clocking
Deviation Frequency
fMOD
Spread Spectrum Clocking
Modulation Frequency
(1)
(2)
(3)
(4)
(5)
(6)
See Figure 14, Table 1, Table 2
(4) (5)
f = 85 MHz,
SSCG = ON
±0.5%
±2.5%
8
100
kHz
The Electrical Characteristics tables list ensured specifications under the listed in Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at the Recommended Operating Conditions at
the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35 * PCLK). The UI scales with PCLK frequency.
Submit Documentation Feedback
Copyright © 2012–2017, Texas Instruments Incorporated
Product Folder Links: DS90UB926Q-Q1
11
DS90UB926Q-Q1
SNLS422D – JULY 2012 – REVISED AUGUST 2017
www.ti.com
7.7 DC and AC Serial Control Bus Characteristics
Over 3.3-V supply and temperature ranges unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
VIH
Input High Level
SDA and SCL
VIL
Input Low Level Voltage
SDA and SCL
VHY
Input Hysteresis
SDA, IOL = 1.25 mA
Iin
SDA or SCL, VIN = VDD33 or GND
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Setup Time — READ
tHD;DAT
Holdup Time — READ
tSP
Input Filter
Cin
Input Capacitance
(1)
(2)
(3)
MIN
TYP
MAX
UNIT
0.7 ×
VDD33
VDD33
V
GND
0.3 ×
VDD33
V
> 50
VOL
tR
(2) (3)
mV
0
0.36
V
–10
10
µA
430
ns
20
ns
See Figure 9
560
ns
See Figure 9
615
ns
50
ns
SDA or SCL
工商网监
湘ICP备2023018690号
