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DS90UH926QSQ/NOPB

DS90UH926QSQ/NOPB

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    WQFN-60_9X9MM-EP

  • 描述:

    IC SERIAL/DESERIAL 24 BIT 60WQFN

  • 数据手册
  • 价格&库存
DS90UH926QSQ/NOPB 数据手册
Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design DS90UH926Q-Q1 SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 DS90UH926Q-Q1 720p, 24-Bit Color FPD-Link III Deserializer With HDCP 1 Features 3 Description • The DS90UH926Q-Q1 deserializer, in conjunction with the DS90UH925Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design. 1 • • • • • • • • • • • • • • • AEC-Q100 Qualified for Automotive Applications – Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature – Device HBM ESD Classification Level 3B – Device CDM ESD Classification Level C6 – Device MM ESD Classification Level M3 Integrated HDCP Cipher Engine With On-Chip Key Storage Bidirectional Control Interface Channel Interface With I2C Compatible Serial Control Bus Supports High-Definition (720p) Digital Video Format RGB888 + VS, HS, DE and I2S Audio Supported 5- to 85-MHz PCLK Supported Single 3.3-V Operation With 1.8-V or 3.3-V Compatible LVCMOS I/O Interface AC-Coupled STP Interconnect up to 10 Meters Parallel LVCMOS Video Outputs DC-Balanced and Scrambled Data With Embedded Clock Adaptive Cable Equalization Supports HDCP Repeater Application Image Enhancement (White Balance and Dithering) and Internal Pattern Generation EMI Minimization (SSCG and EPTO) Low Power Modes Minimize Power Dissipation Backward-Compatible Modes An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features. The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory. Device Information(1) PART NUMBER 2 Applications • • The DS90UH926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock. PACKAGE DS90UH926Q-Q1 Automotive Display for Navigation Rear Seat Entertainment Systems WQFN (60) BODY SIZE (NOM) 9.00 mm × 9.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Diagram HOST Graphics Processor RGB Digital Display Interface VDD33 VDDIO (1.8V or 3.3V) (3.3V) R[7:0] G[7:0] B[7:0] HS VS DE PCLK SCL SDA IDx R[7:0] G[7:0] B[7:0] HS VS DE PCLK FPD-Link III 1 Pair / AC Coupled 0.1 PF 0.1 PF DOUT+ RIN+ DOUT- PDB I2S AUDIO (STEREO) VDDIO VDD33 (3.3V) (1.8V or 3.3V) 3 / DS90UH925Q Serializer 0.1 PF 100 ohm STP Cable MODE_SEL INTB DAP 0.1 PF PDB OSS_SEL OEN MODE_SEL RINDS90UH926Q Deserializer SCL SDA IDx LOCK PASS 3 / INTB_IN RGB Display 720p 24-bit color depth I2S AUDIO (STEREO) MCLK DAP 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS90UH926Q-Q1 SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 7 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Absolute Maximum Ratings ..................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 8 DC Electrical Characteristics .................................... 8 AC Electrical Characteristics................................... 10 DC and AC Serial Control Bus Characteristics....... 10 Recommended Timing Requirements for the Serial Control Bus .............................................................. 11 6.9 Switching Characteristics ........................................ 11 6.10 Timing Diagrams ................................................... 12 6.11 Typical Characteristics .......................................... 15 7 Detailed Description ............................................ 16 7.1 Overview ................................................................. 16 7.2 Functional Block Diagram ....................................... 16 7.3 7.4 7.5 7.6 8 Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 16 28 32 33 Application and Implementation ........................ 47 8.1 Application Information............................................ 47 8.2 Typical Application .................................................. 47 9 Power Supply Recommendations...................... 50 9.1 Power-Up Requirements and PDB Pin ................... 50 10 Layout................................................................... 51 10.1 Layout Guidelines ................................................. 51 10.2 Layout Examples................................................... 53 11 Device and Documentation Support ................. 54 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 54 54 54 54 54 54 12 Mechanical, Packaging, and Orderable Information ........................................................... 54 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision L (February 2017) to Revision M Page • Reverted all previous MLCK content changes made in Revision L back to Revision K ........................................................ 1 • Removed disable jitter cleaner note ....................................................................................................................................... 5 Changes from Revision K (January 2015) to Revision L Page • Changed top view pin out diagram ........................................................................................................................................ 4 • Changed CLK to RES2 .......................................................................................................................................................... 5 • Added note to disable jitter cleaner ....................................................................................................................................... 5 • Changed MCLK to RES2 ....................................................................................................................................................... 5 • Deleted reference to MCLK in this section ............................................................................................................................ 8 • Deleted reference to MCLK in this section .......................................................................................................................... 11 • Deleted reference to MCLK ................................................................................................................................................. 25 • Deleted I2S Jitter Cleaning section ..................................................................................................................................... 25 • Deleted MCLK section ......................................................................................................................................................... 25 • Deleted MCLK columns in the Audio Interface Frequencies table....................................................................................... 26 • Changed values in columns 2 to 5 of Configuration Select (MODE_SEL) table.................................................................. 29 • Changed values in columns 2 to 5 of IDx table ................................................................................................................... 32 • Changed Removed register reference to MCLK .................................................................................................................. 42 • Changed Typical Display System Diagram (removed MCLK) ............................................................................................. 47 • Changed Power-Up Requirements and PDB pin description and added Power-Up Sequence graphic. ........................... 50 2 Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Product Folder Links: DS90UH926Q-Q1 DS90UH926Q-Q1 www.ti.com SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 Changes from Revision J (April 2013) to Revision K • Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision I (August 2012) to Revision J • Page Changed layout of National Semiconductor data sheet to TI format...................................................................................... 1 Changes from Revision H (March 2012) to Revision I • Page : Configuration Select (MODE_SEL) #6 I2S Channel B (18–bit Mode) from L to H, corrected typo in table “DC and AC Serial Control Bus Characteristics” from VDDIO to VDD33, added Recommended FRC settings table, added “When backward compatible mode = ON, set LFMODE = 0” under Functional Description. Reformatted table 9 and added clarification to notes. Added clarification to notes on Serial Control Bus Registers, address 0x02[3:0] (backwards compatible and LFMODE registers), added “Note: Do not enable SSCG feature if PCLK source into the SER has an SSC clock already.” under Functional Description, EMI REDUCTION FEATURES, Spread Spectrum Clock Generation (SSCG) ...................................................................................................................................................... 1 Changes from Revision G (February 2012) to Revision H • Page Deleted “DC Electrical Characteristics” PDB VDDIO = 1.71 to 1.89 V, added under “SUPPLY CURRENT IDDZ, DDIOZ, IDDIOZMax = 10 mA, added under “CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS” EW Min = 0.3 UI AND EH Min = 200 mV, added “INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB)” under Functional Description section, updated "POWER DOWN (PDB) description under Functional Description from VDDIO to VDDIO = 3 to 3.6 V or VDD33, updated Figure 24 .................................................................................................. 1 Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Product Folder Links: DS90UH926Q-Q1 3 DS90UH926Q-Q1 SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 www.ti.com 5 Pin Configuration and Functions OSS_SEL R6 R7 LOCK OEN 32 31 R5 35 33 R4 36 34 R3 40 37 R1/GPIO1 41 38 R0/GPIO0 42 R2 PASS 43 VDDIO RES1 44 39 I2S_DA/GPO_REG6 BISTEN 45 NKB Package 60 Pin WQFN With Exposed Thermal Pad Top View 30 I2S_WC/GPO_REG7 47 29 VDD33_B 48 28 G0/GPIO2 49 27 G1/GPIO3 50 26 G2 CMF 51 25 G3 CMLOUTP 52 24 VDDIO RES0 VDD33_A RIN+ RIN- 46 DS90UH926Q-Q1 CMLOUTN 53 TOP VIEW NC 54 DAP = GND CAPR12 55 21 23 G4 22 G5 G6 15 14 B3 MODE_SEL 11 B5 12 10 B6 13 9 B4 8 B7 VDDIO 7 VS BISTC/INTB_IN HS 16 DE 60 6 MCLK 5 B2 PCLK B1/I2S_DB/GPO_REG5 17 4 18 59 3 58 PDB SCL CAPI2S CAPL12 B0/GPO_REG4 2 G7 19 1 20 57 SDA 56 I2S_CLK/GPO_REG8 IDx CAPP12 Pin Functions PIN NAME NO. I/O, TYPE DESCRIPTION LVCMOS PARALLEL INTERFACE R[7:0] 33, 34, 35, 36, 37, 39, 40, 41 RED Parallel Interface Data Output Pins O, LVCMOS Leave open if unused with pulldown R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1 G[7:0] 20, 21, 22, 23, 25, 26, 27, 28 GREEN Parallel Interface Data Output Pins O, LVCMOS Leave open if unused with pulldown G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3. B[7:0] 9, 10, 11, 12, 14, 17, 18, 19 BLUE Parallel Interface Data Output Pins O, LVCMOS Leave open if unused with pulldown B0 can optionally be used as GPO_REG4 and B1 can optionally be used as I2S_DB or GPO_REG5. 8 Horizontal Sync Output Pin Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the O, LVCMOS Control Signal Filter is enabled. There is no restriction on the minimum transition pulse with pulldown when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs. See Table 11 HS 4 Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Product Folder Links: DS90UH926Q-Q1 DS90UH926Q-Q1 www.ti.com SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 Pin Functions (continued) PIN NAME NO. I/O, TYPE DESCRIPTION 7 Vertical Sync Output Pin O, LVCMOS Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse with pulldown width is 130 PCLKs. DE 6 Data Enable Output Pin Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the O, LVCMOS Control Signal Filter is enabled. There is no restriction on the minimum transition pulse with pulldown when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs. See Table 11 PCLK 5 O, LVCMOS Pixel Clock Output Pin. Strobe edge set by RFB configuration register. See Table 11 with pulldown 1, 30, 45 Digital Audio Interface Data Output Pins O, LVCMOS Leave open if unused with pulldown I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as GPO_REG7, and I2S_DA can optionally be used as GPO_REG6. VS I2S_CLK, I2S_WC, I2S_DA MCLK 60 O, LVCMOS I2S Master Clock Output with pulldown x1, x2, or x4 of I2S_CLK Frequency OPTIONAL PARALLEL INTERFACE I2S_DB 18 Second Channel Digital Audio Interface Data Output pin at 18–bit color mode and set by O, LVCMOS MODE_SEL or configuration register with pulldown Leave open if unused I2S_B can optionally be used as BI or GPO_REG5. GPIO[3:0] 27, 28, 40, 41 Standard General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL or configuration register. I/O, LVCMOS See Table 11 with pulldown Leave open if unused Shared with G1, G0, R1 and R0. GPO_REG[8: 4] 1, 30, 45, 18, 19 O, LVCMOS General Purpose Outputs and set by configuration register. See Table 11 with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0. 16 Input, Interrupt Input LVCMOS Shared with BISTC with pulldown PDB 59 Power-down Mode Input Pin PDB = H, device is enabled (normal operation) I, LVCMOS Refer to Power Supply Recommendations. with pulldown PDB = L, device is powered down. When the device is in the POWER DOWN state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown and IDD is minimized. OEN 31 Input, Output Enable Pin. LVCMOS See Table 8 with pulldown OSS_SEL 46 Input, Output Sleep State Select Pin. LVCMOS See Table 8 with pulldown MODE_SEL 15 BISTEN 44 BIST Enable Pin. I, LVCMOS 0: BIST Mode is disabled. with pulldown 1: BIST Mode is enabled. BISTC 16 BIST Clock Select. I, LVCMOS Shared with INTB_IN with pulldown 0: PCLK; 1: 33 MHz INTB_IN CONTROL I, Analog Device Configuration Select. See Table 9 Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Product Folder Links: DS90UH926Q-Q1 5 DS90UH926Q-Q1 SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 www.ti.com Pin Functions (continued) PIN NAME NO. I/O, TYPE DESCRIPTION I2C I, Analog I2C Serial Control Bus Device ID Address Select External pull-up to VDD33 is required under all conditions, DO NOT FLOAT. Connect to external pullup and pulldown resistor to create a voltage divider. See Figure 23 IDx 56 SCL 3 I2C Clock Input / Output Interface I/O, LVCMOS Must have an external pullup to VDD33, DO NOT FLOAT. Open-Drain Recommended pullup: 4.7 kΩ. SDA 2 I2C Data Input / Output Interface I/O, LVCMOS Must have an external pullup to VDD33, DO NOT FLOAT. Open-Drain Recommended pullup: 4.7 kΩ. LOCK 32 LOCK Status Output Pin O, LVCMOS 0: PLL is unlocked, RGB[7:0], I2S[2:0], HS, VS, DE and PCLK output states are controlled with pulldown by OEN. May be used as Link Status or Display Enable 1: PLL is Locked, outputs are active PASS 42 PASS Output Pin O, LVCMOS 0: One or more errors were detected in the received payload with pulldown 1: ERROR FREE Transmission Leave Open if unused. Route to test point (pad) recommended STATUS FPD-LINK III SERIAL INTERFACE RIN+ 49 I, LVDS True Input. The interconnection should be AC-coupled to this pin with a 0.1 μF capacitor. RIN– 50 I, LVDS Inverting Input. The interconnection should be AC-coupled to this pin with a 0.1 μF capacitor. CMLOUTP 52 O, LVDS True CML Output Monitor point for equalized differential signal CMLOUTN 53 O, LVDS Inverting CML Output Monitor point for equalized differential signal CMF 51 Analog Common Mode Filter. Connect 0.1-μF capacitor to GND. 48, 29 Power Power to on-chip regulator 3 V – 3.6 V. Requires 4.7 uF to GND at each VDD pin. VDDIO 13, 24, 38 Power LVCMOS I/O Power 1.8 V ±5% OR 3 V – 3.6 V. Requires 4.7 uF to GND at each VDDIO pin. GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. POWER (1) AND GROUND VDD33_A, VDD33_B REGULATOR CAPACITOR CAPR12 55 CAPP12 57 CAPI2S 58 CAPL12 4 CAP Decoupling capacitor connection for on-chip regulator. Requires a 4.7-µF to GND at each CAP pin. CAP Decoupling capacitor connection for on-chip regulator. Requires two 4.7-µF to GND at this CAP pin. OTHERS NC RES[1:0] (1) 6 54 NC 43.47 GND No connect. This pin may be left open or tied to any level. Reserved - tie to Ground The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Product Folder Links: DS90UH926Q-Q1 DS90UH926Q-Q1 www.ti.com SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 6 Specifications 6.1 Absolute Maximum Ratings See (1) (2) (3) MIN MAX UNIT Supply voltage – VDD33 −0.3 4 V Supply voltage – VDDIO −0.3 4 V LVCMOS I/O voltage −0.3 (VDDIO + 0.3) V Deserializer input voltage −0.3 2.75 V Junction temperature 60-pin WQFN Package Maximum power dissipation capacity at 25°C Derate above 25 °C 150 °C 1/ RθJA °C/W 31 °C/W 2.4 °C/W 150 °C RθJA RθJC −65 Storage temperature, Tstg (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering (SNOA549). 6.2 ESD Ratings VALUE Human-body model (HBM), per AEC Q100-002 V(ESD) (1) Electrostatic discharge (1) UNIT ±8000 Charged-device model (CDM), per AEC Q100-011 ±1250 Machine model, all pins ±250 (IEC, powered-up only) RD = 330 Ω, CS = 150 pF Air Discharge (Pin 49 and 50) Contact Discharge (Pin 49 and 50) ±15000 ±8000 (ISO10605) RD = 330 Ω, CS = 150 pF Air Discharge (Pin 49 and 50) ±15000 Contact Discharge (Pin 49 and 50) ±8000 (ISO10605) RD = 2 kΩ, CS = 150 & 330 pF Air Discharge (Pin 49 and 50) ±15000 Contact Discharge (Pin 49 and 50) ±8000 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions MIN NOM MAX 3 3.3 3.6 V Connect VDDIO to 3.3 V and use 3.3-V IOs 3 3.3 3.6 V Connect VDDIO to 1.8 V and use 1.8-V IOs 1.71 1.8 1.89 V −40 25 105 °C Supply voltage (VDD33) LVCMOS supply voltage (VDDIO) Operating free air temperature (TA) PCLK frequency 5 Supply noise (1) (1) UNIT 85 MHz 100 mVP-P Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies with amplitude = 100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10-meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz. Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Product Folder Links: DS90UH926Q-Q1 7 DS90UH926Q-Q1 SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 www.ti.com 6.4 Thermal Information DS90UH926Q-Q1 THERMAL METRIC (1) NKB (WQFN) UNIT 60 PINS RθJA Junction-to-ambient thermal resistance 26.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 8.1 °C/W RθJB Junction-to-board thermal resistance 5.2 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 5.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. 6.5 DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT 2 VDDIO V GND 0.8 V 10 μA 2 VDDIO V 0.65 × VDDIO VDDIO V GND 0.8 V GND 0.35 × VDDIO V LVCMOS I/O DC SPECIFICATIONS VIH High Level Input Voltage VDDIO = 3 to 3.6 V VIL Low Level Input Voltage VDDIO = 3 to 3.6 V IIN Input Current VIN = 0 V or VDDIO = 3 to 3.6 V VIH High Level Input Voltage VIL Low Level Input Voltage IIN VOH Input Current High Level Output Voltage PDB VDDIO = 3 to 3.6 V VDDIO = 1.71 to 1.89 V VDDIO = 3 to 3.6 V OEN, OSS_SEL, BISTEN, BISTC / INTB_IN, GPIO[3:0] VDDIO = 1.71 to 1.89 V VIN = 0 V or VDDIO −10 ±1 10 μA VDDIO = 1.7 to 1.89 V −10 ±1 10 μA VDDIO = 3 to 3.6 V IOH = −4 mA VDDIO = 1.7 to 1.89 V VDDIO = 3 to 3.6 V Low Level Output Voltage IOL = 4 mA IOS Output Short-Circuit Current VOUT = 0 V IOZ Tri-state Output Current VOUT = 0 V or VDDIO, PDB = L (2) (3) 8 ±1 VDDIO = 3 to 3.6 V VOL (1) −10 VDDIO = 1.7 to 1.89 V R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, LOCK, PASS, MCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB, GPO_REG[8:4] 2.4 VDDIO V VDDIO0.45 VDDIO V GND 0.4 V GND 0.35 V −60 −10 mA 10 μA The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the time of product characterization and are not ensured. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages. Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Product Folder Links: DS90UH926Q-Q1 DS90UH926Q-Q1 www.ti.com SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3) PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage VCM Differential Commonmode Voltage RT Internal Termination Resistor - Differential 50 VCM = 2.5 V (Internal VBIAS) −50 mV mV RIN+, RIN– 1.8 80 100 V 120 Ω CML MONITOR DRIVER OUTPUT DC SPECIFICATIONS VODp-p Differential Output Voltage CMLOUTP, CMLOUTN RL = 100 Ω 360 mVp-p SUPPLY CURRENT IDD1 IDDIO1 IDD2 IDDIO2 CL = 12 pF, Checker Board Pattern Figure 1 Supply Current (includes load current) f = 85 MHz VDD33 = 3.6 V CL = 4 pF Checker Board Pattern, VDDIO = 3.6 V Figure 1 VDDIO = 1.89 V Supply Current Sleep Mode Without Input Serial Stream IDDS IDDIOS VDDIO= 3.6 V VDDIO = 1.89 V VDD33 = 3.6 V VDDIO = 3.6 V VDDIO = 1.89 V IDDZ IDDIOZ VDD33= 3.6 V Supply Current (includes load current) f = 85 MHz Supply Current Power Down PDB = L, All LVCMOS inputs are floating or tied to GND VDD33 = 3.6 V VDDIO = 3.6 V VDDIO = 1.89 V VDD33 VDDIO VDD33 VDDIO VDD33 VDDIO VDD33 VDDIO 125 145 110 118 60 75 125 145 75 85 50 65 90 115 3 5 2 3 2 10 0.05 10 0.05 10 Submit Documentation Feedback Copyright © 2010–2017, Texas Instruments Incorporated Product Folder Links: DS90UH926Q-Q1 mA mA mA mA mA mA mA mA 9 DS90UH926Q-Q1 SNLS337M – OCTOBER 2010 – REVISED AUGUST 2017 www.ti.com 6.6 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT GPIO BIT RATE Forward Channel Bit Rate BR See (4) Back Channel Bit Rate (5) f = 5 – 85 MHz, GPIO[3:0] 0.25 × f Mbps > 50 > 75 kbps 0.3 0.4 UI 200 300 mV 800 ns CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS EW Differential Output Eye Opening Width (6) EH Differential Output Eye Height RL = 100 Ω, Jitter Freq > f / 40 Figure 2 (4) (5) CMLOUTP, CMLOUTN, f = 85 MHz BIST MODE tPASS BIST PASS Valid Time BISTEN = H Figure 8 (4) (5) PASS SSCG MODE fDEV Spread Spectrum Clocking Deviation Frequency fMOD Spread Spectrum Clocking Modulation Frequency (1) (2) (3) (4) (5) (6) SeeFigure 14, Table 1 and Table 2 (4) (5) ±0.5% ±2.5% 8 100 f = 85 MHz, SSCG = ON kHz The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the electrical characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25 °C, and at Recommended Operating Conditions at the time of product characterization and are not ensured. Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages. Specification is ensured by characterization and is not tested in production. Specification is ensured by design and is not tested in production. UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35 × PCLK). The UI scales with PCLK frequency. 6.7 DC and AC Serial Control Bus Characteristics Over 3.3-V supply and temperature ranges unless otherwise specified. (1) PARAMETER (2) (3) TEST CONDITIONS MIN VIH Input High Level SDA and SCL 0.7 × VDD33 VIL Input Low Level Voltage SDA and SCL GND VHY Input Hysteresis VOL SDA or SCL, VIN = VDD33 or GND tR SDA Rise Time – READ tF SDA Fall Time – READ tSU;DAT Setup Time — READ tHD;DAT Holdup Time — READ tSP Input Filter CIN Input Capacitance (1) (2) (3) 10 MAX UNIT VDD33 V 0.3 × VDD33 > 50 SDA, IOL = 1.25 mA IIN TYP 0 –10 V mV 0.36 V 10 µA 430 ns 20 ns SeeFigure 9 560 ns SeeFigure 9 615 ns SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9 SDA or SCL 50 ns
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