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Design
DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
DS90UR90xQ-Q1 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
5- to 65-MHz PCLK support (140 Mbps to
1.82 Gbps)
AC-Coupled STP interconnect cable up to 10
meters
Integrated terminations on serializer and
deserializer
At speed link BIST mode and reporting pin
Optional I2C-compatible serial control bus
RGB888 + VS, HS, DE support
Power down mode minimizes power dissipation
1.8-V or 3.3-V compatible LVCMOS I/O interface
Automotive-grade product: AEC-Q100 grade 2
qualified
>8-kV HBM and ISO 10605 ESD rating
Backward compatible mode for operation with
older generation devices
SERIALIZER — DS90UR905Q-Q1
– RGB888 + VS/HS/DE serialized to 1 Pair FPDLink II
– Randomizer/scrambler — DC-balanced data
stream
– Selectable output VOD and adjustable deemphasis
DESERIALIZER — DS90UR906Q-Q1
– FAST random data lock; no reference clock
required
– Adjustable input receiver equalization
– LOCK (real time link status) reporting pin
– EMI minimization on output parallel bus
(SSCG)
– Output slew control (OS)
Automotive display for navigation
Automotive display for entertainment
3 Description
The DS90UR90xQ-Q1 chipset translates a parallel
RGB video interface into a high-speed serialized
interface over a single pair. This serial bus scheme
makes system design easy by eliminating skew
problems between clock and data, reducing the
number of connector pins, reducing the interconnect
size, weight, cost, and easing overall PCB layout. In
addition, internal DC-balanced decoding is used to
support AC-coupled interconnects.
The DS90UR905Q-Q1 serializer embeds the clock,
balances the data payload, and level shifts the
signals to high-speed, low voltage differential
signaling. Up to 24 inputs are serialized, along with
the three video control signals. This supports full
24-bit color or 18-bit color and 6 general-purpose
signals (for example, Audio I2S applications).
The DS90UR906Q-Q1 deserializer recovers the data
(RGB) and control signals and extracts the clock from
the serial stream. The DS90UR906Q-Q1 is able to
lock to the incoming data stream without the use of a
training sequence or special SYNC patterns and does
not require a reference clock. A link status (LOCK)
output signal is provided.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UR905Q-Q1
WQFN (48)
7.00 mm × 7.00 mm
DS90UR906Q-Q1
WQFN (60)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Diagram
HOST
Graphics
Processor
RGB Digital Display Interface
VDDIO
(1.8 V or 3.3 V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
VDDIO
(1.8 V or 3.3 V)
FPD-Link II
1 Pair / AC Coupled
100 nF
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
100 nF
DOUT+
RIN+
DOUT-
RIN100 Ω STP Cable
DS90UR905Q
CMF
Serializer
SCL
SDA
ID[x]
Optional
DAP
DS90UR906Q
Deserializer
PDB
BISTEN
CONFIG [1:0]
RFB
VODSEL
DeEmph
BISTEN
Optional
VDDn
1.8 V
VDDn
1.8 V
RGB Display
QVGA to XGA
24-bit color depth
LOCK
PASS
STRAP pins
not shown
SCL
SDA
ID[x]
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UR905Q-Q1, DS90UR906Q-Q1
SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Description (continued)......................................... 4
Pin Configuration and Functions ......................... 5
Specifications....................................................... 10
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Absolute Maximum Ratings .................................... 10
ESD Ratings............................................................ 10
Recommended Operating Conditions..................... 11
Thermal Information ................................................ 11
Serializer DC Electrical Characteristics ................. 11
Deserializer DC Electrical Characteristics ............. 12
DC and AC Serial Control Bus Characteristics....... 14
Timing Requirements for DC and AC Serial Control
Bus ........................................................................... 14
7.9 Timing Requirements for Serializer PCLK .............. 14
7.10 Timing Requirements for Serial Control Bus ........ 14
7.11 Switching Characteristics: Serializer ..................... 15
7.12 Switching Characteristics: Deserializer................. 16
7.13 Typical Characteristics .......................................... 22
8
Detailed Description ............................................ 23
8.1
8.2
8.3
8.4
8.5
9
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Register Maps .........................................................
23
23
24
38
39
Application and Implementation ........................ 42
9.1 Application Information............................................ 42
9.2 Typical Applications ................................................ 43
10 Power Supply Recommendations ..................... 48
10.1 Power Up Requirements and PDB Pin ................. 48
11 Layout................................................................... 48
11.1 Layout Guidelines ................................................. 48
11.2 Layout Example .................................................... 49
12 Device and Documentation Support ................. 51
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
51
51
51
51
51
51
13 Mechanical, Packaging, and Orderable
Information ........................................................... 51
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (July 2015) to Revision I
•
Page
Fixed typo in power down supply current units - changed mA to uA .................................................................................. 12
Changes from Revision G (April 2013) to Revision H
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision F (January 2011) to Revision G
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 1
Changes from Revision E (August 2010) to Revision F
Page
•
Modified ESD to include IEC condition (330 Ohm, 150pF) .................................................................................................. 10
•
Updated deserializer parameters: IDD1, IDDZ, IDDIOZ, IDDR, VOH, VOL, tROS, tRDC .................................................. 11
•
Updated Figure 14 and Figure 15 to reflect data measurement at VDDIO/2 ...................................................................... 20
•
Updated Figure 38 – C13 changed to 4.7uF ....................................................................................................................... 44
2
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Product Folder Links: DS90UR905Q-Q1 DS90UR906Q-Q1
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SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
Changes from Revision D (May 2010) to Revision E
Page
•
Removed ”Data Randomization & Scrambling ”, "Noise Margin” and “Typical Performance Curves” sections ................... 1
•
Modified order information to include NOPB designation in NSPN column (replaced NSID column) .................................. 1
•
Corrected ESD Ratings to IEC 61000 – 4 – 2 from ISO 10605 (duplication). .................................................................... 10
•
Added RPU = 10k Ω condition for the Serial Control Bus Characteristics of tR and tF. ..................................................... 14
Changes from Revision C (March 2010) to Revision D
Page
•
DS90UR906Q-Q1 data sheet limits have been updated per characterization results ........................................................ 11
•
Corrected register 5 from RFB to VODSEL and register 4 from VODSEL to RFB in Table 14 .......................................... 39
Changes from Revision B (Feburary 2010) to Revision C
Page
•
Added reference to soldering profile..................................................................................................................................... 10
•
Added ESD CDM and ESD MM values................................................................................................................................ 10
•
Updated RθA value ............................................................................................................................................................... 11
Changes from Revision A (September 2009) to Revision B
Page
•
Removed IDDT3 and IDDIOT3 (RANDOM pattern) because the limits are the same as checker board pattern ................ 1
•
DS90UR905Q data sheet limits have been updated per characterization result and are the final limits ............................. 1
•
Updated DS90UR905Q-Q1 Typical Connection Diagram — Pin Control. Ref 30102044 .................................................... 5
•
Updated DS90UR906Q-Q1 Pin Diagram: strap changes on pin11, pin14, and pin42 .......................................................... 7
•
Added strap to pin 11 “ OS_PCLK ” (Output Slew_PCLK) ................................................................................................... 7
•
Changed strap pin 14 feature from “ RDS ” to “ OS_DATA ” (Output Slew_DATA) ............................................................. 7
•
Added strap to pin 42 “ OP_LOW ” (Output LOW) ................................................................................................................ 8
•
Updated DS90UR906Q-Q1 Typical Connection Diagram — Pin Control. Ref 30102045 .................................................... 8
•
Updated DS90UR906Q-Q1 Deserializer Pin Descriptions: RDS feature changed to OS_PCLK and OS_DATA.
Added OP_LOW feature ........................................................................................................................................................ 8
•
Created OP_LOW timing Figure 28. Ref 30102065 ............................................................................................................ 31
•
Created OP_LOW timing Figure 29. Ref 30102066 ............................................................................................................ 32
•
Updated Table 12: deleted ID[x] Address 7'b 110 1000 (h'68) (8'b 1101 0000 (h'D0)) ....................................................... 38
•
Updated Table 13: deleted ID[x] Address 7'b 111 0000 (h'70) (8'b 1110 0000 (h'E0)) ....................................................... 39
•
Changed Table 14 ADD \ 1 \ bit \ 6:0 \ ID[x]: deleted Device ID 7b'1101 00 (h'68). Only four (4) IDs will be available...... 39
•
Changed Table 15: ADD \ 0 \ bit \ 6 \ OSS_SEL: “ OSS_SEL ” changed feature to “ OS_PCLK ” (Output
Slew_PCLK). OSS_SEL moved to ADD \ 2 \ bit \ 6 \ ........................................................................................................... 40
•
Changed Table 15: ADD \ 0 \ bit \ 5 \ RDS: changed “ RDS ” feature to OS_DATA (Output Slew_DATA) ....................... 40
•
Changed Table 15: ADD \ 1\ bit \ 6:0 \ ID[x]: deleted Device ID 7b'1110 00 (h'70). Only four (4) IDs will be available. .... 40
•
Changed Table 15: ADD \ 2 \ bit \ 7 \ Reserved: changed “ Reserved ” to “ OP_LOW ”..................................................... 40
•
Changed Table 15: ADD \ 2 \ bit \ 6 \ Reserved: changed “ Reserved ” to “ OSS_SEL ”.................................................... 40
Copyright © 2009–2019, Texas Instruments Incorporated
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SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com
5 Description (continued)
Serial transmission is optimized by a user-selectable de-emphasis, differential output level select features, and
receiver equalization. EMI is minimized by the use of low voltage differential signaling, receiver drive strength
control, and spread spectrum clocking compatibility. The deserializer may be configured to generate spread
spectrum clock and data on its parallel outputs.
The DS90UR905Q-Q1 serializer is offered in a 48-pin WQFN and the DS90UR906Q-Q1 (deserializer) is offered
in a 60-pin WQFN package. They are specified over the automotive AEC-Q100 grade 2 temperature range of
–40°C to +105°C.
4
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Product Folder Links: DS90UR905Q-Q1 DS90UR906Q-Q1
DS90UR905Q-Q1, DS90UR906Q-Q1
www.ti.com
SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
6 Pin Configuration and Functions
R[3]
R[2]
R[1]
R[0]
27
26
25
31
28
BISTEN
32
VDDIO
R[5]
33
R[4]
R[6]
34
29
R[7]
35
30
G[1]
G[0]
36
RHS Package
48-Pin WQFN
Top View
G[2]
37
24
G[3]
38
23
De-Emph
G[4]
39
22
VDDTX
G[5]
40
21
PDB
G[6]
41
20
DOUT+
G[7]
42
19
DOUT-
B[0]
43
18
RES2
B[1]
44
17
VDDHS
B[2]
45
16
RES1
B[3]
46
15
RES0
B[4]
47
14
VDDP
B[5]
48
13
CONFIG[1]
VODSEL
DS90UR905Q
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
B[6]
B[7]
HS
VS
DE
ID[x]
VDDL
SCL
SDA
PCLK
RFB
CONFIG[0]
DAP = GND
DS90UR905Q-Q1 Serializer Pin Functions (1)
PIN
NAME
I/O, TYPE
NO.
DESCRIPTION
LVCMOS PARALLEL INTERFACE
B[7:0]
DE
G[7:0]
2, 1, 48, 47, 46,
45, 44, 43
I, LVCMOS
with pulldown
BLUE parallel interface data input pins
(MSB = 7, LSB = 0)
5
I, LVCMOS
with pulldown
Data enable input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 PCLKs.
42, 41, 40, 39,
38, 37, 36, 35
I, LVCMOS
with pulldown
GREEN parallel interface data input pins
(MSB = 7, LSB = 0)
HS
3
I, LVCMOS
with pulldown
Horizontal Sync Input
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
control signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the
minimum transition pulse when the control signal filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 PCLKs.
PCLK
10
I, LVCMOS
with pulldown
Pixel clock input
Latch edge set by RFB function.
R[7:0]
34, 33, 32, 29,
28, 27, 26, 25
I, LVCMOS
with pulldown
RED parallel interface data input pins
(MSB = 7, LSB = 0)
4
I, LVCMOS
with pulldown
Vertical sync input
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse
width is 130 PCLKs.
VS
(1)
1 = HIGH, 0 = LOW
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SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
www.ti.com
DS90UR905Q-Q1 Serializer Pin Functions(1) (continued)
PIN
NAME
I/O, TYPE
NO.
DESCRIPTION
CONTROL AND CONFIGURATION
I, LVCMOS
with pulldown
BIST mode — optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
13, 12
I, LVCMOS
with pulldown
Operating modes — pin or register control
Determine the operating mode of the DS90UR905 and interfacing device.
CONFIG[1:0] = 00: interfacing to DS90UR906Q-Q1, control signal filter DISABLED
CONFIG[1:0] = 01: interfacing to DS90UR906Q-Q1, control signal filter ENABLED
CONFIG[1:0] = 10: interfacing to DS90UR124, DS99R124
CONFIG[1:0] = 11: interfacing to DS90C124
De-Emph
23
I, Analog
with pullup
ID[x]
6
I, Analog
BISTEN
CONFIG[1:0]
31
De-emphasis control — pin or register control
De-emph = open (float) - disabled
To enable de-emphasis, tie a resistor from this pin to GND or control via register (see
Table 2).
Serial control bus device ID address select — optional
Resistor-to-ground and 10-kΩ pullup to 1.8-V rail (see Table 11).
21
I, LVCMOS
with pulldown
Power-down mode input
PDB = 1, serializer is enabled (normal operation).
Refer to Power Up Requirements and PDB Pin.
PDB = 0, serializer is powered down
When the serializer is in the power-down state, the driver outputs (DOUT±) are both
logic high, the PLL is shutdown, IDD is minimized. Control registers are RESET.
18, 16, 15
I, LVCMOS
with pulldown
Reserved - tie LOW
RFB
11
I, LVCMOS
with pulldown
Pixel clock input latch edge select — pin or register control
RFB = 1, parallel interface data and control signals are latched on the rising clock
edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock
edge.
SCL
8
I, LVCMOS
SDA
9
I/O, LVCMOS
Open-Drain
Serial control bus data input/output - optional
SDA requires an external pullup resistor VDDIO.
VODSEL
24
I, LVCMOS
with pulldown
Differential driver output voltage select — pin or register control
VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typical) — long cable / de-emp
applications
VODSEL = 0, LVDS VOD is 280 mV, 560 mVp-p (typical)
PDB
RES[2:0]
Serial control bus clock input - optional
SCL requires an external pullup resistor to VDDIO.
FPD-LINK II SERIAL INTERFACE
DOUT+
20
O, LVDS
True output
The output must be AC-coupled with a 100-nF capacitor.
DOUT-
19
O, LVDS
Inverting output
The output must be AC-coupled with a 100-nF capacitor.
POWER AND GROUND (2)
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
VDDHS
17
Power
TX high-speed logic power, 1.8 V ±5%
VDDL
7
Power
Logic power, 1.8 V ±5%
VDDP
14
Power
PLL power, 1.8 V ±5%
VDDIO
30
Power
LVCMOS I/O power, 1.8 V ±5% or 3.3 V ±10%
VDDTX
22
Power
Output Driver power, 1.8 V ±5%
GND
(2)
6
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
R[6]/SSC[3]
R[7]
LOCK
NC
32
31
R[5]/SSC[2]
33
R[4]/SSC[1]
35
34
R[3]/SSC[0]
36
40
37
R[1]/MAP_SEL[1]
41
R[2]
R[0]/MAP_SEL[0]
42
VDDIO
PASS/OP_LOW
43
38
VDDR
44
39
NC
BISTEN
45
NKB Package
60-Pin WQFN
Top View
NC
46
30
NC
RES
47
29
VDDL
VDDIR
48
28
G[0]/OSC_SEL[0]
RIN+
49
27
G[1]/OSC_SEL[1]
RIN-
50
26
G[2]/OSC_SEL[2]
CMF
51
25
G[3]
CMLOUTP
52
24
VDDIO
CMLOUTN
53
TOP VIEW
23
G[4]/EQ[0]
VDDCMLO
54
DAP = GND
22
G[5]/EQ[1]
VDDR
55
21
G[6]/EQ[2]
ID[x]
56
20
G[7]/EQ[3]
VDDPR
57
19
B[0]
VDDSC
58
18
B[1]/RFB
PDB
59
17
B[2]/OSS_SEL
NC
60
16
NC
DS90UR906Q
12
13
14
15
B[4]/LF_MODE
VDDIO
B[3]/OS_DATA
NC
B[5]/OS_PCLK
8
HS
11
7
VS
9
6
DE
10
5
PCLK
B[7]/CONFIG[0]
4
B[6]/CONFIG[1]
3
SCL
2
VDDSC
1
NC
SDA
BOLD PIN NAME ± indicates I/O strap
pin associated with output pin
DS90UR906Q-Q1 Deserializer Pin Functions (1)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
B[7:0]
DE
G[7:0]
HS
(1)
9, 10, 11,
12, 14, 17,
18, 19
I, STRAP,
O, LVCMOS
BLUE parallel interface data output pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins
are inputs during power up (see Deserializer Strap Input Pins).
6
O, LVCMOS
Data enable output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the control
signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the control signal filter is disabled
(CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs.
20, 21, 22,
23, 25, 26,
27, 28
I, STRAP,
O, LVCMOS
GREEN parallel interface data output pins (MSB = 7, LSB = 0)
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins
are inputs during power up (see Deserializer Strap Input Pins).
O, LVCMOS
Horizontal sync output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the control
signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the control signal filter is disabled
(CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 PCLKs.
8
1 = HIGH, 0 = LOW
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DS90UR906Q-Q1 Deserializer Pin Functions(1) (continued)
PIN
I/O, TYPE
DESCRIPTION
32
O, LVCMOS
LOCK status output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, RGB[7:0], HS, VS,
DE and PCLK output states are controlled by OSS_SEL (see Table 6). May be used as link
status or to flag when video data is active (ON/OFF).
PASS
42
O, LVCMOS
PASS output (BIST mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
PCLK
5
O, LVCMOS
Pixel clock output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Strobe
edge set by RFB function.
R[7:0]
33, 34, 35,
36, 37, 39,
40, 41
I, STRAP,
O, LVCMOS
RED parallel interface data output pins (MSB = 7, LSB = 0)
In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 6). These pins
are inputs during power up (see Deserializer Strap Input Pins).
O, LVCMOS
Vertical sync output
In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 6). Video
control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130
PCLKs.
NAME
NO.
LOCK
VS
7
CONTROL AND CONFIGURATION — STRAP PINS
For a HIGH state, use a 10-kΩ pullup to VDDIO; for a LOW state, the IO includes an internal pulldown. The STRAP pins are read upon
power up and set device configuration. Pin Number listed along with shared RGB output name in square brackets.
CONFIG[1:0]
10 [B6],
9 [B7]
Operating modes — pin or register control
These pins determine the operating mode of the DS90UR906 and interfacing device.
STRAP
CONFIG[1:0] = 00: interfacing to DS90UR905Q-Q1, control signal filter DISABLED
I, LVCMOS
CONFIG[1:0] = 01: interfacing to DS90UR905Q-Q1, control signal filter ENABLED
with pulldown
CONFIG[1:0] = 10: interfacing to DS90UR241
CONFIG[1:0] = 11: interfacing to DS90C241
EQ[3:0]
20 [G7],
21 [G6],
22 [G5],
23 [G4]
STRAP
I, LVCMOS Receiver input equalization — pin or register control (see Table 3).
with pulldown
LF_MODE
12 [B4]
SSCG low-frequency mode — pin or register control
STRAP
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
I, LVCMOS
LF_MODE = 1, SSCG in low-frequency mode (PCLK = 5 to 20 MHz)
with pulldown
LF_MODE = 0, SSCG in high-frequency mode (PCLK = 20 to 65 MHz)
MAP_SEL[1:0]
40 [R1],
41 [R0]
STRAP
Bit mapping backward compatibility / DS90UR241 options — pin or register control
I, LVCMOS
Normal setting to b'00 (see Table 9).
with pulldown
OP_LOW
42 PASS
Outputs held LOW when LOCK = 1 — pin or register control
See (2)
STRAP
OP_LOW = 1: all outputs are held LOW during power up until released by programming
I, LVCMOS OP_LOW release / set register HIGH
with pulldown See (3)
See Figure 30 and Figure 31.
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
OS_DATA
14 [B3]
STRAP
Data output slew select — pin or register control
I, LVCMOS OS_DATA = 1, increased DATA slew
with pulldown OS_DATA = 0, normal (default)
OSC_SEL[2:0]
26 [G2],
27 [G1],
28 [G0]
STRAP
I, LVCMOS Oscillator select — pin or register control (see Table 7 and Table 8).
with pulldown
OS_PCLK
11 [B5]
STRAP
PCLK output slew select — pin or register control
I, LVCMOS OS_PCLK = 1, increased PCLK slew
with pulldown OS_PCLK = 0, normal (default)
OSS_SEL
17 [B2]
Output sleep state select — pin or register control
STRAP
See (4)
I, LVCMOS
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in power
with pulldown
down (Sleep) (see Table 6).
(2)
(3)
(4)
8
It is not recommended to use any other strap options with this strap function
Before the device is powered up, the outputs are in tri-state.
OSS_SEL strap cannot be used if OP_LOW =1
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DS90UR906Q-Q1 Deserializer Pin Functions(1) (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
RFB
18 [B1]
STRAP
Pixel clock output strobe edge select — pin or register control
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
with pulldown RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
SSC[3:0]
34 [R6],
35 [R5],
36 [R4],
37 R[3]
STRAP
Spread spectrum clock generation (SSCG) range select — pin or register control
I, LVCMOS
See Table 4 and Table 5.
with pulldown
CONTROL AND CONFIGURATION
BIST enable input — optional
I, LVCMOS
BISTEN = 1, BIST is enabled
with pulldown
BISTEN = 0, BIST is disabled
BISTEN
44
ID[x]
56
I, Analog
1, 15, 16,
30, 31, 45,
46, 60
—
NC
Serial control bus device ID address select — optional
Resistor-to-ground and 10-kΩ pullup to 1.8-V rail (see Table 10).
Not connected
Leave pin open (float)
PDB
59
Power-down mode input
PDB = 1, deserializer is enabled (normal operation).
I, LVCMOS Refer to Power Up Requirements and PDB Pin.
with pulldown PDB = 0, deserializer is in power down.
When the deserializer is in the power-down state, the LVCMOS output state is determined by
Table 6. Control Registers are RESET.
RES
47
I, LVCMOS
Reserved - tie LOW
with pulldown
SCL
3
SDA
2
I, LVCMOS
Serial control bus clock input — optional
SCL requires an external pullup resistor to VDDIO.
I/O, LVCMOS Serial control bus data input/output — optional
Open-Drain SDA requires an external pullup resistor to VDDIO.
FPD-LINK II SERIAL INTERFACE
CMF
51
I, Analog
Common-mode filter
VCM center-tap is a virtual ground which may be AC coupled to ground to increase receiver
common-mode noise immunity. Recommended value is 0.1 μF or higher.
CMLOUTN
53
O, LVDS
Test monitor pin — EQ waveform
NC or connect to test point. Requires serial bus control to enable.
CMLOUTP
52
O, LVDS
Test monitor pin — EQ waveform
NC or connect to test point. Requires serial bus control to enable.
RIN+
49
I, LVDS
True input. The input must be AC coupled with a 100-nF capacitor.
RIN-
50
I, LVDS
Inverting input. The input must be AC coupled with a 100-nF capacitor.
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
VDDCMLO
54
Power
RX high-speed logic power, 1.8 V ±5%
VDDL
29
Power
Logic power, 1.8 V ±5%
VDDIO
13, 24, 38
Power
LVCMOS I/O power, 1.8 V ±5% or 3.3 V ±10% (VDDIO)
VDDIR
48
Power
Input power, 1.8 V ±5%
VDDPR
57
Power
PLL power, 1.8 V ±5%
VDDR
43, 55
Power
RX high-speed logic power, 1.8 V ±5%
VDDSC
4, 58
Power
SSCG power, 1.8 V ±5%
POWER AND GROUND (5)
GND
(5)
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3).
MIN
MAX
UNIT
Supply voltage – VDDn (1.8 V)
–0.3
2.5
V
Supply voltage – VDDIO
–0.3
4
V
LVCMOS I/O voltage
–0.3
VDDIO + 0.3
V
Receiver input voltage
–0.3
VDD + 0.3
V
Driver output voltage
–0.3
VDD + 0.3
V
150
°C
Maximum power dissipation capacity at 25°C
215
mW
Derate above 25°C
1/θJA
mW/°C
Maximum power dissipation capacity at 25°C
470
mW
Derate above 25°C
1/θJA
mW/°C
150
°C
Junction temperature
48L RHS package
60L NKB package
Storage temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office or Distributors for availability and
specifications.
For soldering specifications see product folder at www.ti.com and SNOA549.
7.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
±8000
Charged-device model (CDM), per AEC Q100-011
±1000
Machine Model (MM)
ISO10605 (2)
V(ESD)
Electrostatic discharge
ISO10605 (3)
IEC 61000-4-2 (3)
(1)
(2)
(3)
10
UNIT
±250
Air Discharge (DOUT+, DOUT−)
≥±30000
Contact Discharge (DOUT+, DOUT−)
≥±10000
Air Discharge (RIN+, RIN−)
≥±30000
Contact Discharge (RIN+, RIN−)
≥±10000
Air Discharge (DOUT+, DOUT−)
≥±15000
Contact Discharge (DOUT+, DOUT−)
≥±10000
Air Discharge (RIN+, RIN−)
≥±15000
Contact Discharge (RIN+, RIN−)
≥±10000
Air Discharge (DOUT+, DOUT−)
≥±25000
Contact Discharge (DOUT+, DOUT−)
≥±8000
Air Discharge (RIN+, RIN−)
≥±25000
Contact Discharge (RIN+, RIN−)
≥±8000
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
RD = 2 kΩ, CS = 150 pF or RD = 2 kΩ, CS = 330 pF or RD = 330 Ω, CS = 150 pF
RD = 330 Ω, CS = 330 pF
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS supply voltage (VDDIO)
1.71
1.8
1.89
3
3.3
3.6
−40
25
105
OR LVCMOS supply voltage (VDDIO)
Operating free-air temperature (TA)
PCLK clock frequency
5
Supply noise (1)
(1)
V
°C
65
MHz
50
mVP-P
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8-V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the serializer and output of the deserializer
with 10 meter cable shows no error when the noise frequency on the serializer is less than 750 kHz. The deserializer on the other hand
shows no error when the noise frequency is less than 400 kHz.
7.4 Thermal Information
THERMAL METRIC (1)
DS90UR905Q-Q1
DS90UR906Q-Q1
RHS (WQFN)
NKB (WQFN)
UNIT
48 PINS
60 PINS
RθJA
Junction-to-ambient thermal resistance (2)
30.3
26.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (2)
11.5
9.1
°C/W
RθJB
Junction-to-board thermal resistance
7.3
6.0
°C/W
ψJT
Junction-to-top characterization parameter
0.1
0.1
°C/W
ψJB
Junction-to-board characterization parameter
7.3
6.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.7
1.5
°C/W
(1)
(2)
7.5
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Based on nine thermal vias.
Serializer DC Electrical Characteristics
over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN / FREQ
MIN
TYP
MAX
UNIT
2.2
VDDIO
V
0.65 ×
VDDIO
VDDIO
V
GND
0.8
V
GND
0.35 ×
VDDIO
V
LVCMOS INPUT DC SPECIFICATIONS
VDDIO = 3.0 to 3.6 V
VIH
High-level input voltage
VIL
Low-level input voltage
VDDIO = 1.71 to 1.89 V
VDDIO = 3.0 to 3.6 V
IIN
(1)
(2)
(3)
Input current
VDDIO = 1.71 to 1.89 V
VIN = 0 V or VDDIO
VDDIO = 3.0
to 3.6 V
VDDIO = 1.7
to 1.89 V
R[7:0],
G[7:0],
B[7:0],
HS, VS, DE,
PCLK, PDB,
VODSEL,
RFB,
CONFIG[1:0],BIS
TEN
–15
±1
+15
μA
–15
±1
+15
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, TA = 25°C, and at the Recommended Operating Conditions at the
time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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Serializer DC Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN / FREQ
MIN
TYP
MAX
±205
±280
±355
±320
±420
±520
UNIT
LVDS DRIVER DC SPECIFICATIONS
VODSEL = 0
VOD
Differential output
voltage
VODp-p
Differential output
voltage
(DOUT+) – (DOUT-)
ΔVOD
Output voltage
unbalance
VOS
Offset voltage – singleRL = 100 Ω,
ended
De-emph = disabled
at TP A and B, Figure 1
ΔVOS
Offset voltage
unbalance
RL = 100 Ω, De-emph = disabled
Single-ended
at TP A and B, Figure 1
IOS
Output short circuit
current
RT
Internal termination
resistor
RL = 100 Ω,
De-emph = disabled,
Figure 2
DOUT+, DOUT–
VODSEL = 1
VODSEL = 0
560
DOUT+, DOUT–
VODSEL = 1
1
DOUT+, DOUT–
VODSEL = 0
mVp-p
840
RL = 100 Ω, De-emph = disabled, VODSEL = L
DOUT± = 0 V,
De-emph = disabled
mV
50
mV
1.65
VODSEL = 1
V
1.575
1
mV
–36
mA
DOUT+, DOUT–
VODSEL = 0
80
100
120
75
85
3
5
11
15
65
75
3
5
Ω
SUPPLY CURRENT
IDDT1
IDDIOT1
IDDT2
Serializer
supply current
(includes load current)
RL = 100 Ω, f = 65 MHz
IDDIOT2
IDDZ
IDDIOZ
7.6
Serializer
cupply current power
down
Checker Board Pattern,
De-emph = 3 KΩ
VODSEL = H, Figure 9
Checker Board Pattern,
De-emph = 6 KΩ,
VODSEL = L, Figure 9
VDD = 1.89 V
All VDD pins
VDDIO = 1.89 V
VDDIO
VDDIO = 3.6 V
VDD = 1.89 V
All VDD pins
VDDIO = 1.89 V
VDDIO
VDDIO = 3.6 V
VDD = 1.89 V
PDB = 0 V , (All other
LVCMOS Inputs = 0 V)
All VDD pins
VDDIO = 1.89 V
VDDIO
VDDIO = 3.6 V
11
15
40
1000
5
10
10
20
mA
mA
μA
Deserializer DC Electrical Characteristics
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN / FREQ
MIN
PDB, BISTEN
TYP
MAX
UNIT
2.2
VDDIO
V
GND
0.8
V
15
μA
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6 V
VIH
High-level input voltage
VIL
Low-level input voltage
IIN
Input current
VIN = 0 V or VDDIO
VOH
High-level output voltage
IOH = −2 mA,
OS_PCLK/DATA = L
R[7:0], G[7:0],
B[7:0], HS,VS,
DE, PCLK,
LOCK, PASS
VOL
Low-level output voltage
IOL = +2 mA,
OS_PCLK/DATA = L
R[7:0], G[7:0],
B[7:0], HS, VS,
DE,PCLK,
LOCK, PASS
Output short circuit current
VDDIO = 3.3 V
VOUT = 0 V,
OS_PCLK/DATA = L/H
PCLK
36
mA
Output short circuit current
VDDIO = 3.3 V
VOUT = 0 V,
OS_PCLK/DATA = L/H
Deserializer
Outputs
37
mA
TRI-STATE output current
PDB = 0 V, OSS_SEL = 0
Outputs
V, VOUT = H
IOS
IOZ
12
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−15
±1
2.4
VDDIO
GND
−15
V
0.4
15
V
µA
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SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
Deserializer DC Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN / FREQ
MIN
TYP
MAX
UNIT
1.235
VDDIO
V
GND
0.595
V
15
μA
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89 V
VIH
High-level input voltage
VIL
Low-level input voltage
IIN
Input current
VIN = 0 V or VDDIO
VOH
High-level output voltage
IOH = −2 mA,
OS_PCLK/DATA = L/H
VOL
Low-level output voltage
IOL = +2 mA,
OS_PCLK/DATA = L/H
IOS
IOZ
PDB, BISTEN
Output short circuit current
R[7:0], G[7:0],
B[7:0], HS, VS,
DE, PCLK,
LOCK, PASS
−15
±1
VDDIO −
0.45
VDDIO
GND
0.45
V
VDDIO = 1.8 V
VOUT = 0 V,
OS_PCLK/DATA = L/H
PCLK
18
mA
VDDIO = 1.8 V
VOUT = 0 V,
OS_PCLK/DATA = L/H
DATA
18
mA
PDB = 0 V, OSS_SEL = 0
Outputs
V, VOUT = 0 V or VDDIO
TRI-STATE output current
V
–15
15
µA
LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential input threshold high
voltage
VTL
Differential input threshold low
voltage
VCM
Common-mode voltage, internal
VBIAS
IIN
Input current
RT
Internal termination resistor
VCM = +1.2 V (Internal
VBIAS)
RIN+, RIN-
50
mV
–50
mV
1.2
VIN = 0 V or VDDIO
–15
RIN+, RIN-
80
100
V
15
µA
120
Ω
CMLOUTP/N DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
VOD
Differential output voltage
RL = 100 Ω
VOS
Offset voltage
Single-ended
RL = 100 Ω
RT
Internal termination resistor
CMLOUTP,
CMLOUTN
CMLOUTP,
CMLOUTN
80
542
mV
1.4
V
100
120
Ω
93
110
mA
33
45
mA
62
75
mA
40
3000
µA
5
50
µA
10
100
µA
SUPPLY CURRENT
IDD1
IDDIO1
Deserializer
supply current
(includes load current)
Checker Board Pattern,
OS_PCLK/DATA = H,
EQ = 001,
SSCG=ON
CMLOUTP/N = enabled
CL = 4 pF, Figure 9
Deserializer supply current power
down
PDB = 0 V, All other
LVCMOS Inputs = 0 V
IDDZ
IDDIOZ
All VDD pins
VDDIO
All VDD pins
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VDDIO
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7.7 DC and AC Serial Control Bus Characteristics
over 3.3-V supply and temperature ranges unless otherwise specified.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
Input high-level voltage
SDA and SCL
2.2
VDDIO
VIL
Input low-level voltage
SDA and SCL
GND
0.8
VHY
Input hysteresis
VOL
Output low-level voltage (1)
>50
SDA, IOL = 1.25 mA
Iin
SDA or SCL, Vin = VDDIO or GND
Cin
(1)
0
Input capacitance
–15
SDA or SCL
V
mV
0.4
V
15
µA
0
100
kHz
Fast Mode
>0
400
kHz
Standard Mode
4.7
µs
Fast Mode
1.3
µs
tLOW
SCL low period
tHIGH
SCL high period
Standard Mode
tHD;STA
Hold time for a start or a
repeated start condition,
Figure 18
tSU:STA
4
µs
0.6
µs
4
us
Fast Mode
0.6
µs
Set-up time for a start or a
repeated start condition,
Figure 18
Standard Mode
4.7
µs
Fast Mode
0.6
µs
tHD;DAT
Data hold time,
Figure 18
Standard Mode
0
3.45
µs
Fast Mode
0
0.9
µs
tSU;DAT
Data set-up time,
Figure 18
Standard Mode
250
ns
Fast Mode
100
ns
14
Standard Mode
Fast Mode
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Timing Requirements for Serial Control Bus (continued)
over 3.3-V supply and temperature ranges unless otherwise specified.
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Set-up time for STOP condition,
Figure 18
Standard Mode
4
µs
Fast Mode
0.6
µs
tBUF
Bus free time between STOP
and START, Figure 18
Standard Mode
4.7
µs
Fast Mode
1.3
tr
SCL and SDA rise time,
Figure 18
Standard Mode
SCL and SDA fall time,
Figure 18
tSU;STO
tf
µs
1000
µs
Fast Mode
300
ns
Standard Mode
300
ns
Fast mode
300
ns
MAX
UNIT
7.11 Switching Characteristics: Serializer
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERS
TEST CONDITIONS
MIN
TYP
Serializer output low-to-high
transition time, Figure 3
RL = 100 Ω, De-emphasis = disabled, VODSEL = 0
200
ps
RL = 100 Ω, De-emphasis = disabled, VODSEL = 1
200
ps
tHLT
Serializer output high-to-low
transition time, Figure 3
RL = 100 Ω, De-emphasis = disabled, VODSEL = 0
200
ps
RL = 100 Ω, De-emphasis = disabled, VODSEL = 1
200
ps
tDIS
Input data – set-up time,
Figure 4
RGB[7:0], HS, VS, DE to PCLK
2
ns
tDIH
Input data – hold time,
Figure 4
PCLK to RGB[7:0], HS, VS, DE
2
ns
tXZD
Serializer output active to OFF
delay, Figure 6 (1)
tPLD (2)
Serializer PLL lock time,
Figure 5 (1) (3)
tSD
Serializer delay – latency,
Figure 7 (1)
tLHT
Serializer output total jitter,
Figure 8
tDJIT
λSTXBW
δSTX
(1)
(2)
(3)
(4)
Serializer jitter transfer
Function –3-dB bandwidth
Serializer jitter transfer
function peaking
8
15
ns
RL = 100 Ω
1.4
10
ms
RL = 100 Ω
144 × T
145 × T
ns
RL = 100 Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 65 MHz
0.28
UI (4)
RL = 100 Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 43 MHz
0.27
UI
RL = 100 Ω, De-Emph = disabled,
RANDOM pattern, PCLK = 5 MHz
0.35
UI
PCLK = 65 MHz
3
MHz
PCLK = 43 MHz
2.3
MHz
PCLK = 20 MHz
1.3
MHz
PCLK = 5 MHz
650
kHz
PCLK = 65 MHz
0.838
dB
PCLK = 43 MHz
0.825
dB
PCLK = 20 MHz
0.826
dB
PCLK = 5 MHz
0.278
dB
Specification is ensured by characterization and is not tested in production.
tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
When the serializer output is at TRI-STATE the deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require tPLD
UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / [28 × PCLK]). The UI scales with PCLK frequency.
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7.12 Switching Characteristics: Deserializer
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERS
tRCP
TEST CONDITIONS
PCLK output period
tRCP = tTCP
PIN / FREQ
PCLK
SSCG=OFF, 5–65 MHz
tRDC
PCLK output duty cycle
SSCG=ON, 5–20 MHz
PCLK
SSCG=ON, 20–65 MHz
tCLH
LVCMOS
Low-to-high transition time,
Figure 10
tCHL
LVCMOS
High-to-low transition time,
Figure 10
VDDIO = 1.8 V, CL = 4 pF
VDDIO = 3.3 V, CL = 4 pF
VDDIO = 1.8 V
CL = 4 pF, OS_PCLK/DATA = L
VDDIO = 3.3 V
CL = 4 pF, OS_PCLK/DATA = H
MIN
TYP
MAX
UNIT
ns
15.38
T
200
43%
50%
57%
35%
59%
65%
40%
53%
60%
PCLK/RGB[7:0], HS,
VS, DE
PCLK/RGB[7:0], HS,
VS, DE
2.1
ns
2.0
ns
1.6
ns
1.5
ns
tROS
Data valid before PCLK –
set-up time Figure 14
VDDIO = 1.71 to 1.89 V or 3.0 to
3.6 V
CL = 4pF (lumped load)
RGB[7:0], HS, VS, DE
0.27
0.45
T
tROH
Data valid after PCLK – hold
time Figure 14
VDDIO = 1.71 to 1.89 V or 3.0 to
3.6 V
CL = 4pF (lumped load)
RGB[7:0], HS, VS, DE
0.4
0.55
T
SSC[3:0] = 0000 (OFF) (2)
PCLK = 5 MHz
tDDLT (1)
SSC[3:0] = 0000 (OFF)
Deserializer lock time,
Figure 13
(2)
PCLK = 65 MHz
4
ms
PCLK = 5 MHz
30
ms
SSC[3:0] = ON (2)
PCLK = 65 MHz
6
ms
tDD
SSC[3:0] = 0000 (OFF) (2)
tDPJ
Deserializer period jitter
SSC[3:0] = OFF (3) (4) (5)
Deserializer cycle-to-cycle
jitter
SSC[3:0] = OFF (6) (7) (5)
EQ = OFF,
SSCG = OFF,
PCLK = 65 MHz
Deserializer input jitter
tolerance, Figure 16
tIJT
ms
SSC[3:0] = ON (2)
Deserializer delay – latency,
Figure 11
tDCCJ
3
139 × T
140 × T
ns
PCLK = 5 MHz
975
1700
ps
PCLK = 10 MHz
500
1000
ps
PCLK = 65 MHz
550
1250
ps
PCLK = 5 MHz
675
1150
ps
PCLK = 10 MHz
375
900
ps
PCLK = 65 MHz
500
1150
ps
for jitter freq < 2 MHz
0.9
UI
for jitter freq > 6 MHz
0.5
UI
BIST Mode
tPASS
BIST PASS valid time,
BISTEN = 1, Figure 17
1
10
µs
SSCG Mode
fDEV
Spread spectrum clocking
deviation frequency
Under typical conditions
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
±0.5%
±2%
fMOD
Spread spectrum clocking
modulation frequency
Under typical conditions
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
8
100
(1)
(2)
(3)
(4)
(5)
(6)
(7)
16
kHz
tDDLT is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.
tDPJ is the maximum amount the period is allowed to deviate over many samples.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
Specification is ensured by characterization and is not tested in production.
tDCCJ is the maximum amount of jitter between adjacent clock cycles.
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A
A'
CA
Scope
50:
50:
CB
B
B'
50:
50:
Single-Ended
Figure 1. Serializer Test Circuit
DOUT+
VOD-
VOD+
DOUT-
VOS
Differential
GND
VOD+
(DOUT+) - (DOUT+)
0V
VODp-p
VOD-
Figure 2. Serializer Output Waveforms
+VOD
80%
(DOUT+) - (DOUT-)
0V
20%
-VOD
tLLHT
tLHLT
Figure 3. Serializer Output Transition Times
tTCIH
tTCP
PCLK
w/ RFB = L
tTCIL
80%
20%
1/2 VDDIO
tCLKT
tDIS
GND
tCLKT
VDDIO
VIHmin
VILmax
RGB[n],
VS, HS, DE
VDDIO
GND
tDIH
Figure 4. Serializer Input PCLK Waveform and Set and Hold Times
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PDB
PCLK
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1/2 VDDIO
"X"
active
tPLD
DOUT
(Diff.)
Driver On
Driver OFF, VOD = 0V
Figure 5. Serializer Lock Time
1/2 VDDIO
PDB
PCLK
active
"X"
tXZD
DOUT
(Diff.)
active
Driver OFF, VOD = 0V
Figure 6. Serializer Disable Time
RGB[7:0],
HS, VS, DE
SYMBOL N
SYMBOL N+1
tSD
PCLK
(RFB = L)
START
BIT
DOUT
0
(Diff.)
STOP START
BIT BIT
1
2
27
SYMBOL N-1
0
STOP
BIT
1
2
27
SYMBOL N
Figure 7. Serializer Latency Delay
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tDJIT
tDJIT
VOD (+)
DOUT
(Diff.)
TxOUT_E_O
0V
VOD (-)
tBIT (1 UI)
Figure 8. Serializer Output Jitter
VDDIO
PCLK
w/ RFB = L
GND
VDDIO
RGB[n] (odd),
VS, HS
GND
VDDIO
RGB[n] (even),
DE
GND
Figure 9. Checkerboard Data Pattern
VDDIO
80%
20%
GND
tCLH
tCHL
Figure 10. Deserializer LVCMOS Transition Times
START
BIT
RIN
(Diff.)
0
STOP START
BIT BIT
1
2
SYMBOL N
27
0
STOP
BIT
1
2
SYMBOL N+1
27
tDD
PCLK
(RFB = L)
RGB[7:0],
HS, VS, DE
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 11. Deserializer Delay – Latency
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1/2 VDDIO
PDB
RIN
(Diff.)
active
"X"
tXZR
PCLK,
RGB[7:0],
DE, HS, VS,
PASS, LOCK
active
Z (TRI-STATE)
Figure 12. Deserializer Disable Time (OSS_SEL = 0)
PDB
2.0V
0.8V
RIN
(Diff.)
'RQ¶W &DUH
tDDLT
LOCK
TRI-STATE
or LOW
Z or L
tRxZ
RGB[7:0],
HS, VS, DE
TRI-STATE or LOW or Pulled Up
PCLK
(RFB = L)
Z or L or PU
TRI-STATE or LOW
OFF
IN LOCK TIME
Z or L
ACTIVE
OFF
Figure 13. Deserializer PLL Lock Times and PDB TRI-STATE Delay
VDDIO
PCLK
w/ RFB = H
1/2 VDDIO
GND
VDDIO
RGB[n],
VS, HS, DE
1/2 VDDIO
GND
tROS
tROH
Figure 14. Deserializer Output Data Valid (Set-up and Hold) Times With SSCG = Off
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VDDIO
PCLK
w/ RFB = H
1/2 VDDIO
GND
RGB[n],
VS, HS, DE
1/2 VDDIO
VDDIO
1/2 VDDIO
tROS
GND
tROH
Figure 15. Deserializer Output Data Valid (Set-up and Hold) Times With SSCG = On
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RxIN_TOL
Left
VTH
0V
VTL
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tRJIT
= RxIN_TOL (Left + Right)
- tRJIT
Sampling Window = 1 UI
Figure 16. Receiver Input Jitter Tolerance
BISTEN
1/2 VDDIO
tPASS
PASS
(w/ errors)
1/2 VDDIO
Current BIST Test - Toggle on Error
Prior BIST Result
Result Held
Figure 17. BIST PASS Waveform
SDA
tLOW
tf
tBUF
tHD;STA
tr
tf
tr
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 18. Serial Control Bus Timing Diagram
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7.13 Typical Characteristics
Figure 19. Differential Output Voltage vs Ambient
Temperature
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Figure 20. CMLOUT VOD vs Ambient Temperature
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8 Detailed Description
8.1 Overview
The DS90UR90xQ-Q1 chipset transmits and receives 27-bits of data (24-high speed color bits and 3 low speed
video control signals) over a single serial FPD-Link II pair operating at 140Mbps to 1.82Gbps. The serial stream
also contains an embedded clock, video control signals and the DC-balance information which enhances signal
quality and supports AC coupling. The pair is intended for use with each other but is backward-compatible with
previous generations of FPD-Link II as well.
The deserializer can attain lock to a data stream without the use of a separate reference clock source, which
greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer
regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming
serial stream without the need of special training patterns or sync characters. The deserializer recovers the clock
and data by extracting the embedded clock information, validating and then deserializing the incoming data
stream providing a parallel LVCMOS video bus to the display.
The DS90UR90xQ-Q1 chipset can operate in 24-bit color depth (with VS,HS,DE encoded in the DCA bit) or in
18-bit color depth (with VS, HS, DE encoded in DCA or mapped into the high-speed data bits). In 18–bit color
applications, the three video signals maybe sent encoded via the DCA bit (restrictions apply) or sent as data bits
along with three additional general-purpose signals.
Functional Block Diagrams shows the diagrams for the chipsets.
8.2 Functional Block Diagrams
RFB
PCLK
PLL
Parallel to Serial
24
Input Latch
RGB[7:0]
HS
VS
DE
DC Balance Encoder
VODSEL
De-Emph
DOUT+
DOUT-
Pattern
Generator
CONFIG[1:0]
PDB
SCL
SCA
ID[x]
Timing and
Control
BISTEN
Figure 21. DS90UR905Q-Q1 – Serializer
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Functional Block Diagrams (continued)
STRAP INPUT
CONFIG [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
SSCG
RIN+
RIN-
BISTEN
PDB
SCL
SCA
ID[x]
Timing and
Control
24
RGB [7:0]
Output Latch
Serial to Parallel
DC Balance Decoder
CMF
HS
VS
DE
Error
Detector
PASS
Clock and
Data
Recovery
PCLK
LOCK
STRAP INPUT
OP_LOW
Figure 22. DS90UR906Q-Q1 – Deserializer
8.3 Feature Description
8.3.1 Data Transfer
The DS90UR90xQ-Q1 chipset will transmit and receive a pixel of data in the following format: C1 and C0
represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain
the scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term
DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data
integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB
coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 23
illustrates the serial stream per PCLK cycle.
NOTE
The figure only illustrates the bits but does not actually represent the bit location as the
bits are scrambled and balanced continuously.
C
1
b
0
b
1
D
C
B
b
2
b
1
2
b
3
b
1
3
b
4
b
1
4
b
5
b
1
5
b
6
b
1
6
b
7
b
1
7
b
8
b
1
8
b
9
b
1
9
b
1
0
b
2
0
b
1
1
b
2
1
D
C
A
b
2
2
b
2
3
C
0
Figure 23. FPD-Link II Serial Stream (DS90UR90xQ-Q1)
24
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Feature Description (continued)
8.3.2 Video Control Signal Filter — Serializer and Deserializer
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK
or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS: Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals (see Figure 24).
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 24. Video Control Signal Filter Waveform
8.3.3 Serializer Functional Description
The serializer converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built-In Self Test (BIST) mode. The device can be configured via external pins or
through the optional serial control bus. The serializer features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the FPD-Link II data coding that
provides randomization, scrambling, and DC balancing of the video data. The serializer includes multiple features
to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the
data and also the system spread spectrum PCLK support. The serializer features power saving features with a
sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
8.3.3.1 EMI Reduction Features
8.3.3.1.1 Serializer Spread Spectrum Compatibility
The serializer PCLK is capable of tracking spread spectrum clocking (SSC) from a host source. The PCLK will
accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The
maximum conditions for the PCLK input are: a modulation frequency of 35 kHz and amplitude deviations of ±2%
(4% total).
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Feature Description (continued)
8.3.3.2 Signal Quality Enhancers
8.3.3.2.1 Serializer VOD Select (VODSEL)
The serializer differential output voltage may be increased by setting the VODSEL pin High. When VODSEL is
Low, the VOD is at the standard (default) level. When VODSEL is High, the DC VOD is increased in level. The
increased VOD is useful in extremely high noise environments and also on extra long cable length applications.
When using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially
with the larger de-emphasis settings. This feature may be controlled by the external pin or by register.
Table 1. Differential Output Voltage
INPUT
EFFECT
VODSEL
VOD (mV)
VOD (mVp-p)
H
±420
840
L
±280
560
8.3.3.2.2 Serializer De-Emphasis (De-Emph)
The De-Emph pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the
serializer drives. This is useful to counteract loading effects of long or lossy cables. This pin should be left open
for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by
connecting a resistor on this pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When
using De-Emphasis, TI recommends to set VODSEL = H.
Table 2. De-Emphasis Resistor Value
RESISTOR VALUE (KΩ)
DE-EMPHASIS SETTING
Open
Disabled
0.6
–12 dB
1.0
–9 dB
2.0
–6 dB
5.0
–3 dB
0.00
VDD = 1.8V,
-2.00
TA = 25oC
DE-EMPH (dB)
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
R VALUE - LOG SCALE (:)
Figure 25. De-Emph vs. R value
8.3.3.3 Power-Saving Features
8.3.3.3.1 Serializer Power-down Feature (PDB)
The serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the host
and is used to save power, disabling the link when the display is not needed. In the power-down mode, the highspeed driver outputs are both pulled to VDD and present a 0-V VOD state.
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NOTE
In power down, the optional Serial Bus Control Registers are RESET.
8.3.3.3.2 Serializer Stop Clock Feature
The serializer will enter a low power SLEEP state when the PCLK is stopped. A STOP condition is detected
when the input clock frequency is less than 3 MHz. The clock should be held at a static LOW or HIGH state.
When the PCLK starts again, the Ser will then lock to the valid input PCLK and then transmits the RGB data to
the deserializer.
NOTE
In STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
8.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
The serializer parallel bus and serial bus interface can operate with 1.8 V or 3.3 V levels (VDDIO) for host
compatibility. The 1.8 V levels will offer lower noise (EMI) and also a system power savings.
8.3.3.4 Serializer Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising
edge of the PCLK. If RFB is Low, input data is latched on the Falling edge of the PCLK. serializer and
deserializer maybe set differently. This feature may be controlled by the external pin or by register.
8.3.3.5 Optional Serial Bus Control
See Optional Serial Bus Control.
8.3.3.6 Optional BIST Mode
See Built-In Self Test (BIST).
8.3.4 Deserializer Functional Description
The deserializer converts a single input serial data stream to a wide parallel output bus, and also provides a
signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured via external pins and
strap pins or through the optional serial control bus. The deserializer features enhance signal quality on the link
by supporting: an equalizer input and also the FPD-Link II data coding that provides randomization, scrambling,
and DC balanacing of the data. The deserializer includes multiple features to reduce EMI associated with display
data transmission. This includes the randomization and scrambling of the data and also the output spread
spectrum clock generation (SSCG) support. The deserializer features power saving features with a power-down
mode, and optional LVCMOS (1.8 V) interface compatibility.
8.3.4.1 Signal Quality Enhancers
8.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
The deserializer can enable receiver input equalization of the serial stream to increase the eye opening to the
deserializer input.
NOTE
This function cannot be seen at the RxIN± input but can be observed at the serial test port
(CMLOUTP/N) enabled through the Serial Bus control registers. The equalization feature
may be controlled by the external pin or by register.
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Table 3. Receiver Equalization Configuration Table
INPUTS
(1)
EQ3
EQ2
L
L
EFFECT
EQ1
EQ0
L
L
H
L
H
H
≈3 dB
L
H
L
H
≈4.5 dB
L
H
H
H
≈6 dB
H
L
L
H
≈7.5 dB
H
L
H
H
≈9 dB
H
H
L
H
≈10.5 dB
H
H
H
H
≈12 dB
X
X
X
L
OFF (1)
≈1.5 dB
Default Setting is EQ = Off
8.3.4.2 EMI Reduction Features
8.3.4.2.1 Deserializer Output Slew (OS_PCLK/DATA)
The parallel bus outputs (RGB[7:0], VS, HS, DE and PCLK) of the deserializer feature a selectable output slew.
The DATA (RGB[7:0], VS, HS, DE) are controlled by strap pin or register bit OS_DATA. The PCLK is controlled
by strap pin or register bit OS_PCLK. When the OS_PCLK/DATA = HIGH, the maximum slew rate is selected.
When the OS_PCLK/DATA = LOW, the minimum slew rate is selected. Use the higher slew rate setting when
driving longer traces or a heavier capacitive load.
8.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) — Optional
The deserializer provides access to the center tap of the internal termination. A capacitor may be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1-µF capacitor may be connected to this pin to Ground.
8.3.4.2.3 Deserializer SSCG Generation — Optional
The deserializer provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both
clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4%
total) at up to 35kHz modulations nominally are available (see Table 4). This feature may be controlled by
external STRAP pins or by register.
Table 4. SSCG Configuration (LF_MODE = L) — Deserializer Output
SSC[3:0] INPUTS
LF_MODE = L (20 to 65 MHz)
28
RESULT
SSC3
SSC2
SSC1
SSC0
FDEV (%)
FMOD (kHz)
L
L
L
L
Off
Off
L
L
L
H
±0.5
L
L
H
L
±1.0
L
L
H
H
±1.5
L
H
L
L
±2.0
L
H
L
H
±0.5
L
H
H
L
±1.0
L
H
H
H
±1.5
H
L
L
L
±2.0
H
L
L
H
±0.5
H
L
H
L
±1.0
H
L
H
H
±1.5
H
H
L
L
±2.0
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PCLK/2168
PCLK/1300
PCLK/868
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Table 4. SSCG Configuration (LF_MODE = L) — Deserializer Output (continued)
SSC[3:0] INPUTS
LF_MODE = L (20 to 65 MHz)
RESULT
SSC3
SSC2
SSC1
SSC0
FDEV (%)
H
H
L
H
±0.5
H
H
H
L
±1.0
H
H
H
H
±1.5
FMOD (kHz)
PCLK/650
Table 5. SSCG Configuration (LF_MODE = H) — Deserializer Output
SSC[3:0] INPUTS
LH_MODE = H (5 to 20 MHz)
RESULT
SSC3
SSC2
SSC1
SSC0
FDEV (%)
FMOD (kHz)
L
L
L
L
L
L
L
Off
Off
H
±0.5
L
L
H
L
±1.0
L
L
H
H
±1.5
L
H
L
L
±2.0
L
H
L
H
±0.5
L
H
H
L
±1.0
L
H
H
H
±1.5
H
L
L
L
±2.0
H
L
L
H
±0.5
H
L
H
L
±1.0
H
L
H
H
±1.5
H
H
L
L
±2.0
H
H
L
H
±0.5
H
H
H
L
±1.0
H
H
H
H
±1.5
PCLK/620
PCLK/370
PCLK/258
PCLK/192
Frequency
fdev(max)
FPCLK+
FPCLK
FPCLK-
fdev(min)
Time
1/fmod
Figure 26. SSCG Waveform
8.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
The deserializer parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for target
(Display) compatibility. The 1.8-V levels will offer a lower noise (EMI) and also a system power-savings.
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8.3.4.3 Power-Saving Features
8.3.4.3.1 Deserializer Power-Down Feature (PDB)
The deserializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by
the system to save power, disabling the deserializer when the display is not needed. An auto detect mode is also
available. In this mode, the PDB pin is tied High and the deserializer will enter power down when the serial
stream stops. When the serial stream starts up again, the deserializer will lock to the input stream and assert the
LOCK pin and output valid data. In power-down mode, the Data and PCLK output states are determined by the
OSS_SEL status.
NOTE
In power down, the optional Serial Bus Control Registers are RESET.
8.3.4.3.2 Deserializer Stop Stream SLEEP Feature
The deserializer will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition
is detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer
will then lock to the incoming signal and recover the data.
NOTE
In STOP STREAM SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
8.3.4.4 Deserializer CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to
LOW (depending on the value of the OSS_SEL setting). After the DS90UR906Q-Q1 completes its lock sequence
to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the parallel bus and PCLK outputs. The PCLK output is held at its current state at the
change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the RGB/VS/HS/DE
outputs are based on the OSS_SEL setting (STRAP PIN configuration or register).
8.3.4.5 Deserializer Oscillator Output (Optional)
The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin or by register (see Table 7 and Table 8).
Table 6. OSS_SEL and PDB Configuration — Deserializer Outputs (1)
INPUTS
SERIAL
INPUT
(1)
30
OUTPUTS
PDB
OSS_SEL
PCLK
RGB/HS/VS/DE
LOCK
PASS
X
L
X
Z
Z
Z
Z
Static
H
L
L
L
L
L
Static
H
H
Z
Z*
L
L
Active
H
X
Active
Active
H
H
If pin is strapped HIGH, output will be pulled up
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Table 7. OSC (Oscillator) Mode — Deserializer Output (1)
INPUTS
(1)
OUTPUTS
EMBEDDED PCLK
PCLK
RGB/HS/VS/DE
LOCK
PASS
NOTE *
OSC
Output
L
L
L
Present
Toggling
Active
H
H
Absent and OSC_SEL ≠ 000
PDB
(DES)
RIN
(Diff.)
active serial stream
X
H
LOCK
Z
H
L
L
Z
RGB[7:0],
HS, VS, DE
L
L
L
PCLK*
(DES)
L
L
L
PASS
H
H
L
Z
L
Locking
OFF
Active
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
Z
Active
OFF
CONDITIONS: * RFB = L, and OSS_SEL = L
Figure 27. Deserializer Outputs With Output State Select Low (OSS_SEL = L)
PDB
(DES)
RIN
(Diff.)
LOCK
active serial stream
X
H
Z
L
H
L
Z
RGB[7:0],
HS, VS, DE
Z
Z
Z
PCLK*
(DES)
Z
Z
Z
PASS
H
Z
OFF
L
Locking
H
L
Active
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
Z
Active
OFF
CONDITIONS: * RFB = L, and OSS_SEL = H
Figure 28. Deserializer Outputs With Output State Select High (OSS_SEL = H)
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Table 8. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
PCLK OSCILLATOR OUTPUT
OSC_SEL2
OSC_SEL1
OSC_SEL0
L
L
L
Off – Feature Disabled – Default
L
L
H
50 MHz ±40%
L
H
L
25 MHz ±40%
L
H
H
16.7 MHz ±40%
H
L
L
12.5 MHz ±40%
H
L
H
10 MHz ±40%
H
H
L
8.3 MHz ±40%
H
H
H
6.3 MHz ±40%
PDB
(DES)
RIN
(Diff.)
LOCK
active serial stream
H
Z
RGB[7:0],
HS, VS, DE
L
PCLK*
(DES)
L
PASS
X
H
L
f
L
Z
L
L
f
L
H
H
L
Z
OFF
Locking
Z
L
Active
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
Active
OFF
CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000.
Figure 29. Deserializer Outputs with Output State High and PCLK Output Oscillator Option Enabled
8.3.4.6 Deserializer OP_LOW (Optional)
The OP_ LOW feature is used to hold the LVCMOS outputs (except the LOCK output) at a LOW state. The user
must toggle the OP_LOW Set / Reset register bit to release the outputs to the normal toggling state.
NOTE
The release of the outputs can only occur when LOCK is HIGH. When the OP_LOW
feature is enabled, anytime LOCK = LOW, the LVCMOS outputs will toggle to a LOW
state again. The OP_ LOW strap pin feature is assigned to output PASS pin 42.
Restrictions on other straps:
1. Other straps should not be used in order to keep RGB[7:0], HS, VS, DE, and PCLK at a true LOW state.
Other features should be selected through I2C.
2. OSS_SEL function is not available when O/P_LOW is tied H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in TRI-STATE before PDB toggles HIGH because the
OP_LOW strap value has not been recognized until the DS90UR906Q-Q1 powers up. Figure 30 shows the user
controlled release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 31
shows the user controlled release of OP_LOW and manual reset of OP_LOW set.
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NOTE
Manual reset of OP_LOW can only occur when LOCK is H.
PDB
2.0V
LOCK
OP_ LOW
SET
(Strap pin)
User
controlled
User
controlled
OP_ LOW
RELEASE/SET
(Register)
RGB[7:0],
HS, VS, DE
TRISTATE
ACTIVE
ACTIVE
PCLK
TRISTATE
ACTIVE
ACTIVE
Figure 30. OP_LOW Auto Set
PDB
2.0V
LOCK
OP_LOW
SET
(Strap pin)
User
controlled
User
controlled
OP_ LOW
RELEASE/SET
(Register)
RGB[7:0],
HS, VS, DE
TRISTATE
ACTIVE
PCLK
TRISTATE
ACTIVE
Figure 31. OP_LOW Manual Set/Reset
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8.3.4.7 Deserializer Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising
edge of the PCLK. If RFB is Low, data is strobed on the Falling edge of the PCLK. This allows for interoperability with downstream devices. The deserializer output does not need to use the same edge as the
serializer input. This feature may be controlled by the external pin or by register.
8.3.4.8 Deserializer Control Signal Filter (Optional)
The deserializer provides an optional Control Signal (VS, HS, DE) filter that monitors the three video control
signals and eliminates any pulses that are 1 or 2 PCLKs wide. Control signals must be 3 pixel clocks wide (in its
HIGH or LOW state, regardless of which state is active). This is set by the CONFIG[1:0] or by the Control
Register. This feature may be controlled by the external pin or by Register.
8.3.4.9 Deserializer Low Frequency Optimization (LF_Mode)
This feature may be controlled by the external pin or by Register.
8.3.4.10 Deserializer Map Select
This feature may be controlled by the external pin or by register.
Table 9. Map Select Configuration
INPUTS
Effect
MAPSEL1
MAPSEL0
L
L
Bit 4, Bit 5 on LSB
DEFAULT
L
H
LSB 0 or 1
H
H or L
LSB 0
8.3.4.11 Deserializer Strap Input Pins
Configuration of the device maybe done through configuration input pins and the STRAP input pins, or through
the Serial Control Bus. The STRAP input pins share select parallel bus output pins. They are used to load in
configuration values during the initial power-up sequence of the device. Only a pullup on the pin is required when
a HIGH is desired. By default the pad has an internal pulldown, and will bias Low by itself. The recommended
value of the pullup is 10 kΩ to VDDIO; open (NC) for Low, no pulldown is required (internal pulldown). If using the
Serial Control Bus, no pullups are required.
8.3.4.12 Optional Serial Bus Control
See Optional Serial Bus Control.
8.3.4.13 Optional BIST Mode
See Built-In Self Test (BIST).
8.3.5 Built-In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the serializer and deserializer BISTEN input pins. The
Ser outputs a test pattern (PRBS7) and drives the link at speed. The deserializer detects the PRBS7 pattern and
monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon
completion of the test, the result of the test is held on the PASS output until reset (new BIST test or power
down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors
were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin.
During the BIST duration the deserializer data outputs toggle with a checkerboard pattern.
Inter-operability is supported between this FPD-Link II device and all FPD-Link II generations (Gen 1, 2, 3). See
Sample BIST Sequence for entering BIST mode and control.
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8.3.5.1 Sample BIST Sequence
See Figure 32 for the BIST mode flow diagram.
Step 1: Place the DS90UR905Q-Q1 serializer in BIST Mode by setting serializer BISTEN = H. For the
DS90UR905Q-Q1 serializer or DS99R421 FPD-Link II serializer BIST Mode is enabled through the BISTEN pin.
For the DS90C241 serializer or DS90UR241 serializer, BIST mode is enetered by setting all the input data of the
device to LOW state. A PCLK is required for all the serializer options. When the deserializer detects the BIST
mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut off.
Step 2: Place the DS90UR906Q-Q1 deserializer in BIST mode by setting the BISTEN = H. The deserializer is
now in the BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is
detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can
be monitored and counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data and the final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If
there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new
BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set Low. The Link returns to normal
operation.
Figure 33 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: SER in Normal
Figure 32. BIST Mode Flow Diagram
8.3.5.2 BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
• Pixel Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the PCLK rate times the test duration. If we
assume a 65-MHz PCLK, a 10 minute (600 seconds) test, and a PASS, the BERT is ≤ 1.07 × 10E-12.
The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and
performance monitoring.
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SER
BISTEN
(SER)
DES Outputs
BISTEN
(DES)
Case 1 - Pass
PCLK
(RFB = L)
RGB[7:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
X
FAIL
Prior Result
Normal
Case 2 - Fail
X = bit error(s)
DATA
(internal)
PRBS
BIST
Result
Held
BIST Test
BIST Duration
Normal
Figure 33. BIST Waveforms
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8.3.6 Optional Serial Bus Control
The serializer and deserializer may also be configured by the use of a serial control bus that is I2C protocol
compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write
of 01'h to reg_0x00'h will enable or allow configuration by registers; this will override the control/strap pins.
Multiple devices may share the serial control bus since multiple addresses are supported (see Figure 34).
The serial bus is comprised of three pins. The SCL is a serial bus clock Input. The SDA is the serial bus data
input/output signal. Both SCL and SDA signals require an external pullup resistor to VDDIO. For most applications
a 4.7-k pullup resistor to VDDIO may be used. The resistor value may be adjusted for capacitive loading and data
rate requirements. The signals are either pulled High, or driven Low.
1.8V
10 k
VDDIO
ID[X]
4.7k
HOST
4.7k
RID
SCL
SCL
SDA
SDA
SER
or
DES
To other
Devices
Figure 34. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are
possible. The pin may be pulled to VDD (1.8V, NOT VDDIO) with a 10 kΩ resistor; or a 10-kΩ pullup resistor (to
VDD1.8V, NOT VDDIO) and a pulldown resistor of the recommended value to set other three possible addresses
may be used. See Table 10 for the serializer and Table 11 for the deserializer. Do not tie ID[x] directly to VSS.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH (see
Figure 35).
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 35. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 36 and a WRITE is shown in Figure 37.
NOTE
During initial power-up, a delay of 10 ms will be required before the I2C will respond.
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If the Serial Bus is not required, the three pins may be left open (NC).
Table 10. ID[x] Resistor Value – DS90UR905Q-Q1 Serializer
RESISTOR
RID (1) kΩ (5% TOL)
(1)
ADDRESS
7'b
ADDRESS
8'b
0 APPENDED
(WRITE)
0.47
7b' 110 1001 (h'69)
8b' 1101 0010 (h'D2)
2.7
7b' 110 1010 (h'6A)
8b' 1101 0100 (h'D4)
8.2
7b' 110 1011 (h'6B)
8b' 1101 0110 (h'D6)
Open
7b' 110 1110 (h'6E)
8b' 1101 1100 (h'DC)
RID ≠ 0 Ω, do not connect directly to VSS (GND), this is not a valid address.
Table 11. ID[x] Resistor Value – DS90UR906Q-Q1 Deserializer
(1)
RESISTOR
RID (1) kΩ (5% TOL)
ADDRESS
7'b
ADDRESS
8'b
0 APPENDED
(WRITE)
0.47
7b' 111 0001 (h'71)
8b' 1110 0010 (h'E2)
2.7
7b' 111 0010 (h'72)
8b' 1110 0100 (h'E4)
8.2
7b' 111 0011 (h'73)
8b' 1110 0110 (h'E6)
Open
7b' 111 0110 (h'76)
8b' 1110 1100 (h'EC)
RID ≠ 0 Ω, do not connect directly to VSS (GND), this is not a valid address.
Register Address
Slave Address
A
2
S
A
1
A
0
0
Slave Address
a
c
k
a
c
k
A
2
S
A
1
A
0
Data
1
a
c
k
a
c
k
P
Figure 36. Serial Control Bus — READ
Register Address
Slave Address
A
2
S
A
1
A
0
0
a
c
k
Data
a
c
k
a
c
k
P
Figure 37. Serial Control Bus — WRITE
8.4 Device Functional Modes
8.4.1 Serializer and Deserializer Operating Modes and Backward Compatibility (CONFIG[1:0])
The DS90UR90xQ-Q1 chipset is also backward-compatible with previous generations of FPD-Link II.
Configuration modes are provided for backwards compatibility with the DS90C241 / DS90C124 FPD-Link II
Generation 1, and also the DS90UR241 / DS90UR124 FPD-Link II Generation 2 chipset by setting the respective
mode with the CONFIG[1:0] pins on the serializer or deserializer as shown in Table 12 and Table 13. The
selection also determine whether the Video Control Signal filter feature is enabled or disabled in Normal mode.
This feature may be controlled by pin or by Register.
Table 12. DS90UR905Q-Q1 Serializer Modes
CONFIG1
38
CONFIG0
MODE
DESERIALIZER DEVICE
L
L
Normal Mode, Control Signal Filter disabled
DS90UR906Q-Q1
L
H
Normal Mode, Control Signal Filter enabled
DS90UR906Q-Q1
H
L
Backwards-Compatible GEN2
DS90UR124, DS99R124
H
H
Backwards-Compatible GEN1
DS90C124
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Table 13. DS90UR906Q Deserializer Modes
CONFIG1
CONFIG0
MODE
SERIALIZER DEVICE
L
L
Normal Mode, Control Signal Filter disabled
DS90UR905Q-Q1
L
H
Normal Mode, Control Signal Filter enabled
DS90UR905Q-Q1
H
L
Backwards-Compatible GEN2
DS90UR241
H
H
Backwards-Compatible GEN1
DS90C241
8.5 Register Maps
Table 14. SERIALIZER — Serial Bus Control Registers
ADD
(DEC)
0
1
ADD
(HEX)
0
1
REGISTER
NAME
Serializer
Config 1
BIT(S)
R/W
DEFAULT
(BIN)
7
R/W
6
R/W
5
4
2
DESCRIPTION
0
Reserved
Reserved
0
Reserved
Reserved
R/W
0
VODSEL
0: Low
1: High
R/W
0
RFB
0: Data latched on Falling edge of PCLK
1: Data latched on Rising edge of PCLK
3:2
R/W
00
CONFIG
00: Control Signal Filter Disabled
01: Control Signal Filter Enabled
10: DS90UR124, DS99R124 Mode
11: DS90C124 Mode
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
R/W
0
REG
0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
7
R/W
0
REG ID
0: Address from ID[x] Pin
1: Address from Register
ID[X]
Serial Bus Device ID, Four IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are Reserved.
De-E Setting
000: set by external Resistor
001: –1 dB
010: –2 dB
011: –3.3 dB
100: –5 dB
101: –6.7 dB
110: –9 dB
111: –12 dB
Device ID
6:0
2
FUNCTION
R/W
1101000
7:5
R/W
000
4
R/W
0
De-E EN
0: De-Emphasis Enabled
1: De-Emphasis Disabled
3:0
R/W
000
Reserved
Reserved
De-Emphasis
Control
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Table 15. DESERIALIZER — Serial Bus Control Registers
ADD
(DEC)
0
1
ADD REGISTER
(HEX) NAME
0
1
BIT(S)
R/W
DEFAULT
(BIN)
FUNCTION
DESCRIPTION
7
R/W
0
LFMODE
0: 20 to 65 MHz Operation
1: 5 to 20 MHz Operation
6
R/W
0
OS_PCLK
0: Normal PCLK Output Slew
1: Increased PCLK Slew
5
R/W
0
OS_DATA
0: Normal DATA OUTPUT Slew
1: Increased Data Slew
4
R/W
0
RFB
0: Data strobed on Falling edge of PCLK
1: Data strobed on Rising edge of PCLK
3:2
R/W
00
CONFIG
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: Backwards-Compatible (DS90UR241)
11: Backwards-Compatible (DS90C241)
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
R/W
0
REG Control
0: Configurations set from control pins / STRAP pins
1: Configurations set from registers (except I2C_ID)
7
R/W
0
Deserializer
Config 1
7
6
2
Deserializer
Features 1
R/W
R/W
R/W
1110000
OP_LOW
Release/Set
0: set outputs state LOW (except LOCK)
1: release output LOW state, outputs toggling
normally
Note: This register only works during LOCK = 1.
0
OSS_SEL
Output Sleep State Select
0: PCLK/RGB[7:0]/HS/VS/DE = L, LOCK = Normal,
PASS = H
1: PCLK/RGB[7:0]/HS/VS/DE = Tri-State, LOCK =
Normal, PASS = H
0
5:4
R/W
00
MAP_SEL
Special for Backwards-Compatible Mode
00: bit 4, 5 on LSB
01: LSB zero if all data is zero; one if any data is one
10: LSB zero
11: LSB zero
3
R/W
0
OP_LOW
strap bypass
0: strap will determine whether OP_LOW feature is
ON or OFF
1: Turns OFF OP_LOW feature
OSC_SEL
000:
001:
010:
011:
100:
101:
110:
111:
2:0
40
ID[X]
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
Slave ID
6:0
2
0: Address from ID[X] Pin
1: Address from Register
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R/W
00
OFF
50 MHz ±40%
25 MHz ±40%
16.7 MHz ±40%
12.5 MHz ±40%
10 MHz ±40%
8.3 MHz ±40%
6.3 MHz ±40%
Copyright © 2009–2019, Texas Instruments Incorporated
Product Folder Links: DS90UR905Q-Q1 DS90UR906Q-Q1
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SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
Table 15. DESERIALIZER — Serial Bus Control Registers (continued)
ADD
(DEC)
3
ADD REGISTER
(HEX) NAME
3
BIT(S)
4
DEFAULT
(BIN)
7:5
R/W
000
4
R/W
0
FUNCTION
DESCRIPTION
EQ Gain
000: ≈1.625 dB
001: ≈3.25 dB
010: ≈4.87 dB
011: ≈6.5 dB
100: ≈8.125 dB
101: ≈9.75 dB
110: ≈11.375 dB
111: ≈13 dB
EQ Enable
0: EQ = disabled
1: EQ = enabled
SSC
IF LF_MODE = 0, then:
000: SSCG OFF
0001: fdev = ±0.5%, fmod
0010: fdev = ±1.0%, fmod
0011: fdev = ±1.5%, fmod
0100: fdev = ±2.0%, fmod
0101: fdev = ±0.5%, fmod
0110: fdev = ±1.0%, fmod
0111: fdev = ±1.5%, fmod
1000: fdev = ±2.0%, fmod
1001: fdev = ±0.5%, fmod
1010: fdev = ±1.0%, fmod
1011: fdev = ±1.5%, fmod
1100: fdev = ±2.0%, fmod
1101: fdev = ±0.5%, fmod
1110: fdev = ±1.0%, fmod
1111: fdev = ±1.5%, fmod
IF LF_MODE = 1, then:
000: SSCG OFF
0001: fdev = ±0.5%, fmod
0010: fdev = ±1.0%, fmod
0011: fdev = ±1.5%, fmod
0100: fdev = ±2.0%, fmod
0101: fdev = ±0.5%, fmod
0110: fdev = ±1.0%, fmod
0111: fdev = ±1.5%, fmod
1000: fdev = ±2.0%, fmod
1001: fdev = ±0.5%, fmod
1010: fdev = ±1.0%, fmod
1011: fdev = ±1.5%, fmod
1100: fdev = ±2.0%, fmod
1101: fdev = ±0.5%, fmod
1110: fdev = ±1.0%, fmod
1111: fdev = ±1.5%, fmod
Deserializer
Features 2
3:0
4
R/W
CMLOUT Config
R/W
0000
= PCLK/2168
= PCLK/2168
= PCLK/2168
= PCLK/2168
= PCLK/1300
= PCLK/1300
= PCLK/1300
= PCLK/1300
= PCLK/868
= PCLK/868
= PCLK/868
= PCLK/868
= PCLK/650
= PCLK/650
= PCLK/650
= PCLK/620
= PCLK/620
= PCLK/620
= PCLK/620
= PCLK/370
= PCLK/370
= PCLK/370
= PCLK/370
= PCLK/258
= PCLK/258
= PCLK/258
= PCLK/258
= PCLK/192
= PCLK/192
= PCLK/192
7
R/W
0
Repeater
Enable
0: Output CMLOUTP/N = disabled
1: Output CMLOUTP/N = enabled
6:0
R/W
0000000
Reserved
Reserved
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Display Application
The DS90UR90xQ-Q1 chipset is intended for interface between a host (graphics processor) and a display. It
supports an 24-bit color depth (RGB888) and up to 1024 × 768 display formats. In a RGB888 application, 24
color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link with PCLK rates from 5 to 65 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general-purpose signals may also be sent from host to display.
The deserializer is expected to be located close to its target device. The interconnect between the deserializer
and the target device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is
expected to be in the 5 to 10 pF range. Care should be taken on the PCLK output trace as this signal is edge
sensitive and strobes the data. It is also assumed that the fanout of the deserializer is one. If additional loads
need to be driven, a logic buffer or mux device is recommended.
9.1.2 Live Link Insertion
The serializer and deserializer devices support live pluggable applications. The automatic receiver lock to
random data “plug & go” hot insertion capability allows the DS90UR906Q-Q1 to attain lock to the active data
stream during a live insertion event.
9.1.3 Alternate Color / Data Mapping
Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit Color Applications.
Seven [7] is assumed to be the MSB, and Zero [0] is assumed to be the LSB. While this is recommended it is not
required. When connecting to earlier generations of FPD-Link II serializer and deserializer devices, a color
mapping review is recommended to ensure the correct connectivity is obtained. Table 16 provides examples for
interfacing to 18-bit applications with or without the video control signals embedded. The DS90UR906Q-Q1
deserializer also provides additional flexibility with the MAP_SEL feature as well.
Table 16. Alternate Color / Data Mapping
42
18-BIT RGB
18-BIT RGB
24-BIT RGB
24-BIT RGB
18-BIT RGB
18-BIT RGB
LSB R0
GP0
RO
RO
R0
R0
GP0
LSB R0
R1
GP1
R1
R1
R1
R1
GP1
R1
R2
R0
R2
R2
R2
R2
R0
R2
R3
R1
R3
R3
R3
R3
R1
R3
R4
R2
R4
R4
R4
R4
R2
R4
MSB R5
R3
R5
R5
R5
R5
R3
MSB R5
LSB G0
R4
R6
R6
R6
R6
R4
LSB G0
G1
R5
R7
R7
R7
R7
R5
G1
G2
GP2
G0
G0
G0
G0
GP2
G2
G3
GP3
G1
G1
G1
G1
GP3
G3
G4
GO
G2
G2
G2
G2
G0
G4
MSB G5
G1
G3
G3
G3
G3
G1
MSB G5
LSB B0
G2
G4
G4
G4
G4
G2
LSB0
B1
G3
G5
G5
G5
G5
G3
B1
B2
G4
G6
G6
G6
G6
G4
B2
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905 PIN NAME 906 PIN NAME
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Product Folder Links: DS90UR905Q-Q1 DS90UR906Q-Q1
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SNLS313I – SEPTEMBER 2009 – REVISED OCTOBER 2019
Application Information (continued)
Table 16. Alternate Color / Data Mapping (continued)
18-BIT RGB
18-BIT RGB
24-BIT RGB
24-BIT RGB
18-BIT RGB
18-BIT RGB
B3
G5
G7
905 PIN NAME 906 PIN NAME
G7
G7
G7
G5
B3
B4
GP4
B0
B0
B0
B0
GP4
B4
MSB B5
GP5
B1
B1
B1
B1
GP5
MSB B5
HS
B0
B2
B2
B2
B2
B0
HS
VS
B1
B3
B3
B3
B3
B1
VS
DE
B2
B4
B4
B4
B4
B2
DE
GP0
B3
B5
B5
B5
B5
B3
GP0
GP1
B4
B6
B6
B6
B6
B4
GP1
GP2
B5
B7
B7
B7
B7
B5
GP2
GND
HS
HS
HS
HS
HS
HS
GND
GND
VS
VS
VS
VS
VS
VS
GND
GND
DE
DE
DE
DE
DE
DE
GND
Scenario 3 (1)
Scenario 2 (2)
Scenario 1 (3)
905 Pin Name
906 Pin Name
Scenario 1 (3)
Scenario 2 (2)
Scenario 3 (1)
(1)
(2)
(3)
Scenario 3 supports an 18-bit RGB color mapping, 3 un-embedded video control signals, and up to three general-purpose signals.
Scenario 2 supports an 18-bit RGB color mapping, 3 embedded video control signals, and up to six general-purpose signals.
Scenario 1 supports the 24-bit RGB color mapping, along with the 3 embedded video control signals. This is the native mode for the
chipset.
9.2 Typical Applications
9.2.1 DS90UR905Q-Q1 Typical Connection
Figure 38 shows a typical application of the DS90UR905Q-Q1 serializer in Pin control mode for a 65 MHz 24-bit
Color Display Application. The LVDS outputs require 100-nF AC-coupling capacitors to the line. The line driver
includes internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1
µF capacitors and a 4.7-µF capacitor should be used for local device bypassing. System GPO (General-Purpose
Output) signals control the PDB and BISTEN pins. In this application the RFB pin is tied Low to latch data on the
falling edge of the PCLK. The application assumes the companion deserializer (DS90UR906Q-Q1) therefore the
configuration pins are also both tied Low. In this example the cable is long, therefore the VODSEL pin is tied
High and a De-Emphasis value is selected by the resistor R1. The interface to the host is with 1.8-V LVCMOS
levels, thus the VDDIO pin is connected also to the 1.8-V rail. The Optional Serial Bus Control is not used in this
example, thus the SCL, SDA and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the
enabling of the device until power is stable.
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Typical Applications (continued)
DS90UR905Q (SER)
VDDIO
VDDIO
C9
C7
FB1
C3
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
LVCMOS
Parallel
Video
Interface
VDDTX
VDDHS
HS
VS
DE
LVCMOS
Control
Interface
BISTEN
PDB
C12
CONFIG1
CONFIG1
RFB
C4
FB2
C5
FB3
C6
FB4
C8
C10
VDDP
C11
VDDL
C1
Serial
FPD-Link II
Interface
DOUT+
DOUTC2
B7
B6
B5
B4
B3
B2
B1
B0
PCLK
1.8V
VDDIO
VODSEL
De-Emph
1.8V
R1
10k
ID[X]
SCL
SDA
RID
RES2
RES1
RES0
DAP (GND)
NOTE:
C1-C2 = 0.1 PF (50 WV)
C3-C8 = 0.1 PF
C9-11 = 4.7 PF
C12 = >10 PF
R1 (cable specific)
RID (see ID[x] Resistor Value Table 12)
FB1-FB4: Impedance = 1 k:,
low DC resistance (
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