Product
Folder
Order
Now
Technical
Documents
Support &
Community
Tools &
Software
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
MSP430F676x1 Polyphase Metering SoCs
1 Device Overview
1.1
Features
1
• Accuracy VeREF–
voltage input
(2)
1.4
AVCC
V
VeREF–
Negative external
reference voltage input
VeREF+ > VeREF–
(3)
0
1.2
V
(VeREF+ –
VeREF–)
Differential external
reference voltage input
VeREF+ > VeREF–
(4)
1.4
AVCC
V
±26
µA
±1
µA
IVeREF+,
IVeREF–
CVeREF+/(1)
(2)
(3)
(4)
(5)
56
Static input current
Capacitance at VeREF+
or VeREF- terminal
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
2.2 V, 3 V
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
2.2 V, 3 V
See
(5)
±8.5
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide.
Specifications
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
5.8.10 REF
Table 5-47 lists the characteristics of the REF.
Table 5-47. REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VREF+
AVCC(min)
IREF+
TEST CONDITIONS
Positive built-in reference
voltage
AVCC minimum voltage,
Positive built-in reference
active
Operating supply current
into AVCC terminal (1)
VCC
MIN
TYP
MAX
REFVSEL = {2} for 2.5 V, REFON = 1
3V
2.47
2.51
2.55
REFVSEL = {1} for 2.0 V, REFON = 1
3V
1.95
1.99
2.03
REFVSEL = {0} for 1.5 V, REFON = 1
2.2 V, 3 V
1.46
1.50
1.54
REFVSEL = {0} for 1.5 V
1.8
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
UNIT
V
V
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
3V
23
30
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2.0 V
3V
21
27
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V
3V
19
25
10
50
µA
TCREF+
Temperature coefficient of
built-in reference (2)
REFVSEL = {0, 1, 2}, REFON = 1
ISENSOR
Operating supply current
into AVCC terminal
REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C
2.2 V
145
220
3V
170
245
VSENSOR
See
REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C
2.2 V
780
3V
780
VMID
AVCC divider at channel 11
ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC
2.2 V
1.08
1.1
1.12
3V
1.48
1.5
1.52
tSENSOR(sample)
Sample time required if
channel 10 is selected (4)
REFON = 1, ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
tVMID(sample)
Sample time required if
channel 11 is selected (5)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
PSRR_DC
Power supply rejection ratio
(DC)
AVCC = AVCC (min) to AVCC(max),
TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1
120
PSRR_AC
Power supply rejection ratio
(AC)
AVCC = AVCC (min) to AVCC(max),
TA = 25°C,
f = 1 kHz, ΔVpp = 100 mV
REFVSEL = {0, 1, 2}, REFON = 1
1
mV/V
tSETTLE
Settling time of reference
voltage (6)
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0→1
75
µs
VSD24REF
SD24_B internal reference
voltage
SD24REFS = 1
3V
tON
SD24_B internal reference
turnon time (7)
SD24REFS = 0→1, CREF = 100 nF
3V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(3)
ppm/
°C
µA
mV
V
30
µs
1
µs
1.137
1.151
300
1.165
200
µV/V
V
µs
The internal reference current is supplied through the AVCC terminal. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
The condition is that the error in a conversion started after tREFON is ≤ 1 LSB.
The condition is that SD24_B conversion started after tON should guarantee specified SINAD values for the selected Gain, OSR and
fSD24.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Specifications
57
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
5.8.11 Flash Memory
Table 5-48 lists the characteristics of the flash memory.
Table 5-48. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
Program and erase supply voltage
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
6
11
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank erase
6
11
mA
Cumulative program time
(1)
16
104
Program and erase endurance
tRetention
Data retention duration
tWord
3.6
UNIT
DVCC(PGM/ERASE)
tCPT
1.8
MAX
ms
cycles
100
years
64
85
µs
0
Block program time for first byte or word (2)
49
65
µs
tBlock,
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word (2)
37
49
µs
tBlock,
N
Block program time for last byte or word (2)
55
73
µs
tErase
Erase time for segment erase, mass erase, and bank erase when
available (2)
23
32
ms
fMCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
0
1
MHz
tBlock,
(1)
(2)
Word or byte program time
25°C
(2)
105
V
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word- or byte-write and block-write modes.
These values are hardwired into the state machine of the flash controller.
5.8.12 Emulation and Debug
Table 5-49 lists the characteristics of the JTAG and Spy-Bi-Wire interface.
Table 5-49. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
1
µs
15
100
µs
2.2 V
0
5
3V
0
10
2.2 V, 3 V
45
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
tSBW,Rst
Spy-Bi-Wire return to normal operation time
TCK input frequency for 4-wire JTAG (2)
fTCK
Rinternal
(1)
(2)
58
Internal pulldown resistance on TEST
VCC
(1)
MIN
TYP
2.2 V, 3 V
60
80
MHz
kΩ
Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6 Detailed Description
6.1
Overview
The TI MSP430F676x1 polyphase metering SoCs are powerful highly integrated solutions for revenue
meters that offer accuracy and low system cost with few external components. The F676x1 uses the lowpower MSP430 CPU with a 32-bit multiplier to perform all energy calculations, metering applications such
as tariff rate management, and communications with AMR or AMI modules. The F676x1 features TI's 24bit sigma-delta converter technology, which provides better than 0.5% accuracy. Family members include
up to 128KB of flash and 8KB of RAM and an LCD controller with support for up to 320 segments.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
59
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.2
www.ti.com
Functional Block Diagrams
XIN
DVCC DVSS
XOUT
AVCC AVSS
AUX1 AUX2 AUX3
PA
P1.x P2.x
RST/NMI
PB
P3.x P4.x
PC
P5.x P6.x
P7.x
PD
P8.x
PE
P9.x
(32 kHz)
ACLK
Unified
Clock
System
SMCLK
SYS
128KB
64KB
8KB
4KB
Flash
RAM
Watchdog
MCLK
MPY32
CRC16
Port
Mapping
Controller
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
2×8 I/Os
I/O Ports
P9
1×4 I/O
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
PE
1×4 I/O
CPUXV2
and
Working
Registers
(25 MHz)
EEM
(S: 3+1)
PMM
Auxiliary
Supplies
JTAG,
SBW
Interface
LDO,
SVM, SVS,
BOR
Port PJ
LCD_C
ADC10_A
SD24_B
10 Bit
200 ksps
3 Channel
REF
8-Mux
Up to 320
Segments
RTC_C
Reference
1.5 V, 2.0 V,
2.5 V
Timer_A
2 CC
Registers
Timer_A
3 CC
Registers
PJ.x
eUSCI_A0
eUSCI_A1
eUSCI_A2
TA1
TA2
TA3
TA0
(UART,
IrDA, SPI)
eUSCI_B0
2
(SPI, I C)
DMA
3 Channel
Copyright © 2016, Texas Instruments Incorporated
Figure 6-1. Functional Block Diagram – PZ Package
XIN
XOUT
DVCC DVSS
AVCC AVSS
AUX1 AUX2 AUX3
PA
P1.x P2.x
RST/NMI
PB
P3.x P4.x
PC
P5.x P6.x
(32 kHz)
ACLK
Unified
Clock
System
SMCLK
128KB
64KB
8KB
4KB
Flash
RAM
SYS
DMA
Watchdog
3 Channel
Port
Mapping
Controller
MCLK
CRC16
MPY32
I/O Ports
P1, P2
2×8 I/Os
Interrupt,
Wakeup
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
TA0
TA1
TA2
TA3
eUSCI_A0
eUSCI_A1
eUSCI_A2
Timer_A
3 CC
Registers
Timer_A
2 CC
Registers
(UART,
IrDA, SPI)
CPUXV2
and
Working
Registers
(25 MHz)
EEM
(S: 3+1)
JTAG,
SBW
Interface
Port PJ
PMM
Auxiliary
Supplies
LDO,
SVM, SVS,
BOR
SD24_B
3 Channel
ADC10_A
10 Bit
200 ksps
LCD_C
8-Mux
Up to 320
Segments
REF
Reference
1.5 V, 2.0 V,
2.5 V
RTC_C
eUSCI_B0
(SPI, I2C)
PJ.x
Copyright © 2016, Texas Instruments Incorporated
Figure 6-2. Functional Block Diagram – PN Package
60
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
6.3
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are
dedicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see Figure 6-3).
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Figure 6-3. CPU Registers
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
61
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.4
www.ti.com
Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 lists examples of the three types of instruction formats. Table 6-2 lists the address
modes.
Table 6-1. Instruction Word Formats
INSTRUCTION WORD FORMAT
EXAMPLE
Dual operands, source and destination
ADD
R4,R5
Single operands, destination only
CALL
Relative jump, un/conditional
JNE
R8
OPERATION
R4 + R5 → R5
PC → (TOS), R8 → PC
Jump-on-equal bit = 0
Table 6-2. Address Mode Descriptions
S (1)
D (1)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
Absolute
✓
✓
MOV & MEM, & TCDAT
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
ADDRESS MODE
(1)
S = source, D = destination
62
Detailed Description
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
6.5
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Operating Modes
These microcontrollers have one active mode and seven software-selectable low-power modes of
operation. An interrupt event can wake up the device from any of the low-power modes, service the
request, and restore back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No RAM retention, Backup RAM retained
– I/O pad state retention
– RTC clocked by low-frequency oscillator
– Wake-up input from RST/NMI, RTC_C events, port P1, or port P2
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No RAM retention, backup RAM retained
– RTC is disabled
– I/O pad state retention
– Wake-up input from RST/NMI, port P1, or port P2
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
63
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.6
www.ti.com
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-Up
External Reset
Watchdog Time-out, Key Violation
Flash Memory Key Violation
WDTIFG, KEYV (SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1) (3)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
Supply Switch
NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
61
Watchdog Timer_A Interval Timer
Mode
WDTIFG
Maskable
0FFF8h
60
eUSCI_A0 Receive or Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (4)
Maskable
0FFF6h
59
eUSCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (4)
Maskable
0FFF4h
58
ADC10_A
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG
(ADC10IV) (1) (4)
Maskable
0FFF2h
57
SD24_B
SD24_B Interrupt Flags (SD24IV) (1) (4)
Maskable
0FFF0h
56
Timer TA0
TA0CCR0 CCIFG0 (4)
Maskable
0FFEEh
55
Timer TA0
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV) (1) (4)
Maskable
0FFECh
54
eUSCI_A1 Receive or Transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV)
(1) (4)
Maskable
0FFEAh
53
eUSCI_A2 Receive or Transmit
UCA2RXIFG, UCA2TXIFG (UCA2IV) (1) (4)
Maskable
0FFE8h
52
(1) (4)
Maskable
0FFE6h
51
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (4)
Maskable
0FFE4h
50
Timer TA1
TA1CCR0 CCIFG0 (4)
Maskable
0FFE2h
49
Timer TA1
TA1CCR1 CCIFG1,
TA1IFG (TA1IV) (1) (4)
Maskable
0FFE0h
48
Maskable
0FFDEh
47
Maskable
0FFDCh
46
Maskable
0FFDAh
45
Auxiliary Supplies
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV)
Timer TA2
TA2CCR0 CCIFG0 (4)
Timer TA2
TA2CCR1 CCIFG1,
TA2IFG (TA2IV) (1) (4)
I/O Port P2
(1)
(2)
(3)
(4)
64
Auxiliary Supplies Interrupt Flags (AUXIV)
P2IFG.0 to P2IFG.7 (P2IV)
(1) (4)
(1) (4)
Maskable
0FFD8h
44
Timer TA3
TA3CCR0 CCIFG0
(4)
Maskable
0FFD6h
43
Timer TA3
TA3CCR1 CCIFG1,
TA3IFG (TA3IV) (1) (4)
Maskable
0FFD4h
42
LCD_C
LCD_C Interrupt Flags (LCDCIV) (1) (4)
Maskable
0FFD2h
41
RTC_C
RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (4)
Maskable
0FFD0h
40
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-3. Interrupt Sources, Flags, and Vectors (continued)
(5)
INTERRUPT SOURCE
INTERRUPT FLAG
Reserved
Reserved (5)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
0FFCEh
39
⋮
⋮
0FF80h
0, lowest
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, TI recommends reserving these locations.
6.7
Memory Organization
Table 6-4 summarizes the memory map.
Table 6-4. Memory Organization
MSP430F67641
Main Memory (flash)
Total Size
128KB
64KB
00FFFFh to 00FF80h
00FFFFh to 00FF80h
Bank 3
32KB
023FFFh to 01C000h
not available
Bank 2
32KB
01BFFFh to 014000h
not available
Bank 1
32KB
013FFFh to 00C000h
32KB
013FFFh to 00C000h
Bank 0
32KB
00BFFFh to 004000h
32KB
00BFFFh to 004000h
8KB
4KB
Sector 3
2KB
003BFFh to 003400h
not available
Sector 2
2KB
0033FFh to 002C00h
not available
Sector 1
2KB
002BFFh to 002400h
2KB
002BFFh to 002400h
Sector 0
2KB
0023FFh to 001C00h
2KB
0023FFh to 001C00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
Main: Interrupt vector
Main: code memory
RAM
Information memory
(flash)
Bootloader (BSL)
memory (flash)
MSP430F67621
Total Size
Peripherals
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
65
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.8
www.ti.com
Bootloader (BSL)
The BSL lets users program the flash memory or RAM using various serial interfaces. Access to the
device memory by the BSL is protected by an user-defined password. BSL entry requires a specific entry
sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features
of the BSL and its implementation, see the MSP430™ Flash Device Bootloader (BSL) User's Guide.
Table 6-5 lists the BSL pin requirements.
Table 6-5. UART BSL Pin Requirements and Functions
6.9
6.9.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P3.0
Data transmit
P3.1
Data receive
DVCC
Power supply
DVSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide and MSP430 Programming With the JTAG Interface.
Table 6-6. JTAG Pin Requirements and Functions
66
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/ACLK/TCK
IN
JTAG clock input
PJ.2/ADC10CLK/TMS
IN
JTAG state control
PJ.1/MCLK/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/SMCLK/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
Detailed Description
DVCC
Power supply
DVSS
Ground supply
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
6.9.2
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The SpyBi-Wire interface pin requirements are shown in Table 6-7. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide and MSP430
Programming With the JTAG Interface.
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
DVCC
Power supply
DVSS
Ground supply
6.10 Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are
also called information memory.
• Segment A can be locked separately.
6.11 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage;
however, all data are lost. Features of the RAM include:
• RAM has n sectors of 2KB each.
• Each sector 0 to n can be complete disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low-power retention mode when possible.
6.12 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5. This
backup RAM is part of the Backup subsystem, which operates on dedicated power supply AUXVCC3.
8 bytes of backup RAM are available in this device. The backup RAM can be word-wise accessed through
the registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. The backup RAM registers cannot be
accessed by the CPU when the high-side SVS is disabled by software.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
67
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.13 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx
Family User's Guide.
6.13.1 Oscillator and System Clock
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an
internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator
(REFO), and an integrated internal digitally controlled oscillator (DCO). The UCS module is designed to
meet the requirements of both low system cost and low power consumption. The UCS module features
digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO
provides a fast turnon clock source and stabilizes in 3 µs (typical). The UCS module provides the following
clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator
(VLO), or the trimmed low-frequency oscillator (REFO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
6.13.2 Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and
contains programmable output levels to provide for power optimization. The PMM also includes supply
voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, and brownout protection. The
brownout circuit provides the proper internal reset signal to the device during power-on and power-off. The
SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both
supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is
not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
6.13.3 Auxiliary Supply System (AUX)
The AUX module can operate the device from auxiliary supplies when the primary supply fails. Two
auxiliary supplies are supported: AUXVCC1 and AUXVCC2. AUX supports automatic or manual switching
from primary supply to auxiliary supplies while maintaining full functionality. AUX allows threshold-based
monitoring of primary and auxiliary supplies. The device can be started from primary supply or AUXVCC1,
whichever is higher. AUX enables internal monitoring of voltage levels on primary and auxiliary supplies
using ADC10_A. This module implements a simple charger for backup supplies.
6.13.4 Backup Subsystem
The Backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes lowfrequency oscillator (XT1), RTC module, and Backup RAM. The functionality of the Backup subsystem is
retained during LPM3.5. The Backup subsystem module registers cannot be accessed by the CPU when
the high-side SVS is disabled by user. It is necessary to keep the high-side SVS enabled with
SVSHMD = 1 and SVSMHACE = 0 to turn off the low-frequency oscillator (XT1) in LPM4.
68
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.13.5 Digital I/O
Up to nine I/O ports are implemented. For 100-pin options, Ports P1 to P8 are complete, and P9 is
reduced to 4-bit I/O. For 80-pin options, Ports P1 to P6 are complete, and P7, P8, and P9 are completely
removed. Port PJ contains four individual I/O pins, common to all devices. All I/O bits are individually
programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Programmable drive strength on all ports.
• Edge-selectable interrupt and LPM3.5 or LPM4.5 wake-up input capability available for all bits of ports
P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PE).
6.13.6 Port Mapping Controller
The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, and
P3 (see Table 6-8). Table 6-9 lists the default settings for all pins that support port mapping.
Table 6-8. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
1
2
3
4
5
6
PM_UCA0RXD
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
PM_UCA0SOMI
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
PM_UCA0TXD
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
PM_UCA0SIMO
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
PM_UCA0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
PM_UCA0STE
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA1RXD
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
PM_UCA1SOMI
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
PM_UCA1TXD
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
PM_UCA1SIMO
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
7
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
8
PM_UCA1STE
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
9
10
PM_UCA2RXD
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
PM_UCA2SOMI
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
PM_UCA2TXD
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
PM_UCA2SIMO
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
11
PM_UCA2CLK
eUSCI_A2 clock input/output (direction controlled by eUSCI)
12
PM_UCA2STE
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
13
14
PM_UCB0SIMO
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
PM_UCB0SDA
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
PM_UCB0SOMI
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
PM_UCB0SCL
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
15
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
16
PM_UCB0STE
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
17
PM_TA0.0
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
18
PM_TA0.1
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
19
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
20
PM_TA1.0
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
21
PM_TA1.1
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
69
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-8. Port Mapping Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
22
PM_TA2.0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
23
PM_TA2.1
TA2 CCR1 capture input CCI1A
TA2 CCR1 compare output Out1
24
PM_TA3.0
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
25
PM_TA3.1
TA3 CCR1 capture input CCI1A
TA3 CCR1 compare output Out1
PM_TACLK
Timer_A clock input to
TA0, TA1, TA2, TA3
None
None
RTC_C clock output
26
PM_RTCCLK
(1)
27
PM_SDCLK
SD24_B bitstream clock input/output (direction controlled by SD24_B)
28
PM_SD0DIO
SD24_B converter 0 bitstream data input/output (direction controlled by SD24_B)
29
PM_SD1DIO
SD24_B converter 1 bitstream data input/output (direction controlled by SD24_B)
30
PM_SD2DIO
SD24_B converter 2 bitstream data input/output (direction controlled by SD24_B)
31 (0FFh) (1)
PM_ANALOG
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
when applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are
ignored, which results in a read value of 31.
Table 6-9. Default Mapping
PIN NAME
PZ
PN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
P1.0/PM_TA0.0/
VeREF-/A2
P1.0/PM_TA0.0/
VeREF-/A2
PM_TA0.0
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
P1.1/PM_TA0.1/
VeREF+/A1
P1.1/PM_TA0.1/
VeREF+/A1
PM_TA0.1
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
PM_UCA0RXD,
PM_UCA0SOMI
eUSCI_A0 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in
(direction controlled by eUSCI)
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
PM_UCA0TXD,
PM_UCA0SIMO
eUSCI_A0 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out
(direction controlled by eUSCI)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
PM_UCA1RXD,
PM_UCA1SOMI
eUSCI_A1 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in
(direction controlled by eUSCI)
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
PM_UCA1TXD,
PM_UCA1SIMO
eUSCI_A1 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out
(direction controlled by eUSCI)
P1.6/PM_UCA0CLK/
COM4
P1.6/PM_UCA0CLK/
COM4
PM_UCA0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
P1.7/PM_UCB0CLK/
COM5
P1.7/PM_UCB0CLK/
COM5
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39
PM_UCB0SOMI,
PM_UCB0SCL
eUSCI_B0 SPI slave out master in
(direction controlled by eUSCI),
eUSCI_B0 I2C clock
(open drain and direction controlled by eUSCI)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38
PM_UCB0SIMO,
PM_UCB0SDA
eUSCI_B0 SPI slave in master out
(direction controlled by eUSCI),
eUSCI_B0 I2C data
(open drain and direction controlled by eUSCI)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
PM_UCA2RXD,
PM_UCA2SOMI
eUSCI_A2 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in
(direction controlled by eUSCI)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
PM_UCA2TXD,
PM_UCA2SIMO
eUSCI_A2 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out
(direction controlled by eUSCI)
P2.4/PM_UCA1CLK
P2.4/PM_UCA1CLK/S35
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
70
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-9. Default Mapping (continued)
PIN NAME
PZ
PxMAPy MNEMONIC
PN
INPUT PIN FUNCTION
PM_UCA2CLK
OUTPUT PIN FUNCTION
P2.5/PM_UCA2CLK
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0
P2.6/PM_TA1.0/S33
PM_TA1.0
TA1 CCR0 capture input CCI0A
eUSCI_A2 clock input/output (direction controlled by eUSCI)
TA1 CCR0 compare output Out0
P2.7/PM_TA1.1
P2.7/PM_TA1.1/S32
PM_TA1.1
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
P3.0/PM_TA2.0
P3.0/PM_TA2.0/S31
PM_TA2.0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
P3.1/PM_TA2.1
P3.1/PM_TA2.1/S30
PM_TA2.1
TA2 CCR1 capture input CCI1A
TA2 CCR1 compare output Out1
P3.2/PM_TACLK/
PM_RTCCLK
P3.2/PM_TACLK/
PM_RTCCLK/S29
PM_TACLK,
PM_RTCCLK
Timer_A clock input to
TA0, TA1, TA2, TA3
RTC_C clock output
P3.3/PM_TA0.2
P3.3/PM_TA0.2/S28
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
P3.4/PM_SDCLK/S39
P3.4/PM_SDCLK/S27
PM_SDCLK
SD24_B bitstream clock input/output
(direction controlled by SD24_B)
P3.5/PM_SD0DIO/S38
P3.5/PM_SD0DIO/S26
PM_SD0DIO
SD24_B converter 0 bitstream data input/output
(direction controlled by SD24_B)
P3.6/PM_SD1DIO/S37
P3.6/PM_SD1DIO/S25
PM_SD1DIO
SD24_B converter 1 bitstream data input/output
(direction controlled by SD24_B)
P3.7/PM_SD2DIO/S36
P3.7/PM_SD2DIO/S24
PM_SD2DIO
SD24_B converter 2 bitstream data input/output
(direction controlled by SD24_B)
6.13.7 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power on reset
(POR) and power up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators (see Table 6-10), bootloader entry mechanisms, and configuration management (device
descriptors). It also includes a data exchange mechanism through JTAG called a JTAG mailbox that can
be used in the application.
Table 6-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
INTERRUPT EVENT
WORD
ADDRESS
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
DoBOR (BOR)
06h
Wake up from LPMx.5 (BOR)
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SYSRSTIV, System Reset
OFFSET
SVMH_OVP (POR)
019Eh
12h
14h
WDT time-out (PUC)
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h to 3Eh
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Highest
10h
DoPOR (POR)
Copyright © 2014–2018, Texas Instruments Incorporated
PRIORITY
Lowest
Detailed Description
71
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-10. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR REGISTER
INTERRUPT EVENT
WORD
ADDRESS
OFFSET
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
SYSSNIV, System NMI
Highest
08h
VMAIFG
019Ch
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIIFG
02h
OFIFG
SYSUNIV, User NMI
PRIORITY
019Ah
ACCVIFG
Lowest
Highest
04h
06h
AUXSWNMIFG
08h
Reserved
0Ah to 1Eh
Lowest
6.13.8 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the timer can be configured as an interval timer and can generate
interrupts at selected time intervals.
6.13.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral.
Table 6-11. DMA Trigger Assignments (1)
TRIGGER
(1)
72
Detailed Description
CHANNEL
0
1
0
DMAREQ
1
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
4
Reserved
5
TA2CCR0 CCIFG
6
Reserved
7
TA3CCR0 CCIFG
8
Reserved
9
Reserved
2
Reserved DMA triggers may be used by other devices in the family.
Reserved DMA triggers do not cause any DMA trigger event when
selected.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-11. DMA Trigger Assignments(1) (continued)
TRIGGER
CHANNEL
0
1
10
Reserved
11
Reserved
12
Reserved
13
SD24IFG
14
Reserved
15
Reserved
16
UCA0RXIFG
17
UCA0TXIFG
18
UCA1RXIFG
19
UCA1TXIFG
20
UCA2RXIFG
21
UCA2TXIFG
22
UCB0RXIFG0
23
UCB0TXIFG0
24
ADC10IFG0
25
Reserved
26
Reserved
27
Reserved
28
Reserved
29
MPY ready
30
DMA2IFG
31
DMA0IFG
2
DMA1IFG
Reserved
6.13.10 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.13.11 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.13.12 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module supports SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module supports SPI (3-pin or 4-pin) or I2C.
Three eUSCI_A and one eUSCI_B modules are implemented.
6.13.13 ADC10_A
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and a conversion results buffer. A window
comparator with a lower and upper limit allows CPU-independent result monitoring with three window
comparator interrupt flags.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
73
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.13.14 SD24_B
The SD24_B module integrates up to three independent 24-bit sigma-delta analog-to-digital converters.
Each converter is designed with a fully differential analog input pair and programmable gain amplifier input
stage. The converters are based on second-order over-sampling sigma-delta modulators and digital
decimation filters. The decimation filters are comb type filters with selectable oversampling ratios of up to
1024.
6.13.15 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 6-12). TA0 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 6-12. TA0 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
NA
NA
PM_TA0.0
CCR0
DVCC
VCC
PM_TA0.1
CCI1A
PM_TA0.1
ACLK (internal)
CCI1B
ADC10_A (internal)
ADC10SHSx = {1}
DVSS
GND
DVCC
VCC
PM_TA0.2
CCI2A
DVSS
CCI2B
DVSS
GND
DVCC
VCC
CCR1
74
TA0
Detailed Description
TA1
SD24_B (internal)
SD24SCSx = {1}
PM_TA0.2
CCR2
TA2
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.13.16 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-13). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-13. TA1 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
PM_TA1.1
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
DVCC
VCC
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
NA
NA
PM_TA1.0
CCR0
TA0
PM_TA1.1
CCR1
TA1
6.13.17 TA2
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-14). TA2 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-14. TA2 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
NA
NA
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA2.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
PM_TA2.1
CCI1A
PM_TA2.1
ACLK (internal)
CCI1B
SD24_B (internal)
SD24SCSx = {2}
DVSS
GND
DVCC
VCC
PM_TA2.0
CCR0
CCR1
TA0
TA1
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
75
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.13.18 TA3
TA3 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA3 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 6-15). TA3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-15. TA3 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
DEVICE OUTPUT
SIGNAL
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA3.0
CCI0A
PM_TA3.0
DVSS
CCI0B
TA0
ADC10_A (internal)
ADC10SHSx = {2}
DVSS
GND
TA1
CCR0
DVCC
VCC
PM_TA3.1
CCI1A
PM_TA3.1
ACLK (internal)
CCI1B
SD24_B (internal)
SD24SCSx = {3}
DVSS
GND
DVCC
VCC
CCR1
6.13.19 SD24_B Triggers
Table 6-16 lists the input trigger connections to SD24_B converters from Timer_A modules and output
trigger pulse connection from SD24_B to ADC10_A.
Table 6-16. SD24_B Input/Output Trigger Connections
DEVICE INPUT SIGNAL MODULE INPUT SIGNAL
TA0.1 (internal)
SD24_B
SD24SCSx = {1}
TA2.1 (internal)
SD24_B
SD24SCSx = {2}
TA3.1 (internal)
SD24_B
SD24SCSx = {3}
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Trigger Pulse
ADC10_A (internal)
ADC10SHSx = {3}
SD24_B
6.13.20 ADC10_A Triggers
Table 6-17 lists the input trigger connections to ADC10_A from Timer_A modules and SD24_B.
Table 6-17. ADC10_A Input Trigger Connections
76
DEVICE INPUT SIGNAL
MODULE INPUT SIGNAL
TA0.1 (internal)
ADC10_A
ADC10SHSx = {1}
TA3.0 (internal)
ADC10_A
ADC10SHSx = {2}
SD24_B
trigger pulse (internal)
ADC10_A
ADC10SHSx = {3}
Detailed Description
MODULE BLOCK
ADC10_A
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.13.21 Real-Time Clock (RTC_C)
The RTC_C module can be configured for real-time clock (RTC) mode or for calendar mode providing
seconds, hours, day of week, day of month, month, and year. The RTC_C control and configuration
registers are password protected to ensure clock integrity against runaway code. Calendar mode
integrates an internal calendar that compensates for months with less than 31 days and includes leap year
correction. The RTC_C also supports flexible alarm functions, offset calibration, and temperature
compensation. The RTC_C on this device operates on dedicated AUXVCC3 supply and supports
operation in LPM3.5.
6.13.22 Reference (REF) Module Voltage Reference
The REF module generates all critical reference voltages that can be used by the various analog
peripherals in the device. These include the ADC10_A, LCD_C, and SD24_B modules.
6.13.23 LCD_C
The LCD_C driver generates the segment and common signals required to drive a liquid crystal display
(LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common
and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to 8-mux
LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its
integrated charge pump. It is possible to control the level of the LCD voltage and thus contrast by
software. The module also provides an automatic blinking capability for individual segments in static,
2‑mux, 3-mux, and 4-mux modes.
6.13.24 Embedded Emulation Module (EEM) (S Version)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
77
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.13.25 Peripheral File Map
Table 6-18 lists the base address and offset address range for the registers of all supported peripherals.
Table 6-18. Peripherals
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 6-19)
0100h
000h to 01Fh
PMM (see Table 6-20)
0120h
000h to 01Fh
Flash Control (see Table 6-21)
0140h
000h to 00Fh
CRC16 (see Table 6-22)
0150h
000h to 007h
RAM Control (see Table 6-23)
0158h
000h to 001h
Watchdog (see Table 6-24)
015Ch
000h to 001h
UCS (see Table 6-25)
0160h
000h to 01Fh
SYS (see Table 6-26)
0180h
000h to 01Fh
Shared Reference (see Table 6-27)
01B0h
000h to 001h
Port Mapping Control (see Table 6-28)
01C0h
000h to 007h
Port Mapping Port P1 (see Table 6-29)
01C8h
000h to 007h
Port Mapping Port P2 (see Table 6-30)
01D0h
000h to 007h
Port Mapping Port P3 (see Table 6-31)
01D8h
000h to 007h
Port P1, P2 (see Table 6-32)
0200h
000h to 01Fh
Port P3, P4 (see Table 6-33)
0220h
000h to 00Bh
Port P5, P6 (see Table 6-34)
0240h
000h to 00Bh
Port P7, P8 (see Table 6-35)
(not available in PN package)
0260h
000h to 00Bh
Port P9 (see Table 6-36)
(not available in PN package)
0280h
000h to 00Bh
Port PJ (see Table 6-37)
0320h
000h to 01Fh
Timer TA0 (see Table 6-38)
0340h
000h to 03Fh
Timer TA1 (see Table 6-39)
0380h
000h to 03Fh
Timer TA2 (see Table 6-40)
0400h
000h to 03Fh
Timer TA3 (see Table 6-41)
0440h
000h to 03Fh
Backup Memory (see Table 6-42)
0480h
000h to 00Fh
RTC_C (see Table 6-43)
04A0h
000h to 01Fh
32-Bit Hardware Multiplier (see Table 6-44)
04C0h
000h to 02Fh
DMA General Control (see Table 6-45)
0500h
000h to 00Fh
DMA Channel 0 (see Table 6-46)
0500h
010h to 01Fh
DMA Channel 1 (see Table 6-47)
0500h
020h to 02Fh
DMA Channel 2 (see Table 6-48)
0500h
030h to 03Fh
eUSCI_A0 (see Table 6-49)
05C0h
000h to 01Fh
eUSCI_A1 (see Table 6-50)
05E0h
000h to 01Fh
eUSCI_A2 (see Table 6-51)
0600h
000h to 01Fh
eUSCI_B0 (see Table 6-52)
0640h
000h to 02Fh
ADC10_A (see Table 6-53)
0740h
000h to 01Fh
SD24_B(see Table 6-54)
0800h
000h to 06Fh
Auxiliary Supply (see Table 6-48)
09E0h
000h to 01Fh
LCD_C (see Table 6-56)
0A00h
000h to 05Fh
MODULE NAME
78
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-19. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 6-20. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high-side control
SVSMHCTL
04h
SVS low-side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM power mode 5 control register 0
PM5CTL0
10h
Table 6-21. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 6-22. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRC16DIRB
02h
CRC result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 6-23. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 6-24. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
OFFSET
00h
Detailed Description
79
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-25. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
Table 6-26. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 6-27. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 6-28. Port Mapping Controller (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping password
PMAPPWD
00h
Port mapping control
PMAPCTL
02h
Table 6-29. Port Mapping for Port P1 (Base Address: 01C8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1.0 mapping
P1MAP0
00h
Port P1.1 mapping
P1MAP1
01h
Port P1.2 mapping
P1MAP2
02h
Port P1.3 mapping
P1MAP3
03h
Port P1.4 mapping
P1MAP4
04h
Port P1.5 mapping
P1MAP5
05h
Port P1.6 mapping
P1MAP6
06h
Port P1.7 mapping
P1MAP7
07h
80
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-30. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P2.0 mapping
P2MAP0
00h
Port P2.1 mapping
P2MAP2
01h
Port P2.2 mapping
P2MAP2
02h
Port P2.3 mapping
P2MAP3
03h
Port P2.4 mapping
P2MAP4
04h
Port P2.5 mapping
P2MAP5
05h
Port P2.6 mapping
P2MAP6
06h
Port P2.7 mapping
P2MAP7
07h
Table 6-31. Port Mapping for Port P3 (Base Address: 01D8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3.0 mapping
P3MAP0
00h
Port P3.1 mapping
P3MAP3
01h
Port P3.2 mapping
P3MAP2
02h
Port P3.3 mapping
P3MAP3
03h
Port P3.4 mapping
P3MAP4
04h
Port P3.5 mapping
P3MAP5
05h
Port P3.6 mapping
P3MAP6
06h
Port P3.7 mapping
P3MAP7
07h
Table 6-32. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 resistor enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 resistor enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
81
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-33. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 resistor enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 resistor enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
Table 6-34. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 resistor enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 resistor enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
Table 6-35. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 resistor enable
P7REN
06h
Port P7 drive strength
P7DS
08h
Port P7 selection
P7SEL
0Ah
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 resistor enable
P8REN
07h
Port P8 drive strength
P8DS
09h
Port P8 selection
P8SEL
0Bh
82
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-36. Port P9 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 resistor enable
P9REN
06h
Port P9 drive strength
P9DS
08h
Port P9 selection
P9SEL
0Ah
Table 6-37. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ resistor enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Port PJ selection
PJSEL
0Ah
Table 6-38. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0 counter
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
TA0 expansion 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 6-39. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
TA1 counter
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
TA1 expansion 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
83
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-40. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
TA2 counter
TA2R
10h
Capture/compare 0
TA2CCR0
12h
Capture/compare 1
TA2CCR1
14h
TA2 expansion 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
Table 6-41. TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA3 control
TA3CTL
00h
Capture/compare control 0
TA3CCTL0
02h
Capture/compare control 1
TA3CCTL1
04h
TA3 counter
TA3R
10h
Capture/compare 0
TA3CCR0
12h
Capture/compare 1
TA3CCR1
14h
TA3 expansion 0
TA3EX0
20h
TA3 interrupt vector
TA3IV
2Eh
Table 6-42. Backup Memory Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Backup memory 0
BAKMEM0
00h
Backup memory 1
BAKMEM1
02h
Backup memory 2
BAKMEM2
04h
Backup memory 3
BAKMEM3
06h
84
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-43. RTC_C Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC password
RTCPWD
01h
RTC control 1
RTCCTL1
02h
RTC control 3
RTCCTL3
03h
RTC offset calibration
RTCOCAL
04h
RTC temperature compensation
RTCTCMP
06h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds
RTCSEC
10h
RTC minutes
RTCMIN
11h
RTC hours
RTCHOUR
12h
RTC day of week
RTCDOW
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year
RTCYEAR
16h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion
BIN2BCD
1Ch
BCD-to-binary conversion
BCD2BIN
1Eh
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
85
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-44. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control 0
MPY32CTL0
2Ch
Table 6-45. DMA General Control Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 6-46. DMA Channel 0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
10h
DMA channel 0 source address low
DMA0SAL
12h
DMA channel 0 source address high
DMA0SAH
14h
DMA channel 0 destination address low
DMA0DAL
16h
DMA channel 0 destination address high
DMA0DAH
18h
DMA channel 0 transfer size
DMA0SZ
1Ah
86
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-47. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 1 control
DMA1CTL
20h
DMA channel 1 source address low
DMA1SAL
22h
DMA channel 1 source address high
DMA1SAH
24h
DMA channel 1 destination address low
DMA1DAL
26h
DMA channel 1 destination address high
DMA1DAH
28h
DMA channel 1 transfer size
DMA1SZ
2Ah
Table 6-48. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 2 control
DMA2CTL
30h
DMA channel 2 source address low
DMA2SAL
32h
DMA channel 2 source address high
DMA2SAH
34h
DMA channel 2 destination address low
DMA2DAL
36h
DMA channel 2 destination address high
DMA2DAH
38h
DMA channel 2 transfer size
DMA2SZ
3Ah
Table 6-49. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI _A control word 1
UCA0CTLW1
02h
eUSCI_A baud rate 0
UCA0BR0
06h
eUSCI_A baud rate 1
UCA0BR1
07h
eUSCI_A modulation control
UCA0MCTLW
08h
eUSCI_A status
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
UCA0IRTCTL
12h
eUSCI_A IrDA receive control
UCA0IRRCTL
13h
eUSCI_A interrupt enable
UCA0IE
1Ah
eUSCI_A interrupt flags
UCA0IFG
1Ch
eUSCI_A interrupt vector word
UCA0IV
1Eh
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
87
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-50. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA1CTLW0
00h
eUSCI _A control word 1
UCA1CTLW1
02h
eUSCI_A baud rate 0
UCA1BR0
06h
eUSCI_A baud rate 1
UCA1BR1
07h
eUSCI_A modulation control
UCA1MCTLW
08h
eUSCI_A status
UCA1STAT
0Ah
eUSCI_A receive buffer
UCA1RXBUF
0Ch
eUSCI_A transmit buffer
UCA1TXBUF
0Eh
eUSCI_A LIN control
UCA1ABCTL
10h
eUSCI_A IrDA transmit control
UCA1IRTCTL
12h
eUSCI_A IrDA receive control
UCA1IRRCTL
13h
eUSCI_A interrupt enable
UCA1IE
1Ah
eUSCI_A interrupt flags
UCA1IFG
1Ch
eUSCI_A interrupt vector word
UCA1IV
1Eh
Table 6-51. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA2CTLW0
00h
eUSCI _A control word 1
UCA2CTLW1
02h
eUSCI_A baud rate 0
UCA2BR0
06h
eUSCI_A baud rate 1
UCA2BR1
07h
eUSCI_A modulation control
UCA2MCTLW
08h
eUSCI_A status
UCA2STAT
0Ah
eUSCI_A receive buffer
UCA2RXBUF
0Ch
eUSCI_A transmit buffer
UCA2TXBUF
0Eh
eUSCI_A LIN control
UCA2ABCTL
10h
eUSCI_A IrDA transmit control
UCA2IRTCTL
12h
eUSCI_A IrDA receive control
UCA2IRRCTL
13h
eUSCI_A interrupt enable
UCA2IE
1Ah
eUSCI_A interrupt flags
UCA2IFG
1Ch
eUSCI_A interrupt vector word
UCA2IV
1Eh
88
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-52. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
eUSCI_B received address
UCB0ADDRX
1Ch
eUSCI_B address mask
UCB0ADDMASK
1Eh
eUSCI I2C slave address
UCB0I2CSA
20h
eUSCI interrupt enable
UCB0IE
2Ah
eUSCI interrupt flags
UCB0IFG
2Ch
eUSCI interrupt vector word
UCB0IV
2Eh
2
Table 6-53. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_A control 0
ADC10CTL0
00h
ADC10_A control 1
ADC10CTL1
02h
ADC10_A control 2
ADC10CTL2
04h
ADC10_A window comparator low threshold
ADC10LO
06h
ADC10_A window comparator high threshold
ADC10HI
08h
ADC10_A memory control 0
ADC10MCTL0
0Ah
ADC10_A conversion memory
ADC10MCTL0
12h
ADC10_A interrupt enable
ADC10IE
1Ah
ADC10_A interrupt flags
ADC10IGH
1Ch
ADC10_A interrupt vector word
ADC10IV
1Eh
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
89
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-54. SD24_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SD24_B control 0
SD24BCTL0
00h
SD24_B control 1
SD24BCTL1
02h
SD24_B trigger control
SD24BTRGCTL
04h
SD24_B trigger OSR control
SD24BTRGOSR
06h
SD24_B trigger preload
SD24BTRGPRE
08h
SD24_B interrupt flag
SD24BIFG
0Ah
SD24_B interrupt enable
SD24BIE
0Ch
SD24_B interrupt vector
SD24BIV
0Eh
SD24_B converter 0 control
SD24BCCTL0
10h
SD24_B converter 0 input control
SD24BINCTL0
12h
SD24_B converter 0 OSR control
SD24BOSR0
14h
SD24_B converter 0 preload
SD24BPRE0
16h
SD24_B converter 1 control
SD24BCCTL1
18h
SD24_B converter 1 input control
SD24BINCTL1
1Ah
SD24_B converter 1 OSR control
SD24BOSR1
1Ch
SD24_B converter 1 preload
SD24BPRE1
1Eh
SD24_B converter 2 control
SD24BCCTL2
20h
SD24_B converter 2 input control
SD24BINCTL2
22h
SD24_B converter 2 OSR control
SD24BOSR2
24h
SD24_B converter 2 preload
SD24BPRE2
26h
SD24_B converter 0 conversion memory low word
SD24BMEML0
50h
SD24_B converter 0 conversion memory high word
SD24BMEMH0
52h
SD24_B converter 1 conversion memory low word
SD24BMEML1
54h
SD24_B converter 1 conversion memory high word
SD24BMEMH1
56h
SD24_B converter 2 conversion memory low word
SD24BMEML2
58h
SD24_B converter 2 conversion memory high word
SD24BMEMH2
5Ah
Table 6-55. Auxiliary Supplies Registers (Base Address: 09E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Auxiliary supply control 0
AUXCTL0
00h
Auxiliary supply control 1
AUXCTL1
02h
Auxiliary supply control 2
AUXCTL2
04h
AUX2 charger control
AUX2CHCTL
12h
AUX3 charger control
AUX3CHCTL
14h
AUX ADC control
AUXADCCTL
16h
AUX interrupt flag
AUXIFG
1Ah
AUX interrupt enable
AUXIE
1Ch
AUX interrupt vector word
AUXIV
1Eh
90
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-56. LCD_C Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_C control 0
LCDCCTL0
000h
LCD_C control 1
LCDCCTL1
002h
LCD_C blinking control
LCDCBLKCTL
004h
LCD_C memory control
LCDCMEMCTL
006h
LCD_C voltage control
LCDCVCTL
008h
LCD_C port control 0
LCDCPCTL0
00Ah
LCD_C port control 1
LCDCPCTL1
00Ch
LCD_C port control 2
LCDCPCTL2
00Eh
LCD_C charge pump control
LCDCCPCTL
012h
LCD_C interrupt vector
LCDCIV
01Eh
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
Static and 2 to 4 mux modes
⋮
⋮
⋮
LCD_C memory 20
LCDM20
033h
LCD_C blinking memory 1
LCDBM1
040h
LCD_C blinking memory 2
LCDBM2
041h
⋮
⋮
LCD_C blinking memory 20
⋮
LCDBM20
053h
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
5 to 8 mux modes
⋮
⋮
LCD_C memory 40
LCDM40
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
⋮
047h
Detailed Description
91
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14 Input/Output Diagrams
6.14.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
Figure 6-4 shows the port diagram. Table 6-57 summarizes the selection of the pin functions.
Pad Logic
To and from Reference
To ADC10_A
INCHx = y
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
From Port Mapping
1
P1OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1
P1IN.x
Bus
Keeper
EN
To Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Figure 6-4. Port P1 (P1.0 and P1.1) Diagram
92
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-57. Port P1 (P1.0 and P1.1) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
0
X
0
1
default
TA0.TA0
1
1
default
VeREF-/A2 (2)
X
1
= 31
I: 0; O: 1
0
X
TA0.CCI1A
0
1
default
TA0.TA1
1
1
default
VeREF+/A1 (2)
X
1
= 31
P1.0 (I/O)
P1.0/PM_TA0.0/
VeREF-/A2
0
TA0.CCI0A
P1.1 (I/O)
P1.1/PM_TA0.1/
VeREF+/A1
(1)
(2)
1
CONTROL BITS OR SIGNALS (1)
P1MAPx
X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
93
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.2 Port P1 (P1.2), Input/Output With Schmitt Trigger
Figure 6-5 shows the port diagram. Table 6-58 summarizes the selection of the pin functions.
Pad Logic
To ADC10_A
INCHx = y
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
From Port Mapping
1
P1OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
To Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
Set
P1SEL.x
Interrupt
Edge
Select
P1IES.x
Figure 6-5. Port P1 (P1.2) Diagram
Table 6-58. Port P1 (P1.2) Pin Functions
PIN NAME (P1.x)
x
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
2
FUNCTION
P1.2 (I/O)
(1)
(2)
94
CONTROL BITS OR SIGNALS (1)
P1DIR.x
P1SEL.x
P1MAPx
I: 0; O: 1
0
X
UCA0RXD/UCA0SOMI
X
1
default
A0 (2)
X
1
= 31
X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.14.3 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
Figure 6-6 shows the port diagram. Table 6-59 summarizes the selection of the pin functions.
To LCD_C
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
From Port Mapping
1
P1OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
To Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
Set
P1SEL.x
Interrupt
Edge
Select
P1IES.x
Figure 6-6. Port P1 (P1.3 to P1.5) Diagram
Table 6-59. Port P1 (P1.3 to P1.5) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.3 (I/O)
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
3
P1DIR.x
P1SEL.x
I: 0; O: 1
0
X
X
1
default
= 31
UCA0TXD/UCA0SIMO
R03 (2)
4
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
5
P1MAPx
X
1
I: 0; O: 1
0
X
UCA1RXD/UCA1SOMI
X
1
default
LCDREF/R13 (2)
X
1
= 31
P1.4 (I/O)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
P1.5 (I/O)
(1)
(2)
CONTROL BITS OR SIGNALS (1)
I: 0; O: 1
0
X
UCA1TXD/UCA1SIMO
X
1
default
R23 (2)
X
1
= 31
X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
95
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.4 Port P1 (P1.6 and P1.7), Port P2 (P2.0 and P2.1) (PZ Package Only) Input/Output
With Schmitt Trigger
Figure 6-7 shows the port diagram. Table 6-60 and Table 6-61 summarize the selection of the pin
functions.
COM4 to COM7
From LCD_C
Pad Logic
PyREN.x
PyMAP.x = PMAP_ANALOG
PyDIR.x
0
From Port Mapping
1
PyOUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
PyDS.x
0: Low drive
1: High drive
PySEL.x
PyIN.x
Bus
Keeper
EN
To Port Mapping
D
PyIE.x
EN
PyIRQ.x
Q
PyIFG.x
PySEL.x
PyIES.x
Set
Interrupt
Edge
Select
Figure 6-7. Port P1 (P1.6 and P1.7), Port P2 (P2.0 and P2.1) (PZ Package Only) Diagram
96
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-60. Port P1 (P1.6 and P1.7) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (P1.x)
x
P1.6/PM_UCA0CLK/COM4
6
FUNCTION
P1DIR.x
P1SEL.x
P1MAPx
COM4, COM5
Enable Signal
P1.6 (I/O)
I: 0; O: 1
0
X
0
UCA0CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM4
P1.7/PM_UCB0CLK/COM5
(1)
7
X
X
X
1
P1.7 (I/O)
I: 0; O: 1
0
X
0
UCB0CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM5
X
X
X
1
X = Don't care
Table 6-61. Port P2 (P2.0 and P2.1) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2MAPx
COM6, COM7
Enable Signal
I: 0; O: 1
0
X
0
UCB0SOMI/UCB0SCL
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.0 (I/O)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
0
COM6
X
X
X
1
I: 0; O: 1
0
X
0
UCB0SIMO/UCB0SDA
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM7
X
X
X
1
P2.1 (I/O)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
(1)
1
X = Don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
97
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.5 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-8 shows the port diagram. Table 6-62 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
From Port Mapping
1
P2OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
To Port Mapping
P2.2/PM_UCA2RXD/PM_UCA2SOMI
P2.3/PM_UCA2TXD/PM_UCA2SIMO
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
P2.6/PM_TA1.0
P2.7/PM_TA1.1
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-8. Port P2 (P2.2 to P2.7) Diagram (PZ Package Only)
98
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-62. Port P2 (P2.2 to P2.7) Pin Functions (PZ Package Only)
PIN NAME (P2.x)
x
FUNCTION
P2.2 (I/O)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
2
CONTROL BITS OR SIGNALS (1)
P2DIR.x
P2SEL.x
I: 0; O: 1
0
X
X
1
default
= 31
UCA2RXD/UCA2SOMI
Output driver and input Schmitt trigger disabled
P2.3 (I/O)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
3
X
1
I: 0; O: 1
0
X
X
1
default
= 31
UCA2TXD/UCA2SIMO
Output driver and input Schmitt trigger disabled
P2.4/PM_UCA1CLK
4
X
1
P2.4 (I/O)
I: 0; O: 1
0
X
UCA1CLK
X
1
default
= 31
Output driver and input Schmitt trigger disabled
P2.5/PM_UCA2CLK
5
X
1
P2.5 (I/O)
I: 0; O: 1
0
X
UCA2CLK
X
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
P2.6 (I/O)
P2.6/PM_TA1.0
6
I: 0; O: 1
0
X
TA1.CC10A
0
1
default
TA1.TA0
1
1
default
= 31
Output driver and input Schmitt trigger disabled
X
1
I: 0; O: 1
0
X
0
1
default
TA1.TA1
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
P2.7 (I/O)
P2.7/PM_TA1.1
(1)
7
P2MAPx
TA1.CCI1A
X = Don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
99
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.6 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-9 shows the port diagram. Table 6-63 summarizes the selection of the pin functions.
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.0/PM_TA2.0
P3.1/PM_TA2.1
P3.2/PM_TACLK/PM_RTCCLK
P3.3/PM_TA0.2
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
To Port Mapping
D
Figure 6-9. Port P3 (P3.0 to P3.3) Diagram (PZ Package Only)
Table 6-63. Port P3 (P3.0 to P3.3) Pin Functions (PZ Package Only)
PIN NAME (P3.x)
x
FUNCTION
P3.0 (I/O)
P3.0/PM_TA2.0
0
CONTROL BITS OR SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
TA2.CC10A
0
1
default
TA2.TA0
1
1
default
= 31
Output driver and input Schmitt trigger disabled
X
1
I: 0; O: 1
0
X
0
1
default
TA2.TA1
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
I: 0; O: 1
0
X
0
1
default
RTCCLK
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
I: 0; O: 1
0
X
TA0.CCI2A
0
1
default
TA0.TA2
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
P3.1 (I/O)
P3.1/PM_TA2.1
1
TA2.CCI1A
P3.2 (I/O)
P3.2/PM_TACLK/
PM_RTCCLK
2
TACLK
P3.3 (I/O)
P3.3/PM_TA0.2
(1)
100
3
P3MAPx
X = Don't care
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.14.7 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-10 shows the port diagram. Table 6-64 summarizes the selection of the pin functions.
S39 to S37
LCDS39 to LCDS37
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3.4/PM_SDCLK/S39
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
P3.7/PM_SD2DIO/S36
P3IN.x
EN
To Port Mapping
Bus
Keeper
D
Figure 6-10. Port P3 (P3.4 to P3.7) Diagram (PZ Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
101
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-64. Port P3 (P3.4 to P3.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL.x
P3MAPx
LCDS39 to
LCDS36
I: 0; O: 1
0
X
0
SDCLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.4 (I/O)
P3.4/PM_SDCLK/S39
4
S39
X
X
X
1
I: 0; O: 1
0
X
0
SD0DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.5 (I/O)
P3.5/PM_SD0DIO/S38
5
S38
X
X
X
1
I: 0; O: 1
0
X
0
SD1DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S37
X
X
X
1
P3.6 (I/O)
P3.6/PM_SD1DIO/S37
6
P3.7 (I/O)
P3.7/PM_SD2DIO/S36
(1)
102
7
I: 0; O: 1
0
X
0
SD2DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S36
X
X
X
1
X = Don't care
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.14.8 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to
P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-11 shows the port diagram. Table 6-65 through Table 6-69 summarize the selection of the pin
functions.
Sz
LCDSz
Pad Logic
PyREN.x
PyDIR.x
0
0
DVSS
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
PyOUT.x
DVSS
PyDS.x
0: Low drive
1: High drive
PySEL.x
Py.x/Sz
PyIN.x
Bus
Keeper
EN
Not Used
D
Figure 6-11. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7),
Port P8 (P8.0 to P8.3) Diagram (PZ Package Only)
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
103
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-65. Port P4 (P4.0 to P4.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
LCDS35 to
LCDS28
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S35
X
X
1
P4.0 (I/O)
P4.0/S35
0
P4.1 (I/O)
P4.1/S34
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S34
X
X
1
P4.2 (I/O)
P4.2/S33
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S33
P4.3 (I/O)
P4.3/S32
3
4
5
6
(1)
104
7
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S31
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S30
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S29
X
X
1
P4.7 (I/O)
P4.7/S28
0
0
S32
P4.6 (I/O)
P4.6/S29
1
0
DVSS
P4.5 (I/O)
P4.5/S30
X
N/A
P4.4 (I/O)
P4.4/S31
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S28
X
X
1
X = Don't care
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-66. Port P5 (P5.0 to P5.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
LCDS27 to
LCDS20
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S27
X
X
1
P5.0 (I/O)
P5.0/S27
0
P5.1 (I/O)
P5.1/S26
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S26
X
X
1
P5.2 (I/O)
P5.2/S25
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S25
P5.3 (I/O)
P5.3/S24
3
4
5
6
(1)
7
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S23
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S22
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S21
X
X
1
P5.7 (I/O)
P5.7/S20
0
0
S24
P5.6 (I/O)
P5.6/S21
1
0
DVSS
P5.5 (I/O)
P5.5/S22
X
N/A
P5.4 (I/O)
P5.4/S23
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S20
X
X
1
X = Don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
105
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-67. Port P6 (P6.0 to P6.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
LCDS19 to
LCDS12
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S19
X
X
1
P6.0 (I/O)
P6.0/S19
0
P6.1 (I/O)
P6.1/S18
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S18
X
X
1
P6.2 (I/O)
P6.2/S17
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S17
P6.3 (I/O)
P6.3/S16
3
4
5
6
(1)
106
7
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S15
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S14
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S13
X
X
1
P6.7 (I/O)
P6.7/S12
0
0
S16
P6.6 (I/O)
P6.6/S13
1
0
DVSS
P6.5 (I/O)
P6.5/S14
X
N/A
P6.4 (I/O)
P6.4/S15
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S12
X
X
1
X = Don't care
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-68. Port P7 (P7.0 to P7.7) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.x
LCDS11 to
LCDS4
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S11
X
X
1
P7.0 (I/O)
P7.0/S11
0
P7.1 (I/O)
P7.1/S10
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S10
X
X
1
P7.2 (I/O)
P7.2/S9
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S9
P7.3 (I/O)
P7.3/S8
3
4
5
6
(1)
7
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S7
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S6
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S5
X
X
1
P7.7 (I/O)
P7.7/S4
0
0
S8
P7.6 (I/O)
P7.6/S5
1
0
DVSS
P7.5 (I/O)
P7.5/S6
X
N/A
P7.4 (I/O)
P7.4/S7
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S4
X
X
1
X = Don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
107
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-69. Port P8 (P8.0 to P8.3) Pin Functions (PZ Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL.x
LCDS3 to
LCDS0
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S3
X
X
1
P8.0 (I/O)
P8.0/S3
0
P8.1 (I/O)
P8.1/S2
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S2
X
X
1
P8.2 (I/O)
P8.2/S1
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S1
P8.3 (I/O)
P8.3/S0
(1)
108
3
X
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S0
X
X
1
X = Don't care
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.14.9 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-12 shows the port diagram. Table 6-70 summarizes the selection of the pin functions.
Pad Logic
P8REN.x
P8DIR.x
0
Module X OUT
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.x
DVSS
0
1
P8.4/TA1.0
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
Module X IN
D
Figure 6-12. Port P8 (P8.4 to P8.7) Diagram (PZ Package Only)
Table 6-70. Port P8 (P8.4 to P8.7) Pin Functions (PZ Package Only)
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL.x
I: 0; O: 1
0
TA1.CCI0A
0
1
TA1.TA0
1
1
P8.5 (I/O)
P8.4 (I/O)
P8.4/TA1.0
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1
4
5
6
7
CONTROL BITS OR SIGNALS
I: 0; O: 1
0
TA1.CCI1A
0
1
TA1.TA1
1
1
P8.6 (I/O)
I: 0; O: 1
0
TA2.CCI0A
0
1
TA2.TA0
1
1
P8.7 (I/O)
I: 0; O: 1
0
TA2.CCI1A
0
1
TA2.TA1
1
1
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
109
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-13 shows the port diagram. Table 6-71 summarizes the selection of the pin functions.
Pad Logic
P9REN.x
P9DIR.x
0
Module X OUT
0
DVCC
1
1
Direction
0: Input
1: Output
1
P9OUT.x
DVSS
0
1
P9.0/TACLK/RTCCLK
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
EN
Module X IN
D
Figure 6-13. Port P9 (P9.0) Diagram (PZ Package Only)
Table 6-71. Port P9 (P9.0) Pin Functions (PZ Package Only)
PIN NAME (P9.x)
x
CONTROL BITS OR SIGNALS
FUNCTION
P9.0 (I/O)
P9.0/TACLK/RTCCLK
110
Detailed Description
0
P9DIR.x
P9SEL.x
I: 0; O: 1
0
TACLK
0
1
RTCCLK
1
1
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.14.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (PZ Package Only)
Figure 6-14 shows the port diagram. Table 6-72 summarizes the selection of the pin functions.
Pad Logic
To ADC10
INCHx = y
P9REN.x
DVSS
0
DVCC
1
1
P9DIR.x
P9OUT.x
P9.1/A5
P9.2/A4
P9.3/A3
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
Bus
Keeper
Figure 6-14. Port P9 (P9.1 to P9.3) Diagram (PZ Package Only)
Table 6-72. Port P9 (P9.1 to P9.3) Pin Functions (PZ Package Only)
PIN NAME (P9.x)
P9.1/A5
x
1
P9.2/A4
2
P9.3/A3
3
(1)
(2)
FUNCTION
P9.1 (I/O)
A5 (2)
P9.2 (I/O)
A4 (2)
P9.3 (I/O)
A3 (2)
CONTROL BITS OR SIGNALS (1)
P9DIR.x
P9SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
Setting P9SEL.x bit disables the output driver and the input Schmitt trigger.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
111
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (PN Package Only)
Figure 6-15 shows the port diagram. Table 6-73 summarizes the selection of the pin functions.
S39, S38
LCDS39, LCDS38
COM6, COM7
From LCD_C
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
From Port Mapping
1
P2OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
To Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-15. Port P2 (P2.0 and P2.1) Diagram (PN Package Only)
112
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-73. Port P2 (P2.0 and P2.1) Pin Functions (PN Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/
S39
0
(1)
1
P2SEL.x
P2MAPx
LCDS39,
LCDS38
COM6,
COM7
Enable
Signal
I: 0; O: 1
0
X
0
0
UCB0SOMI/UCB0SCL
X
1
default
0
0
Output driver and input
Schmitt trigger disabled
X
1
= 31
0
0
COM6
X
X
X
X
1
S39
X
X
X
1
0
P2.1 (I/O)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/
S38
P2DIR.x
I: 0; O: 1
0
X
0
0
UCB0SIMO/UCB0SDA
X
1
default
0
0
Output driver and input
Schmitt trigger disabled
X
1
= 31
0
0
COM7
X
X
X
X
1
S38
X
X
X
1
0
X = Don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
113
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PN Package Only)
Figure 6-16 shows the port diagram. Table 6-74 summarizes the selection of the pin functions.
S37...S32
LCDS37...LCDS32
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
From Port Mapping
1
P2OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0/S33
P2.7/PM_TA1.1/S32
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
Bus
Keeper
EN
To Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 6-16. Port P2 (P2.2 to P2.7) Diagram (PN Package Only)
114
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-74. Port P2 (P2.2 to P2.7) Pin Functions (PN Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2MAPx
LCDS37 to
LCDS32
I: 0; O: 1
0
X
0
UCA2RXD/UCA2SOMI
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.2 (I/O)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
2
S37
X
X
X
1
I: 0; O: 1
0
X
0
UCA2TXD/UCA2SIMO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.3 (I/O)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
3
S36
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
4
5
X
X
X
1
P2.4 (I/O)
I: 0; O: 1
0
X
0
UCA1CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S35
X
X
X
1
P2.5 (I/O)
I: 0; O: 1
0
X
0
UCA2CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S34
X
X
X
1
I: 0; O: 1
0
X
0
TA1.CCI0A
0
1
default
0
TA1.TA0
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.6 (I/O)
P2.6/PM_TA1.0/S33
6
S33
X
X
X
1
I: 0; O: 1
0
X
0
TA1.CCI1A
0
1
default
0
TA1.TA1
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S32
X
X
X
1
P2.7 (I/O)
P2.7/PM_TA1.1/S32
(1)
7
X = Don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
115
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (PN Package Only)
Figure 6-17 shows the port diagram. Table 6-75 summarizes the selection of the pin functions.
S31 to S24
LCDS31 to LCDS24
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
From Port Mapping
1
P3OUT.x
0
From Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
To Port Mapping
Bus
Keeper
P3.0/PM_TA2.0/S31
P3.1/PM_TA2.1/S30
P3.2/PM_TACLK/PM_RTCCLK/S29
P3.3/PM_TA0.2/S28
P3.4/PM_SDCLK/S27
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
P3.7/PM_SD2DIO/S24
D
Figure 6-17. Port P3 (P3.0 to P3.7) Diagram (PN Package Only)
116
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-75. Port P3 (P3.0 to P3.7) Pin Functions (PN Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x
P3SEL.x
P3MAPx
LCDS31 to
LCDS24
I: 0; O: 1
0
X
0
TA2.CCI0A
0
1
default
0
TA2.TA0
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.0 (I/O)
P3.0/PM_TA2.0/S31
0
S31
X
X
X
1
I: 0; O: 1
0
X
0
TA2.CCI1A
0
1
default
0
TA2.TA1
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.1 (I/O)
P3.1/PM_TA2.1/S30
1
S30
X
X
X
1
I: 0; O: 1
0
X
0
TACLK
0
1
default
0
RTCCLK
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S29
X
X
X
1
P3.2 (I/O)
P3.2/PM_TACLK/
PM_RTCCLK/S29
2
P3.3 (I/O)
P3.3/PM_TA0.2/S28
3
I: 0; O: 1
0
X
0
TA0.CCI2A
0
1
default
0
TA0.TA2
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S28
X
X
X
1
I: 0; O: 1
0
X
0
SDCLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.4 (I/O)
P3.4/PM_SDCLK/S27
4
S27
X
X
X
1
I: 0; O: 1
0
X
0
SD0DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.5 (I/O)
P3.5/PM_SD0DIO/S26
5
S26
X
X
X
1
I: 0; O: 1
0
X
0
SD1DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S25
X
X
X
1
P3.6 (I/O)
P3.6/PM_SD1DIO/S25
6
P3.7 (I/O)
P3.7/PM_SD2DIO/S24
(1)
7
I: 0; O: 1
0
X
0
SD2DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S24
X
X
X
1
X = Don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
117
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output
With Schmitt Trigger (PN Package Only)
Figure 6-18 shows the port diagram. Table 6-76 through Table 6-78 summarize the selection of the pin
functions.
Sz
LCDSz
Pad Logic
PyREN.x
PyDIR.x
0
0
DVSS
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
PyOUT.x
DVSS
PyDS.x
0: Low drive
1: High drive
PySEL.x
Py.x/Sz
PyIN.x
EN
Not Used
Bus
Keeper
D
Figure 6-18. Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Diagram (PN Package
Only)
118
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-76. Port P4 (P4.0 to P4.7) Pin Functions (PN Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL.x
LCDS23 to
LCDS16
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S23
X
X
1
P4.0 (I/O)
P4.0/S23
0
P4.1 (I/O)
P4.1/S22
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S22
X
X
1
P4.2 (I/O)
P4.2/S21
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S21
P4.3 (I/O)
P4.3/S20
3
4
5
6
(1)
7
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S19
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S18
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S17
X
X
1
P4.7 (I/O)
P4.7/S16
0
0
S20
P4.6 (I/O)
P4.6/S17
1
0
DVSS
P4.5 (I/O)
P4.5/S18
X
N/A
P4.4 (I/O)
P4.4/S19
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S16
X
X
1
X = Don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
119
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
Table 6-77. Port P5 (P5.0 to P5.7) Pin Functions (PN Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
LCDS15 to
LCDS8
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S15
X
X
1
P5.0 (I/O)
P5.0/S15
0
P5.1 (I/O)
P5.1/S14
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S14
X
X
1
P5.2 (I/O)
P5.2/S13
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S13
P5.3 (I/O)
P5.3/S12
3
4
5
6
(1)
120
7
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S11
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S10
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S9
X
X
1
P5.7 (I/O)
P5.7/S8
0
0
S12
P5.6 (I/O)
P5.6/S9
1
0
DVSS
P5.5 (I/O)
P5.5/S10
X
N/A
P5.4 (I/O)
P5.4/S11
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S8
X
X
1
X = Don't care
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Table 6-78. Port P6 (P6.0 to P6.7) Pin Functions (PN Package Only)
CONTROL BITS OR SIGNALS (1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
LCDS7 to
LCDS0
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S7
X
X
1
P6.0 (I/O)
P6.0/S7
0
P6.1 (I/O)
P6.1/S6
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S6
X
X
1
P6.2 (I/O)
P6.2/S5
2
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S5
P6.3 (I/O)
P6.3/S4
3
4
5
6
(1)
7
1
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
N/A
DVSS
1
1
0
S3
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S2
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S1
X
X
1
P6.7 (I/O)
P6.7/S0
0
0
S4
P6.6 (I/O)
P6.6/S1
1
0
DVSS
P6.5 (I/O)
P6.5/S2
X
N/A
P6.4 (I/O)
P6.4/S3
X
I: 0; O: 1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S0
X
X
1
X = Don't care
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
121
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.14.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 6-19 shows the port diagram. Table 6-79 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
PJDIR.x
0
DVCC
1
PJOUT.x
00
From JTAG
01
SMCLK
10
DVSS
0
DVCC
1
PJDS.0
0: Low drive
1: High drive
11
1
PJ.0/SMCLK/TDO
PJSEL.x
From JTAG
PJIN.x
EN
Bus
Holder
D
Figure 6-19. Port PJ (PJ.0) Diagram
122
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.14.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
Figure 6-20 shows the port diagram. Table 6-79 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
PJDIR.x
DVSS
DVSS
0
DVCC
1
1
0
1
PJOUT.x
00
From JTAG
01
MCLK/ADC10CLK/ACLK
10
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
PJDS.x
0: Low drive
1: High drive
11
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
To JTAG
Figure 6-20. Port PJ (PJ.1 to PJ.3) Diagram
Table 6-79. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME (PJ.x)
x
FUNCTION
PJ.0 (I/O) (2)
PJ.0/SMCLK/TDO
0
1
0
0
1
1
0
TDO (3)
X
X
1
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
1
1
0
X
X
1
(2)
MCLK
PJ.2 (I/O)
2
(2)
ACLK
TCK
(1)
(2)
(3)
(4)
(2)
(3) (4)
PJ.3 (I/O)
3
(3) (4)
ADC10CLK
TMS
PJ.3/ACLK/TCK
JTAG
MODE
SIGNAL
I: 0; O: 1
TDI/TCLK
PJ.2/ADC10CLK/TMS
PJSEL.x
SMCLK
PJ.1 (I/O)
PJ.1/MCLK/TDI/TCLK
PJDIR.x
(3) (4)
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
123
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
6.15 Device Descriptors (TLV)
Table 6-80 shows the contents of the device descriptor tag-length-value (TLV) structure for each device.
Table 6-80. Device Descriptors
Info Block
Die Record
ADC10 Calibration
124
Detailed Description
VALUE
ADDRESS
SIZE
(bytes)
F67641
F67621
Info length
01A00h
1
06h
06h
CRC length
01A01h
1
06h
06h
CRC value
01A02h
2
Per unit
Per unit
Device ID
01A04h
1
39h
38h
DESCRIPTION
Device ID
01A05h
1
82h
82h
Hardware revision
01A06h
1
Per unit
Per unit
Firmware revision
01A07h
1
Per unit
Per unit
Die record tag
01A08h
1
08h
08h
Die record length
01A09h
1
0Ah
0Ah
Lot/wafer ID
01A0Ah
4
Per unit
Per unit
Die X position
01A0Eh
2
Per unit
Per unit
Die Y position
01A10h
2
Per unit
Per unit
Test results
01A12h
2
Per unit
Per unit
ADC10 calibration tag
01A14h
1
13h
13h
ADC10 calibration length
01A15h
1
10h
10h
ADC gain factor
01A16h
2
Per unit
Per unit
ADC offset
01A18h
2
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
2
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
01A1Ch
2
Per unit
Per unit
ADC 2.0-V reference
Temperature sensor 30°C
01A1Eh
2
Per unit
Per unit
ADC 2.0-V reference
Temperature sensor 85°C
01A20h
2
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 30°C
01A22h
2
Per unit
Per unit
ADC 2.5-V reference
Temperature sensor 85°C
01A24h
2
Per unit
Per unit
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
6.16 Identification
6.16.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see Section 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.15.
6.16.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see Section 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.15.
6.16.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming With the JTAG Interface.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Detailed Description
125
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
The following resources provide application guidelines and best practices when designing with the
MSP430F67641 and MSP430F67621 devices.
Implementation of a Low-Cost Three-Phase Watt-Hour Meter Using the MSP430F67641
This application report describes the implementation of a low-cost 3-phase electronic electricity meter
using the TI MSP430F67641 metering processor. This application report includes the necessary
information with regard to metrology software and hardware procedures for this single-chip
implementation.
Class 0.5 Three-Phase Smart Meter Reference Design
This design implements a complete smart meter design using the MSP430F67641 polyphase metering
system on chip. The design meets all requirements for ANSI/IEC Class 0.5 accuracy and the firmware
provided calculates all energy measurement parameters. The F67641 SoC features 128KB of on-chip
flash plus a 320-segment LCD controller for a single-chip solution to low-cost polyphase meter design
challenges.
Features
• Low-cost 3-phase electricity meter for Class 0.5 accuracy
• TI Energy Library firmware that calculates all energy measurement parameters including active and
reactive power and energy, RMS current and voltage, power factor, line frequency, fundamental and
THD readings
• Add-on communications modules for wireless communications standards such as ZigBee®, Wi-Fi®,
Wireless M-Bus, and IEEE Std 802.15.4g for both 2.4 GHz and Sub-1 GHz
• Built-in 160-segment display
• Powered from 3-phase line voltage
126
Applications, Implementation, and Layout
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
8 Device and Documentation Support
8.1
Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
8.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS.
These prefixes represent evolutionary stages of product development from engineering prototypes (XMS)
through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
temperature range, package type, and distribution format. Figure 8-1 provides a legend for reading the
complete device name.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Copyright © 2014–2018, Texas Instruments Incorporated
127
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series
Feature Set
Various levels of integration within a series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 8-1. Device Nomenclature
128
Device and Documentation Support
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
8.3
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at MSP430 Ultra-Low-Power MCUs –
Tools & software.
Table 8-1 lists the debug features of the MSP430F676x1 MCUs. See the Code Composer Studio for
MSP430 User's Guide for details on the available features.
Table 8-1. Hardware Debug Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
No
Design Kits and Evaluation Modules
EVM430-F6779 - 3 Phase Electronic Watt-Hour EVM for Metering This EVM430-F6779 is a threephase electricity meter evaluation module based on the MSP430F6779 device. The E-meter
has inputs for three voltages and three currents, as well as an additional connection to setup
antitampering.
Polyphase Electric Meter With MSP430F67641 SoC This EVM implements a complete smart meter
design using the MSP430F67641 polyphase metering System on Chip. The design meets all
requirements for ANSI/IEC Class 0.5 accuracy. The F67641 SoC features 128KB of on-chip
flash plus a 320-segment LCD controller for a single-chip solution to low-cost polyphase
meter design challenges.
Software
MSP430Ware™ Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 MCU design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
DLMS (Device Language Message Specification) for MSP430 E-meter SoCs The TI DLMS/COSEM
library supports the MSP430 MCU product line. DLMS has been adopted by the IEC TC13
WG14 into the IEC 62056 series of standards.
IEC60730 Software Package The IEC60730 MSP430 software package was developed to help
customers comply with IEC 60730-1:2010 (Automatic Electrical Controls for Household and
Similar Use – Part 1: General Requirements) for up to Class B products, which includes
home appliances, arc detectors, power converters, power tools, e-bikes, and many others.
The IEC60730 MSP430 software package can be embedded in customer applications
running on MSP430s to help simplify the customer’s certification efforts of functional safetycompliant consumer devices to IEC 60730-1:2010 Class B.
MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that
free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough
documentation is delivered through a helpful API Guide, which includes details on each
function call and the recognized parameters. Developers can use Driver Library functions to
write complete projects with minimal overhead.
MSP430F67641, MSP430F67621 Code Examples C Code examples are available for every MSP device
that configures each of the integrated peripherals for various application needs.
Capacitive Touch Software Library Free C libraries for enabling capacitive touch capabilities on
MSP430 MCUs. The MSP430 MCU version of the library features several capacitive touch
implementations including the RO and RC method.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the energy profile of the application
and helps to optimize it for ultra-low-power consumption.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Copyright © 2014–2018, Texas Instruments Incorporated
129
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
www.ti.com
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully use the unique ultra-low-power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and
remarks to highlight areas of your code that can be further optimized for lower power.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost
microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating-point math library of scalar functions that are up to 26 times faster
than the standard MSP430 math functions. Mathlib is easy to integrate into your designs.
This library is free and is integrated in both Code Composer Studio IDE and IAR Embedded
Workbench IDE.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio (CCS) integrated development environment (IDE) supports all MSP
microcontroller devices. CCS comprises a suite of embedded software utilities used to
develop and debug embedded applications. It includes an optimizing C/C++ compiler, source
code editor, project build environment, debugger, profiler, and many other features.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the
MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which lets users quickly begin application development on MSP lowpower MCUs. Creating MCU software usually requires downloading the resulting binary
program to the MSP device for validation and debugging.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
8.4
Documentation Support
The following documents describe the MSP430F676x1 MCUs. Copies of these documents are available
on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (see Section 8.5 for links). In the upper right corner, click the "Alert me" button. This
registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
Errata
MSP430F67641 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP430F67621 Device Erratasheet Describes the known exceptions to the functional specifications.
130
Device and Documentation Support
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
User's Guides
MSP430x5xx and MSP430x6xx Family User's Guide
peripherals available in this device family.
Detailed information
on
the
modules
and
MSP430™ Flash Device Bootloader (BSL) User's Guide The MSP430 bootloader (BSL) (formerly
known as the bootstrap loader) lets users communicate with embedded memory in the
MSP430 microcontroller during the prototyping phase, final production, and in service. Both
the programmable memory (flash memory) and the data memory (RAM) can be modified as
required. Do not confuse the bootloader with the bootstrap loader programs found in some
digital signal processors (DSPs) that automatically load program code (and data) from
external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface This document describes the functions that are
required to erase, program, and verify the memory module of the MSP430 flash-based and
FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
Application Reports
Implementation of a Single-Phase Electronic Watt-Hour Meter Using MSP430F6736(A)
This
application report describes the implementation of a single-phase electronic electricity meter
using the Texas Instruments MSP430F673x(A) metering processor. It also includes the
necessary information with regard to metrology software and hardware procedures for this
single-chip implementation.
Differences Between MSP430F67xx and MSP430F67xxA Devices This application report describes
the enhancements of the MSP430F67xxA devices from the non-A MSP430F67xx devices.
This application report describes the MSP430F67xx errata that are fixed in the
MSP430F67xxA and the additional features added to the MSP430F67xxA devices. In
addition, metrology results are compared to further show that the changes implemented in
the MSP430F67xxA devices do not affect the metrology performance.
MSP430 32-kHz Crystal Oscillators Selection of the correct crystal, correct load circuit, and proper
board layout are important for a stable crystal oscillator. This application report summarizes
crystal oscillator function and explains the parameters to select the correct crystal for
MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to
ensure stable oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs.
Designing With MSP430 and Segment LCDs Segment liquid crystal displays (LCDs) are needed to
provide information to users in a wide variety of applications from smart meters to electronic
shelf labels (ESLs) to medical equipment. Several MSP430 microcontroller families include
built-in low-power LCD driver circuitry that allows the MSP430 MCU to directly control the
segmented LCD glass. This application note helps explain how segmented LCDs work, the
different features of the various LCD modules across the MSP430 MCU family, LCD
hardware layout tips, guidance on writing efficient and easy-to-use LCD driver software, and
an overview of the portfolio of MSP430 devices that include different LCD features to aid in
device selection.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Copyright © 2014–2018, Texas Instruments Incorporated
131
MSP430F67641, MSP430F67621
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
8.5
www.ti.com
Related Links
Table 8-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430F67641
Click here
Click here
Click here
Click here
Click here
MSP430F67621
Click here
Click here
Click here
Click here
Click here
8.6
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.7
Trademarks
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, Code Composer Studio, E2E are trademarks of
Texas Instruments.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
ZigBee is a registered trademark of ZigBee Alliance.
All other trademarks are the property of their respective owners.
8.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.9
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
132
Device and Documentation Support
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
MSP430F67641, MSP430F67621
www.ti.com
SLAS998A – JUNE 2014 – REVISED OCTOBER 2018
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical, Packaging, and Orderable Information
Submit Documentation Feedback
Product Folder Links: MSP430F67641 MSP430F67621
Copyright © 2014–2018, Texas Instruments Incorporated
133
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430F67621IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F67621
MSP430F67621IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F67621
MSP430F67621IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F67621
MSP430F67621IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F67621
MSP430F67641IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F67641
MSP430F67641IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F67641
MSP430F67641IPZ
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F67641
MSP430F67641IPZR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
F67641
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
