HD3SS213
HD3SS213
SLAS901C – DECEMBER 2016 – REVISED JANUARY
2021
SLAS901C – DECEMBER 2016 – REVISED JANUARY 2021
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HD3SS213 5.4-Gbps DisplayPort 1.2a 2:1 and 1:2 Differential Switch
1 Features
3 Description
•
•
The HD3SS213 device is a high-speed passive switch
capable of switching two full DisplayPort 4 lane ports
from one of two sources to one target location in an
application. It also switches one source to one of two
sinks. For DisplayPort applications, the HD3SS213
supports switching of the Auxiliary (AUX), Display
Data Channel (DDC), and Hot Plug Detect (HPD)
signals in the ZEQ package.
•
•
•
•
•
•
•
•
Compatible with DisplayPort 1.2 electrical standard
2:1 and 1:2 switching supporting data rates up to
5.4 Gbps
Supports HPD switching
Supports AUX and DDC switching
Wide –3-dB differential BW of over 5.4 GHz
Excellent dynamic characteristics (at 2.7 GHz):
– Crosstalk = –50 dB
– Isolation = –25 dB
– Insertion loss = –1.5 dB
– Return loss = –13 dB
– Maximum bit-bit skew = 5 ps
VDD Operating range: 3.3 V ±10%
Package Options:
– 5 mm × 5 mm, 50-Pin nFBGA
Output enable (OE) pin disables switch to save
power
HD3SS213 < 10 mW (standby < 30 µW
when OE = L)
One typical application is a mother board that includes
two GPUs that need to drive one DisplayPort sink.
The GPU is selected by the Dx_SEL pin. Another
application is when one source needs to switch
between one of two sinks which the example is a side
connector and a docking station connector. The
switching is controlled using the Dx_SEL and
AUX_SEL pins. The HD3SS213 operates from a
single supply voltage of 3.3 V over the full industrial
temperature range of –40°C to 105°C.
Device Information (1)
PART NUMBER
2 Applications
HD3SS213
•
•
•
(1)
BODY SIZE (NOM)
nFBGA (50)
5.00 mm x 5.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
DAx(p)
4
PC & notebooks
Tablets
Connected peripherals & printers
PACKAGE
DCx(p)
4
4
DAx(n)
4
DCx(n)
AUXAx
2
Source A
DDCA
2
DDCC
DP Sink
AUXCx
2
2
HPDA
HPDC
2
AUXBx
2
DDCB
HPDB
OE
Source B
Dx_SEL
Control
AUX_SEL
4
DBx(p)
4
DBx(n)
HD3SS213 2:1
4
DAx(p)
DCx(p)
4
4
DAx(n)
4
DCx(n)
AUXAx
2
DP Sink A
2
DDCA
DDCC
DP Source
2
HPDA
2
AUXCx
HPDC
2
2
AUXBx
DDCB
HPDB
OE
DP Sink B
Control
Dx_SEL
AUX_SEL
4
DBx(p)
4
DBx(n)
HD3SS213 1:2
Copyright © 2016, Texas Instruments Incorporated
HD3SS213 Application Block Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements.................................................. 7
6.7 Typical Characteristics................................................ 9
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................11
8 Application and Implementation.................................. 12
8.1 Application Information............................................. 12
8.2 Typical Applications.................................................. 13
9 Layout.............................................................................16
9.1 Layout Guidelines..................................................... 16
9.2 Layout Example........................................................ 17
10 Device and Documentation Support..........................18
10.1 Receiving Notification of Documentation Updates..18
10.2 Support Resources................................................. 18
10.3 Trademarks............................................................. 18
10.4 Electrostatic Discharge Caution..............................18
10.5 Glossary..................................................................18
11 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2016) to Revision C (January 2021)
Page
• NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.
This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the
MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be
updated throughout the datasheet......................................................................................................................1
• Changed u*jr BGA to nFBGA............................................................................................................................. 1
• Changed ZQE to ZXH.........................................................................................................................................3
• Changed u*jr ZQE to nFBGA ZXH. Updated thermal data.................................................................................6
• Changed u*jr BGA to nFBGA........................................................................................................................... 10
Changes from Revision A (September 2013) to Revision B (December 2016)
Page
• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes
section, Application and Implementation section, Power Supply Recommendations section, Layout section,
Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.
............................................................................................................................................................................1
• Added A2 to J4 row in Pin Functions table......................................................................................................... 3
Changes from Revision * (September 2013) to Revision A (September 2013)
Page
• Deleted Ordering Information............................................................................................................................. 3
2
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5 Pin Configuration and Functions
1
2
A
Dx_SEL
VDD
B
DC0(n)
DC0(p)
C
3
GND
4
5
6
DA0(n)
DA1(n)
DA2(n)
DA0(p)
DA1(p)
DA2(p)
7
OE
8
9
DA3(p)
DA3(n)
DB0(p)
DB0(n)
AUX_SEL
GND
D
DC1(n)
DC1(p)
DB1(p)
DB1(n)
E
DC2(n)
DC2(p)
DB2(p)
DB2(n)
F
DC3(n)
DC3(p)
DB3(p)
DB3(n)
GND
GND
G
H
AUXC(n)
AUXC(p)
HPDB
GND
DDCCLK_B
AUXB(p)
J
HPDC
HPDA
DDCCLK_C
VDD
DDCDAT_B
AUXB(n)
GND
DDCCLK_A
AUXA(p)
DDCDAT_C DDCDAT_A
AUXA(n)
nFBGA 50-Pin ZXH Package Top View
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION(2)
NO.
NAME
H9,
J9
AUXA(p),
AUXA(n)
I/O
Port A AUX positive signal
Port A AUX negative signal
H6,
J6
AUXB(p),
AUXB(n)
I/O
Port B AUX positive signal
Port B AUX negative signal
H2,
H1
AUXC(p),
AUXC(n)
I/O
Port C AUX positive signal
Port C AUX negative signal
C2
AUX_SEL
I
AUX/DDC selection control pin in conjunction with Dx_SEL Pin
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Table 5-1. Pin Functions (continued)
PIN
DESCRIPTION(2)
NAME
NA
CADA/B/C
I/O
Port A/B/C cable activity detect
B4,
A4
DA0(p),
DA0(n)
I/O
Port A, Channel 0, High speed positive signal
Port A, Channel 0, High speed negative signal
B5,
A5
DA1(p),
DA1(n)
I/O
Port A, Channel 1, High speed positive signal
Port A, Channel 1, High speed negative signal
B6,
A6
DA2(p),
DA2(n)
I/O
Port A, Channel 2, High speed positive signal
Port A, Channel 2, High speed negative signal
A8,
A9
DA3(p),
DA3(n)
I/O
Port A, Channel 3, High speed positive signal
Port A, Channel 3, High speed negative signal
B8,
B9
DB0(p),
DB0(n)
I/O
Port B, Channel 0, High speed positive signal
Port B, Channel 0, High speed negative signal
D8,
D9
DB1(p),
DB1(n)
I/O
Port B, Channel 1, High speed positive signal
Port B, Channel 1, High speed negative signal
E8,
E9
DB2(p),
DB2(n)
I/O
Port B, Channel 2, High speed positive signal
Port B, Channel 2, High speed negative signal
F8,
F9
DB3(p),
DB3(n)
I/O
Port B, Channel 3, High speed positive signal
Port B, Channel 3, High speed negative signal
B2,
B1
DC0(p),
DC0(n)
I/O
Port C, Channel 0, High speed positive signal
Port C, Channel 0, High speed negative signal
D2,
D1
DC1(p),
DC1(n)
I/O
Port C, Channel 1, High speed positive signal
Port C, Channel 1, High speed negative signal
E2,
E1
DC2(p),
DC2(n)
I/O
Port C, Channel 2, High speed positive signal
Port C, Channel 2, High speed negative signal
F2,
F1
DC3(p),
DC3(n)
I/O
Port C, Channel 3, High speed positive signal
Port C, Channel 3, High speed negative signal
H8,
J8
DDCCLK_A,
DDCDAT_A
I/O
Port A DDC clock signal
Port A DDC data signal
H5,
J5
DDCCLK_B,
DDCDAT_B
I/O
Port B DDC clock signal
Port B DDC data signal
J3,
J7
DDCCLK_C,
DDCDAT_C
I/O
Port C DDC clock signal
Port C DDC data signal
A1
Dx_SEL
I
High speed port selection control pins
B3, C8, G2,
G8, H4, H7
GND
S
Ground
J2
HPDA
I/O
Port A hot plug detect
H3
HPDB
I/O
Port B hot plug detect
J1
HPDC
I/O
Port C hot plug detect
B7
OE
I
Output enable:
OE = VIH: Normal operation
OE = VIL: Standby mode
A2,
J4
VDD
S
3.3-V positive power supply voltage
(1)
(2)
4
TYPE(1)
NO.
I = Input, O = Output, S = Supply
The high speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out
when the port is selected.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VDD (2)
Voltage
MIN
MAX
UNIT
–0.5
4
V
Differential I/O
–0.5
4
Control pin
–0.5
VDD + 0.5
Continuous power dissipation
See Section 6.4
Operating free-air temperature, TA
–40
Storage temperature, Tstg
(1)
(2)
V
105
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Typical values for all parameters are at VCC = 3.3 V and TA = 25°C (unless otherwise noted). All temperature limits are
specified by design.
PARAMETER
VDD
TEST CONDITIONS
Supply voltage
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
VDD
V
VDD/2
+ 300 mV
V
–0.1
0.8
V
VPP
VIH
Input high voltage
Control pins and signal pins (Dx_SEL,
AUX_SEL, OE, HPDx)
VIM
Input mid level voltage
AUX_SEL pin
VIL
Input low voltage
Control pins and signal pins (Dx_SEL,
AUX_SEL, OE, HPDx)
VI/O_Diff
Differential voltage
(Dx, AUXx)
Switch I/O differential voltage
0
1.8
Dx switching I/O commonmode voltage
Switch I/O common-mode voltage
0
2
V
AUXx switching I/O commonmode voltage
Switch I/O common-mode voltage
0
3.6
V
IIH
Input high current
(Dx_SEL, AUX_SEL)
VDD = 3.6 V, VIN = VDD
1
µA
IIM
Input mid level current
(AUX_SEL)
VDD = 3.6V, VIN = VDD/2
1
µA
IIL
Input low current
(Dx_SEL, AUX_SEL)
VDD = 3.6 V, VIN = GND
1
µA
Leakage current
(Dx_SEL, AUX_SEL)
VDD = 3.3 V, VI = 2 V, OE = 3.3 V
1
µA
VDD = 3.3 V, VI = 2 V, OE = 3.3 V,
Dx_SEL = 3.3 V
1
VDD = 3.3 V, VI = 2 V, OE = 3.3 V,
Dx_SEL = GND
1
VI/O_CM
ILK
Leakage current (HPDx)
2
VDD/2
– 300 mV
VDD/2
µA
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Typical values for all parameters are at VCC = 3.3 V and TA = 25°C (unless otherwise noted). All temperature limits are
specified by design.
PARAMETER
Ioff
IDD
TEST CONDITIONS
MIN
NOM
Device shut down current
VDD = 3.6 V, OE = GND
Supply current
VDD = 3.6 V,
Dx_SEL or AUX_SEL = VDD or GND
0.6
MAX
UNIT
2.5
µA
1
mA
DA, DB, DC HIGH SPEED SIGNAL PATH
CON
Outputs ON capacitance
VI = 0 V, outputs open, switch ON
1.5
pF
COFF
Outputs OFF capacitance
VI = 0 V, outputs open, switch OFF
1
pF
RON
ON resistance
VDD = 3.3 V, VCM = 0.5 V to 1.5 V,
IO = –40 mA
8
ΔRON
ON resistance match between
pairs of the same channel
VDD = 3.3 V, 0.5 V ≤ VI ≤ 1.2V,
IO = –40 mA
RFLAT_ON
ON resistance flatness,
RON(max) – RON(min)
VDD = 3.3 V, 0.5 V ≤ VI ≤ 1.2 V
12
Ω
1.5
Ω
1.3
Ω
AUXx, DDC SIGNAL PATH
CON
Outputs ON capacitance
VI = 0 V, outputs open, switch ON
9
pF
COFF
Outputs OFF capacitance
VI = 0 V, outputs open, switch OFF
3
pF
RON(AUX)
ON resistance
VDD = 3.3 V, VCM = 0 V – VDD, IO = –8 mA
RON(DDC)
ON resistance on DDC channel VDD = 3.3 V, VCM = 0.4 V, IO = –3 mA
6
10
Ω
20
30
Ω
6.4 Thermal Information
HD3SS213
THERMAL METRIC
nFBGA (ZXH)
UNIT
50 PIN
RθJA
Junction-to-ambient thermal resistance
72.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.9
°C/W
RθJB
Junction-to-board thermal resistance
43.1
°C/W
ψJT
Junction-to-top characterization parameter
1.6
°C/W
ψJB
Junction-to-board characterization parameter
42.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
6.5 Electrical Characteristics
over recommended operating conditions; RL and RSC = 50 Ω (unless otherwise noted)(1)
PARAMETER
RL
Dx differential return loss
XTALK
Dx differential crosstalk
OIRR
Dx differential off-isolation
IL
Dx differential insertion loss
TEST CONDITIONS
6
TYP
MAX
UNIT
–17
2.7 GHz
–13
2.7 GHz
–50
dB
2.7 GHz
–25
dB
f = 1.35 GHz
f = 2.7 GHz
AUX –3-dB bandwidth
(1)
MIN
1.35 GHz
–1
–1.5
360
dB
dB
MHz
For return loss, crosstalk, off-isolation, and insertion loss values, the data was collected on a Rogers material board with minimum
length traces on the input and output of the device under test.
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6.6 Timing Requirements
over recommended operating conditions; RL and RSC = 50 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
ps
tPD
Switch propagation delay
RSC and RL = 50 Ω, see Figure 6-2
Ton
Dx_SEL/AUX_SEL-to-switch Ton
(Data, AUX and DDC)
RSC and RL = 50 Ω, see Figure 6-1
0.7
1
µs
Toff
Dx_SEL/AUX_SEL-to-switch Toff
(Data, AUX and DDC)
RSC and RL = 50 Ω, see Figure 6-1
0.7
1
µs
Ton
Dx_SEL/AUX_SEL-to-switch Ton (HPD)
RL = 50 Ω, see Figure 6-1
0.7
1
µs
Toff
Dx_SEL/AUX_SEL-to-switch Toff (HPD)
RL = 50 Ω, see Figure 6-1
0.7
1
µs
TSK(O)
Inter-pair output skew (CH-CH)
RSC and RL = 1 kΩ, see Figure 6-2
50
ps
TSK(b-b)
Intra-pair output skew (bit-bit)
RSC and RL = 1 kΩ, see Figure 6-2
5
ps
1
50%
Dx_SEL
90%
VOUT
10%
Toff
Ton
Figure 6-1. Select to Switch Ton and Toff
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Vcc
Rsc = 50
DAx/DBx(p)
HD3SS213
DCx(p)
RLoad = 50
Rsc = 50
DCx(n)
DAx/DBx(n)
RLoad = 50
SEL
DAx/DBx(p)
50%
50%
DAx/DBx(n)
DCx(p)
50%
50%
DCx(n)
tP1
t1
tP2
t4
t3
t2
DCx(p)
50%
DCx(n)
tSK(O)
DCy(p)
DCy(n)
tPD = Max(tp1, tp2)
tSK(O) = Difference between tPD for any two pairs of outputs
tSK(b-b) = 0.5 X |(t4 ± t3) + (t1 ± t2)|
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Figure 6-2. Propagation Delay and Skew
8
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6.7 Typical Characteristics
0.0145
7.8
# 10 -3
0.014
7.6
0.0135
7.4
Time (µS)
Time (µS)
0.013
0.0125
0.012
0.0115
0.0105
–40
–20
0
20
40
60
80
100
7
6.8
V = 3.6 V; AUXc to AUXa
V = 3.0 V; AUXc to AUXa
V = 3.6 V; AUXc to AUXb
V = 3.0 V; AUXc to AUXb
0.011
7.2
V = 3.6 V; AUXc to AUXa
V = 3.0 V; AUXc to AUXa
V = 3.6 V; AUXc to AUXb
V = 3.0 V; AUXc to AUXb
6.6
6.4
–40
120
Temperature (ºC)
–20
0
20
40
60
80
100
120
Temperature (ºC)
Figure 6-3. DxSEL to Switch Toff
Figure 6-4. DxSEL to Switch Ton
0.3
0.0135
V = 3.6 V; AUXc to AUXa
V = 3.0 V; AUXc to AUXa
V = 3.6 V; AUXc to AUXb
V = 3.0 V; AUXc to AUXb
0.013
V = 3.6 V; AUXc to AUXa
V = 3.0 V; AUXc to AUXa
V = 3.6 V; AUXc to AUXb
V = 3.0 V; AUXc to AUXb
0.28
0.0125
0.26
Time (µS)
Time (µS)
0.012
0.0115
0.24
0.011
0.22
0.0105
0.2
0.01
0.0095
–40
–20
0
20
40
60
80
100
120
0.18
–40
–20
0
20
40
60
80
100
120
Temperature (ºC)
Temperature (ºC)
Figure 6-5. OUTEN to Switch Toff
Figure 6-6. OUTEN to Switch Ton
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7 Detailed Description
7.1 Overview
The HD3SS213 device is a high-speed passive switch offered in an industry standard 50-pin nFBGA package.
The device is specified to operate from a single supply voltage of 3.3 V over the industrial temperature range of
–40°C to 105°C. The HD3SS213 is a generic 4-CH high-speed mux/demux type of switch that can be used for
routing high-speed signals between two different locations on a circuit board. The HD3SS213 also supports
several other high speed data protocols with a differential amplitude of < 1800 mVPP and a common-mode
voltage of < 2 V, as with USB 3.0 and DisplayPort 1.2. For display port applications, the HD3SS213 also
supports switching of both the auxiliary and hot plug detect signals.
The high speed port selection control inputs of the device, Dx_SEL and AUX_SEL pins can easily be controlled
by available GPIO pins within a system.
7.2 Functional Block Diagram
VDD
DAz(p)
4
DAz(n)
4
SEL=0
4
(z = 0, 1, 2 or 3)
DBz(p)
DBz(n)
4
DCz(p)
DCz(n)
4
4
SEL=1
SEL
Dx_SEL
SEL
HPDA
SEL=0
HPDB
SEL=1
HPDC
AUX_SEL
AUXA(p)
AUXA(n)
AUXB(p)
AUXB(n)
SEL2
SEL
AUXx(P) or DDCCLK_x
AUXx(n) or DDCDAT_x
AUXC(p)
AUXC(n)
DDCCLK_A
DDCCLK_C
DDCDAT_A
DDCDAT_C
DDCCLK_B
DDCDAT_B
OE
HD3SS213
GND
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7.3 Feature Description
The HD3SS213 behaves as a two to one or one to two using high bandwidth pass gates (see Section 7.2). The
input ports are selected using the AUX_SEL and Dx_SEL pins which are shown in Table 7-1.
Table 7-1. AUX/DDC Switch Control Logic
CONTROL LINES
AUX_SEL
SWITCHED I/O PINS
Dx_SEL
AUXA
AUXB
AUXC
DDCA
DDCB
DDCC
L
L
To/From AUXC
Z
To/From AUXA
Z
Z
Z
L
H
Z
To/From AUXC
To/From AUXB
Z
Z
Z
H
L
Z
Z
To/From DDCA
To/From AUXC
Z
Z
H
H
Z
Z
To/From DDCB
Z
To/From AUXC
Z
M
L
To/From AUXC
Z
To/From AUXA
To/From DDCC
Z
To/From DDCA
M
H
Z
To/From AUXC
To/From AUXB
Z
To/From DDCC
To/From DDCB
7.4 Device Functional Modes
The HD3SS213 can be operated in normal operation mode or in shut down mode. In normal operation, the
inputs ports of the HD3SS213 are routed to the output ports according to Table 7-1. In standby mode, the
HD3SS213 is disabled to enable power savings with a typical current consumption of 2.5 µA. The functional
mode is selected through the OE input pin with HIGH for normal operation and LOW for standby.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
Many interfaces require AC coupling between the source and sink. The 0402 capacitors are the preferred option
to provide AC coupling, and the 0603 size capacitors also work. The 0805 size capacitors and C-packs must be
avoided. When placing AC coupling capacitors symmetric placement is best. A capacitor value of 0.1 µF is best
and the value must be match for the ± signal pair. There are several placement options for the AC coupling
capacitors. Because the switch requires a bias voltage, the capacitors must only be placed on one side of the
switch. If they are placed on both sides of the switch, a biasing voltage must be provided. A few placement
options are shown below.
In Figure 8-1, the coupling capacitors are placed on the source pair. In this situation, the switch is biased by the
sink.
DAx(p)
GPU/
Source A
DCx(p)
DAx(n)
DCx(n)
Sink
Control
DBx(p)
GPU/
Source B
Dx_SEL
AUX_SEL
DBx(n)
HD3SS213
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Source Biased by the Sink
In Figure 8-2, the coupling capacitors are placed between the switch and Sink. In this situation, the switch is
biased by the Source
12
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DAx(p)
DCx(p)
DAx(n)
DCx(n)
Sink
Source
Control
Dx_SEL
AUX_SEL
DBx(n)
Sink
HD3SS213
Copyright © 2016, Texas Instruments Incorporated
Figure 8-2. Switch Biased by the Source
8.2 Typical Applications
8.2.1 HD3SS213 AUX Channel in 2:1 Application
Vdd
Vbias
50 Ÿ
AUXa(n)
100 K
AUXc(n)
AUXa(p)
Source A
AUXc(p)
50 Ÿ
Vbias
100 K
Sink connector
Vbias
50 Ÿ
AUXb(n)
AUXb(p)
Source B
OE
50 Ÿ
Dx_SEL
Vbias
Control
AUX_SEL
HD3SS213 2:1
Copyright © 2016, Texas Instruments Incorporated
Figure 8-3. HD3SS213 AUX Channel in 2:1 Application Schematic
8.2.1.1 Design Requirements
Table 8-1 lists the design parameters.
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Table 8-1. Design Parameters
(1)
PARAMETERS
VALUE
Input voltage
3.3 V
Decoupling capacitors
0.1 µF
AC capacitors(1)
75 nF to 200 nF AC capacitors
DAx, AUXAx, AUXBx and DBx require AC capacitors. N lines require AC capacitors. Alternate
mode signals may or may not require AC capacitors.
8.2.1.2 Detailed Design Procedure
•
•
•
•
•
•
Connect VDD and GND pins to the power and ground planes of the printed-circuit board with 0.1-µF bypass
capacitor
Use VDD/2 logic level at AUX_SEL pin
Use 3.3-V TTL/CMOS logic level at Dx_SEL to connect DAx to DCx
Use GND logic level at Dx_SEL to connect DBx to DCx
Use controlled-impedance transmission media for all the differential signals
Ensure the received complimentary signals are with a differential amplitude of
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