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bq24715
SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
bq24715 2-3 Cell NVDC-1 Battery Charger Controller
with Ultra-Fast Transient Response and High Light-Load Efficiency
1 Features
3 Description
•
The bq24715 is a NVDC-1 synchronous battery
charge controller with low quiescent current, high light
load efficiency for 2S or 3S Li-ion battery charging
applications, offering low component count.
1
•
•
•
•
•
•
•
•
•
6-24V Input SMBus NVDC-1 2-3S Battery
Charger Controller
System Instant-on Operation with No Battery or
Deeply Discharged Battery
Ultra-Fast Transient Response of 100 µs
Ultra-Low Quiescent Current of 500 µA and High
PFM Light Load Efficiency 80% at 20mA load to
Meet Energy Star and ErP Lot6
Switching Frequency: 600kHz/800kHz/1MHz
Programmable System/Charge Voltage (16
mV/step), Input/Charge Current (64 mA/step) with
High Accuracy
– ±0.5% Charge Voltage Regulation
– ±3% Input/Charge Current Regulation
– ±2% 40x Input/16x Discharge Current Monitor
Output
Support Battery LEARN Function
Maximize CPU Performance with Deeply
Discharged Battery or No Battery
Integrated NMOS ACFET and RBFET Driver
20-pin 3.5 x 3.5 mm2 QFN Package
The bq24715 provides N-channel ACFET and RBFET
drivers for the power path management. It also
provides driver of the external P-channel battery FET.
The loop compensation is fully integrated.
The bq24715 has programmable 11-bit charge
voltage, 7-bit input/charge current and 6-bit minimal
system voltage with very high regulation accuracies
through the SMBus communication interface.
The v monitors adapter current or battery discharge
current through the IOUT pin allowing the host to
throttle down CPU speed when needed.
The bq24715 provides extensive safety features for
over current, over voltage and MOSFET short circuit.
Device Information(1)
PART NUMBER
bq24715
2 Applications
•
•
•
The power path management allows the system to be
regulated at battery voltage but does not drop below
the programmable system minimum voltage.
PACKAGE
VQFN (20)
BODY SIZE (NOM)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Ultrabook, Notebook, and Tablet PC
Industrial and Medical Equipment
Portable Equipment
4 Simplified Application Diagram
Ultra-Low Quiescent
Current
Ultra-Fast
DPM
Adaptor
Support CPU Turbo Mode
To System
6-24V
Iin
Enhanced Safety
Features
OCP, OVP,
FET Short
Optional
N-FET
Driver
bq24715
Adaptor Detection
Ichg
SMBus Controls V and I
with High Accuracy
PMOS BAT
FET Driver
NVDC-1
Charger
Controller
SMBus
2S-3S
HOST
Iin, Idischarge
Integrated Compensation Internal Soft Start
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24715
SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Application Diagram............................
Revision History.....................................................
Pin Configuration and Function ...........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements .............................................. 10
SMBus Timing Characteristics................................ 11
Typical Characteristics ............................................ 13
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 18
8.5 Programming........................................................... 21
9
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Application ................................................. 28
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 36
12 Device and Documentation Support ................. 37
12.1
12.2
12.3
12.4
12.5
12.6
Third-Party Products Disclaimer ...........................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2014) to Revision B
•
Page
Added Full Production Data specifications to data sheet ...................................................................................................... 4
Changes from Original (March 2013) to Revision A
Page
•
Added device number to the title and added Device Info table per the new data sheet template......................................... 1
•
Changed comment for Address 0x15H in Table 2 from "Any value below 4.096V results in 4.096V" to "Any value
below 4.096V results in default value".................................................................................................................................. 22
•
Changed Setting Input Current description text string from "Thereafter, all input current goes to system load and
input current increases" to "Keep increasing the system current and the battery will run into supplement mode." ............ 27
•
Changed conditions statement for Figure 16 ....................................................................................................................... 33
•
Changed conditions statement forFigure 17......................................................................................................................... 33
2
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SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
6 Pin Configuration and Function
VCC
PHASE
HIDRV
BTST
REGN
RGR Package
20-Pin VQFN
(Top View)
20
19
18
17
16
ACN
1
15
LODRV
ACDRV
4
12
SRN
ACOK
5
11
BATDRV
6
7
8
9
10
CELL
SRP
SCL
GND
13
SDA
14
3
IOUT
2
ACDET
ACP
CMSRC
Pin Descriptions
PIN
NAME
I/O
DESCRIPTION
1
ACN
I
Input current sense resistor negative input. Place an optional 0.1µF ceramic capacitor from ACN to GND for commonmode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
2
ACP
I
Input current sense resistor positive input. Place a 1µF ceramic capacitor from ACP to GND for common-mode
filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
3
CMSRC
I
ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the common source of ACFET (Q1) and
RBFET (Q2) limits the in-rush current on CMSRC pin.
O
Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel
MOSFET (RBFET). ACDRV voltage is 6.1V above CMSRC when voltage on ACDET pin is higher than 2.4V, voltage
on VCC pin is above UVLO but lower than 26V and voltage on VCC pin is 675mV above voltage on SRN pin so that
ACFET and RBFET can be turned on to power the system by AC adapter. Place a 4kΩ resistor from ACDRV to the
gate of ACFET and RBFET limits the in-rush current on ACDRV pin.
4
ACDRV
5
ACOK
O
AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor
when voltage on ACDET pin is above 2.4V, VCC above UVLO but lower than 26V and voltage on VCC pin is 675mV
above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above conditions can
not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to the pull-up
supply rail.
6
ACDET
I
Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to
ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK
comparator and IOUT are both active.
7
IOUT
O
Buffered 40 times adapter or 16 times discharge current output - the differential voltage across sense resistor;
selectable with SMBus command ChargeOption(). Place a 100pF or less ceramic decoupling capacitor from IOUT pin
to GND.
8
SDA
I/O
SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ
pull-up resistor according to SMBus specifications.
9
SCL
I
SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a
10kΩ pull-up resistor according to SMBus specifications.
10
CELL
I
Cell selection pin. For bq24715, set CELL pin Float for 2-cell, and HIGH for 3-cell. Pulling CELL to GND will provide a
hardware exit function from LEARN mode, disable the input DPM function, reset the bit[5] and bit[1] in chargeoption(),
and reset Maxchargevoltage() to previous CELL pin default setting value and chargecurrent() to zero. Release CELL
from GND, charger will recheck CELL pin voltage and lock the new CELL pin selection.
11
BATDRV
O
P-channel battery FET gate driver output. This pin can go high to turn off the battery FET, go low to turn on the
battery FET, or operate battery FET in linear mode to regulate the minimum system voltage when battery is depleted.
Connect the source of the BATFET to the system load voltage node. Connect the drain of the BATFET to the battery
pack positive node. There is an internal pull-down resistor of 50k on BATDRV to ground.
12
SRN
I
Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with a
0.1µF ceramic capacitor to GND for common-mode filtering and connect to current sensing resistor. Connect a 0.1µF
ceramic capacitor between current sensing resistor to provide differential mode filtering.
13
SRP
I
Charge current sense resistor positive input. Connect a 0.1µF ceramic capacitor between current sensing resistor to
provide differential mode filtering.
14
GND
I
IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the
power pad underneath IC.
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SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
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Pin Descriptions (continued)
PIN
NAME
I/O
15
LODRV
O
Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate.
16
REGN
O
Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when
voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from
REGN to GND.
17
BTST
I
High side power MOSFET driver power supply. Connect a 0.047µF-0.1µF capacitor from BTST to PHASE. Connect a
bootstrap Schottky diode from REGN to BTST.
18
HIDRV
O
High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate.
19
PHASE
I
High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
20
VCC
I
Input supply. Use 10Ω resistor and 1µF capacitor to ground as low pass filter to limit inrush current.
I
Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPad plane. Always
solder PowerPad to the board, and have vias on the PowerPad plane connecting to analog ground and power ground
planes. It also serves as a thermal pad to dissipate the heat.
PowerPAD™
DESCRIPTION
7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
SRN, SRP, ACN, ACP, CMSRC, VCC
–0.3
30
PHASE
–2.5
30
ACDET, SDA, SCL, LODRV, REGN, IOUT, ACOK, CELL
–0.3
7
LODRV (20ns)
–2.5
7
BTST, HIDRV, ACDRV
–0.3
36
HIDRV (20ns)
–2.5
36
BATDRV
–0.3
30
Maximum difference voltage SRP–SRN, ACP–ACN
–0.5
+0.5
V
Junction temperature, TJ
–40
155
°C
Storage temperature, Tstg
–55
155
°C
Voltage range
(1)
(2)
UNIT
V
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
7.2 ESD Ratings
V(ESD)
(1)
(2)
4
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins (1)
±2000
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
SRN, SRP, ACN, ACP, CMSRC, VCC
0
24
V
–2
24
V
ACDET, SDA, SCL, LODRV, REGN, IOUT, ACOK, CELL
0
6.5
V
BTST, HIDRV, ACDRV
0
30
V
BATDRV
–0.3
16
V
SRP–SRN, ACP–CAN
–0.2
0.2
V
PHASE
Voltage range
Maximum
difference range
UNIT
TJ
Junction temperature range
–20
125
°C
TA
Operating free-air temperature range
–20
85
°C
7.4 Thermal Information
bq24715
THERMAL METRIC
(1)
RGR Package
(QFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
34.6
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
49.3
°C/W
(2)
RθJB
Junction-to-board thermal resistance
12.5
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
12.7
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
1
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
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SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
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7.5 Electrical Characteristics
6V ≤ VVCC ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
INPUT OPERATING CONDITIONS
VVCC_OP
VCC Input Voltage Operating Range
6
24
V
14.5
V
MIN SYSTEM VOLTAGE REGULATION (0x3E register)
VSYSMIN_RNG
VSYSMIN_REG and
VSYSMIN_REG_ACC
MinSystem Voltage Regulation Range
4.096
Default minimum system voltage and accuracy at
charge enable and battery voltage lower than
VSYSMIN_REG
MinsystemVoltage() = 0x2400H (3S)
MinsystemVoltage() = 0x1800H (2S)
9.216
–2%
V
1.2%
6.144
V
–3%
1.5%
4.096
14.5
MAX SYSTEM VOLTAGE REGULATION (0x15 register charge disable)
VSYSMAX_RNG
MaxSystem Voltage Regulation Range
VSYSMAX_REG and
VSYSMAX_REG_ACC
Default maximum system voltage and accuracy
at charge disable
MaxChargeVoltage() = 0x34C0H (3S)
MaxChargeVoltage() = 0x2330H (2S)
13.504
–2%
V
V
1.2%
9.008
–3%
V
1.5%
MAX CHARGE VOLTAGE REGULATION (0-85C; 0x15 register charge enable)
VBAT_REG_RNG
Battery voltage range
4.096
MaxChargeVoltage() = 0x3130H
VBAT_REG_ACC
Charge voltage regulation accuracy
MaxChargeVoltage() = 0x20D0H
12.529
12.592
–0.5%
8.35
14.5
V
12.655
V
0.5%
8.4
8.45
V
–0.6%
0.6%
0
81.28
mV
4219
mA
CHARGE CURRENT REGULATION (0-85C)
VIREG_CHG_RNG
Charge current regulation differential voltage
range RSNS = 10mΩ
VIREG_CHG = VSRP - VSRN
ChargeCurrent() = 0x1000H
ChargeCurrent() = 0x0800H
ChargeCurrent() = 0x0400H
ChargeCurrent() = 0x0200H
ICHRG_REG_ACC
Charge current regulation accuracy
10mΩ current sensing resistor, VBAT>VSYSMIN
ChargeCurrent() = 0x0180H
ChargeCurrent() = 0x0100H
ChargeCurrent() = 0x00C0H
ChargeCurrent() = 0x0080H
6
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3937
4096
–3%
1946
3%
2048
–5%
921
1024
512
384
256
64
mA
480
mA
340
mA
33%
192
–40%
–60%
614
25%
–33%
115
mA
20%
–25%
172
1127
10%
–20%
288
mA
5%
–10%
410
2150
269
mA
40%
128
192
mA
60%
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SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
Electrical Characteristics (continued)
6V ≤ VVCC ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
268.8
384
499.2
mA
PRECHARGE CURRENT REGULATION (0-85C)
ChargeCurrent() >= 0x0180H
IPRECHRG_REG_ACC
Charge current regulation accuracy 10mΩ current
sensing resistor,
VBAT 6.5V, VACDET>0.6V (0-50mA
load)
5.5
6
6.5
V
75
mA
REGN Current limit
VREGN = 0V, VVCC > UVLO, Converter
enabled and not in TSHUT
50
IREGN_LIM
VREGN = 0V, VVCC > UVLO, Converter
disabled or in TSHUT
7
14
mA
1
μF
REGN REGULATOR
CREGN
REGN Output capacitor required for stability
ILOAD = 100 µA to 50 mA
UNDER VOLTAGE LOCKOUT COMPARATOR (UVLO)
VUVLO_VCC
VUVLO_BAT
Under-voltage rising threshold
VVCC rising
Under-voltage hysteresis, falling
VVCC falling
Under-voltage rising threshold
VSRN rising
Under-voltage hysteresis, falling
VSRN falling
3
3.2
3.4
400
3
3.3
3.6
400
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V
mV
V
mV
7
bq24715
SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
www.ti.com
Electrical Characteristics (continued)
6V ≤ VVCC ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
13.3
20
μA
VBAT = 12.6V, VSRN>UVLO, BATFET
turns on,
ACDET 2.4V,
CELL pull up, TJ = –20°C to 85°C. No
switching.
540
700
µA
ISTANDBY plus supply current in PFM,
200mW output; Reg0x12[10]=0; MOSFET
Qg=4 nC;
1.5
ISTANDBY plus supply current in PFM,
200mW output; Reg0x12[10]=1; MOSFET
Qg=4 nC;
5
QUIESCENT CURRENT
IBAT_BATFET_ON
Standby mode. System powered by battery.
BATFET ON.
ISRN+ISRP+IPHASE+IBTST+IACP+IACN+ICMSRC
Adapter standby quiescent current,
IVCC+IACP+IACN+ICMSRC
ISTANDBY
IAC_SWLIGHT
IAC_SW
Adapter current, IVCC+IACP+IACN+ICMSRC
VBAT = 12.6V, VSRN >UVLO, BATFET
turns on,
ACDETUVLO, VACDET rising
2.376
2.4
2.424
VACOK_FALL_HYS
ACOK Falling hysteresis
VVCC>UVLO, VACDET falling
35
55
75
mV
V
VWAKEUP_RISE
WAKEUP Detect rising threshold
VVCC>UVLO, VACDET rising
0.52
0.6
V
VWAKEUP_FALL
WAKEUP Detect falling threshold
VVCC>UVLO, VACDET falling
0.35
0.46
120
250
V
VCC to SRN COMPARATOR (VCC_SRN), SLEEP
VVCC-SRN_FALL
VCC-SRN Falling threshold
VVCC falling towards VSRN
VVCC-SRN
VCC-SRN Rising hysteresis
VVCC rising above VSRN
300
mV
ChargeOption() bit [7] = 1
330%
IDPM
_RHYS
375
mV
INPUT OVER-CURRENT COMPARATOR
ACP to ACN Rising Threshold, respect to input
current().
ACOC
ACOC floor
50
mV
180
mV
1.25
mV
2.5
mV
Chargeoption() bit [6] =0
250
mV
Chargeoption() bit [6] =1 (default)
350
mV
ACOC ceiling
LIGHT LOAD COMPARATOR
ACP to ACN Falling Threshold, average
Converter CCM-DCM, current decrease
ACP to ACN Rising Threshold, average
CONVERTER OVER-CURRENT COMPARATOR (ILIM_HI), CYCLE-BY-CYCLE
ILIM_HI
Converter over current limit, measure GND-PH
CONVERTER UNDER-CURRENT COMPARATOR (ILIM_LOW) , CYCLE-BY-CYCLE
Converter over current limit, measure GND-PH
–2
0
6
mV
24
26
28
V
INPUT OVER-VOLTAGE (ACOVP)
VACOVP
VCC Over-Voltage Rising Threshold
VCC rising
VACOV_HYS
VCC Over-Voltage Falling Hysteresis
VCC falling
8
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V
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SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
Electrical Characteristics (continued)
6V ≤ VVCC ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
102.5%
104%
106%
UNIT
BAT OVER-VOLTAGE COMPARATOR (BAT_OVP)
VOVP_RISE
Over-voltage rising threshold as percentage of
VBAT_REG
VSRN rising
VOVP_FALL
Over-voltage falling threshold as percentage of
VBAT_REG
VSRN falling
Discharge current during OVP, SRP pin
Charge enable, BATFET ON
102%
4
mA
SYSTEM OVER-VOLTAGE COMPARATOR (SYS_OVP)
VSYSOVP_RISE_3S
3S System over-voltage rising threshold
VSYSOVP_FALL_3S
3S System over-voltage falling threshold
VSYSOVP_RISE_2S
2S System over-voltage rising threshold
VSYSOVP_FALL_2S
2S System over-voltage falling threshold
VSRN rising, chargeoption bit[12]=0 default
15.1
VSRN rising, chargeoption bit[12]=1
17.0
VSRN falling
13.2
VSRN rising, chargeoption bit[12]=0 default
10.1
VSRN rising, chargeoption bit[12]=1
11.3
VSRN falling
V
V
V
8.8
Discharge current during OVP
V
4
mA
THERMAL SHUTDOWN COMPARATOR (TSHUT)
TSHUT
Thermal shutdown rising temperature
Temperature rising
155
°C
TSHUT_HYS
Thermal shutdown hysteresis, falling
Temperature falling
20
°C
LOGIC INPUT (SDA, SCL)
VIN_ LO
Input low threshold
VIN_ HI
Input high threshold
IIN_ LEAK
Input bias current
0.8
V
1
μA
500
mV
1
μA
2.1
V=7V
V
–1
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA)
VOUT_ LO
Output saturation voltage
5 mA drain current
IOUT_ LEAK
Leakage current
V=7V
–1
ANALOG INPUT (ACDET)
IIN_ LEAK
Input bias current
V=7V
Offset
–1
1
μA
–10
10
mV
1.0
V
1.8
V
ANALOG INPUT (CELL)
GND
Float (2S setting)
1.2
High (3S setting)
2.5
V
Internal pull up resistor to REGN
405
kΩ
Internal pull down resistor to GND
141
kΩ
PWM OSCILLATOR
FSW
FSW_min
PWM Switching frequency
Audio frequency limit, PFM
ChargeOption () bit [9:8] = 00
–10%
600
10%
kHz
ChargeOption() bit [9:8] = 01 (Default)
–10%
800
10%
kHz
ChargeOption() bit [9:8] = 10
–10%
1000
10%
kHz
ChargeOption() bit [10] = 1
40
kHz
ACFET GATE DRIVER (ACDRV)
IACFET
ACDRV Charge pump current limit
VACFET
Gate drive voltage on ACFET
RACDRV_LOAD
Minimum load resistance between ACDRV and
CMSRC
RACDRV_OFF
ACDRV Turn-off resistance
I = 30 μA
VACFET_LOW
ACDRV Turn-off when Vgs voltage is lower than
VACFET (Specified by design)
The voltage below VACFET
VACDRV – VCMSRC when VVCC > UVLO
40
60
5.5
6.1
μA
6.7
500
5
V
kΩ
6.2
7.4
0.2
kΩ
V
BATTERY FET GATE DRIVER (BATDRV)
RDS_BAT_OFF
BATFET Turn-off resistance
100µA current into BATDRV
2
kΩ
RDS_BAT_ON
BATFET Turn-on resistance
100µA current from BATDRV
5
kΩ
BATFET Drive voltage
VBATDRV_REG =VSRN – VBATDRV
when VAVCC > 5 V and BATFET is on
VBATDRV_REG
4.2
8
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Electrical Characteristics (continued)
6V ≤ VVCC ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON
High side driver turn-on resistance
VBTST – VPH = 5.5 V, I = 10 mA
RDS_HI_OFF
High side driver turn-off resistance
VBTST – VPH = 5.5 V, I = 10 mA
Bootstrap refresh comparator threshold voltage
VBTST – VPH when low side refresh pulse is
requested
VBTST_REFRESH
3.85
4
5.5
Ω
0.65
1.3
Ω
4.15
4.7
V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON
Low side driver turn-on resistance
VREGN=6V, I=10mA
4
6.2
Ω
RDS_LO_OFF
Low side driver turn-off resistance
VREGN=6V, I=10mA
0.9
1.4
Ω
In CCM mode 10 mΩ current sensing
resistor
64
INTERNAL SOFT START
ISTEP
Soft start current step
mA
7.6 Timing Requirements
6V ≤ VVCC ≤ 24V, –20°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
2
3
95
160
237
µs
0.76
1.28
1.9
ms
ACOK COMPARATOR
VACOK_RISE_DEG
ACOK Rising deglitch (Specified by design)
VVCC>UVLO, VACDET rising above 2.4V
ms
VCC to SRN COMPARATOR (VCC_SRN), SLEEP
VCC-SRN falling delay
VCC falling towards VSRN
Resume time
VVCC rising above VSRN
INPUT OVER-CURRENT COMPARATOR
Relax time, No latch.
300
ms
INPUT OVER-VOLTAGE (ACOVP)
Rising deglitch
VCC rising
0.1
ms
Falling deglitch
VCC falling
1
ms
1
ms
24
µs
BAT OVER-VOLTAGE COMPARATOR (BAT_OVP)
Over voltage deglitch time to fully turn-off
BATFET
SYSTEM OVER-VOLTAGE COMPARATOR (SYS_OVP)
tSYSOVP_DEG
System over-voltage deglitch time to turn-off
ACDRV
THERMAL SHUTDOWN COMPARATOR (TSHUT)
Rising deglitch
100
µs
Falling deglitch
10
ms
ANALOG INPUT (CELL)
Allowed max delay time to config CELL at POR
72
100
120
ms
PWM DRIVER TIMING
tLOW_HIGH
Driver dead time from low side to high side
20
ns
tHIGH_LOW
Driver dead time from high side to low side
20
ns
24
μs
INTERNAL SOFT START
Soft start current step time
10
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7.7 SMBus Timing Characteristics
4.5 V ≤ V(VCC) ≤ 24 V, 0°C ≤ TJ ≤125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
MIN
TYP MAX
1
UNIT
tR
SCLK/SDATA rise time
tF
SCLK/SDATA fall time
µs
tW(H)
SCLK pulse width high
4
tW(L)
SCLK Pulse Width Low
4.7
µs
tSU(STA)
Setup time for START condition
4.7
µs
tH(STA)
START condition hold time after which first clock pulse is generated
4
µs
tSU(DAT)
Data setup time
250
ns
tH(DAT)
Data hold time
300
ns
tSU(STOP)
Setup time for STOP condition
4
µs
t(BUF)
Bus free time between START and STOP condition
4.7
µs
FS(CL)
Clock Frequency
10
100
kHz
25
35
ms
300
ns
50
µs
HOST COMMUNICATION FAILURE
(1)
ttimeout
SMBus bus release timeout
tBOOT
Deglitch for watchdog reset signal
10
Watchdog timeout period, ChargeOption() bit [14:13] = 01
tWDI
(1)
(2)
(2)
Watchdog timeout period, ChargeOption() bit [14:13] = 10
(2)
Watchdog timeout period, ChargeOption() bit [14:13] = 11
(2)
(Default)
ms
35
44
53
70
88
105
140
175
210
s
Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
User can adjust threshold via SMBus ChargeOption() REG0x12.
Figure 1. SMBus Communication Timing Waveforms
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Figure 2. SMBus Writing Timing
A
B
C
D
E
F
G
H
I
J
K
tLOW tHIGH
SMBCLK
SMBDATA
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:DAT
tSU:STO tBUF
A = START CONDITION
E = SLAVE PULLS SMBDATA LINE LOW
I = ACKNOWLEDGE CLOCK PULSE
B = MSB OF ADDRESS CLOCKED INTO SLAVE
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
J = STOP CONDITION
C = LSB OF ADDRESS CLOCKED INTO SLAVE
G = MSB OF DATA CLOCKED INTO MASTER
K = NEW START CONDITION
D = R/W BIT CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO MASTER
Figure 3. SMBus Read Timing
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7.8 Typical Characteristics
100%
100%
90%
98%
80%
96%
60%
VSYS = 13.5 V
50%
VSYS = 12.6 V
40%
30%
VSYS = 9 V
20%
VSYS = 8.4 V
10%
VSYS = 6 V
Efficiency
Efficiency
70%
94%
92%
90%
88%
19.5Vin_12.6Vbat
0%
0
0.02
0.04
0.06
0.08
0.1
19.5Vin_8.4Vbat
86%
0
System Load Current (A)
2
4
6
8
10
System Load Current (A)
VIN = 19.5 V
Figure 4. Light Load Efficiency vs. System Current
VIN = 19.5 V
Figure 5. Heavy Load Efficiency vs. System Current
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8 Detailed Description
8.1 Overview
The bq24715 is a 2-3 cell battery charge controller with power selection for multi-chemistry portable applications
such as notebook and ultrabook. It supports wide input range of input sources from 6 V to 24 V, and 2-3 cell
battery.
The bq24715 supports automatic system power source selection with separate drivers for n-channel MOSFETs
on the adapter side, and p-channel MOSFETs on the battery side.
The bq24715 features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter
overloading. During battery charging, as the system power increases, the charging current will reduce to maintain
total input current below adapter rating. If system power demand is temporarily exceeds adapter rating, the
bq24715 supports NVDC architecture to allow battery discharge energy to supplement system power
The SMBus controls input current, charge current and charge voltage registers with high resolution, high
accuracy regulation limits.
14
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8.2 Functional Block Diagram
3.2V
UVLO
VCC
ACDRV
CHARGE
PUMP
ACDRV
ACDRV_CMSRC
20
CMSRC+5.9V
EN_REGN
ACGOOD
ACDET
6
0.6V
ACOK_DRV
WAKEUP
4
ACDRV
3
CMSRC
11
BATDRV
17
BTST
18
HIDRV
19
PHASE
16
REGN
15
LODRV
14
GND
SYSOVP
ACOC
ACOVP
26V
SRN
SELECTOR
LOGIC
EN_CHRG
ACGOOD
EN_PRECHRG
SRN-6V
VCC_SRN
EN_FASTCHRG
2.4V
ACOK
EN_SUPPLEMENT
EN_LDOMODE
5
ACOK_DRV
2ms Rising
Deglitch
WD_TIMEOUT
VREF_IAC
FBO
ACP
2
ACN
1
IOUT
7
40X
CHARGE_INHIBIT
MUX
DAC_VALID
IOUT_SEL
SRN
13
EN_LEARN
16X
VREF_ICHG
12
EN_CHRG
EN_DPM
1X
SRP
WATCHDOG
TIMER 175s**
BATOVP or
SYSOVP
EN_PRECHRG
PWM/PFM
CONVERTER
CONTROL
EN_FASTCHRG
EN_SUPPLEMENT
EN_AUDIOFREQ
EN_CHRG
VFB
CELL_LOW
4mA
VREF_VREG
Tj
TSHUT
WAKEUP
155C
SRP
GND_PHASE
VREF_SYSMIN
ILIM_HI
350mV**
10uA
GND
ILIM_LOW
PHASE
DAC_VALID
CHARGE_INHIBIT
SMBUS Interface
SDA
SCL
8
9
EN_LEARN
VREF_VREG
ChargeOption()
ChargeCurrent()
ChargeVoltage()
InputCurrent()
MinsysVoltage()
ManufactureID()
DeviceID()
1.25mV
LIGHT_LOAD
ACP_ACN
PWM
DRIVER
LOGIC
EN_REGN
REGN
LDO
ACP_ACN
ACOC
VREF_ICHG
3.33xVREF_IAC**
VREF_IAC
VREF_SYSMIN
IOUT_SEL
EN_DPM
EN_AUDIOFREQ
4.15V
REFRESH
BTST_PH
SRN
BATOVP
104%VREF_VREG
EN_LDOMODE
IOUT_SEL
VCC
VCC_SRN
SRN+675mV
bq24715
SRN
SYSOVP
CELL_CNT
CELL
10
TRI-STAT
BUFFER
VSYSOVP**
** Threshold is adjustable
by ChargeOption()
CELL_LO
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8.3 Feature Description
8.3.1 Switching Frequency Adjust
The charger switching frequency can be adjusted ±25% to solve EMI issue via SMBus command.
ChargeOption() bit [9:8] can be used to set switching frequency.
If frequency is reduced, the current ripple is increased. Inductor value must be carefully selected so that it will not
trigger cycle-by-cycle peak over current protection even for the worst condition such as higher input voltage, 50%
duty cycle, lower inductance and lower switching frequency.
8.3.2 High Accuracy Current Sense Amplifiers
If LOWPOWER bit is zero (ChargeOption() bit[15] = 0), as an industry standard, high accuracy current sense
amplifiers (CSA) are used to monitor the input current or the discharge current, selectable via SMBUS, see Table
3. Once VCC is above UVLO and ACDET is above 0.6V, input current CSA turns on and the IOUT output
becomes valid. Once SRN is above UVLO and ChargeOption() bit[15] = 0, discharge current CSA turns on and
the IOUT output becomes valid. The CSA senses voltage across the input sense resistor by a factor of 40 or
across the output sense resistor by a factor of 16 through the IOUT pin. To lower the voltage on current
monitoring, a resistor divider from IOUT to GND can be used and accuracy over temperature can still be
achieved.
If LOWPOWER bit is "1" (ChargeOption() bit[15] = 1) and only a valid battery (BAT>UVLO) is connected to
system with an input adaptor (ACDET UVLO;
• VACDET > 2.4V
• VVCC-VSRN > 675mV (not in sleep mode);
8.3.11 ACFET/RBFET Control
The ACDRV drives a pair of common-source (CMSRC) n-channel power MOSFETs (ACFET: Q1A and RBFET:
Q1B) between adapter and converter. The ACFET separates adapter from converter, and provides a limited di/dt
when plugging in adapter by controlling the ACFET turn-on time. The RBFET provides battery discharge
protection when adapter voltage is lower than battery, and minimizes system power dissipation with its low
RDS(on) compared to a Schottky diode.
When adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off. And BATFET is
turned on to discharge battery. After adapter is detected (ACDET pin voltage higher than 2.4V), adapter begins
to provide power to system.
The gate drive voltage on ACFET and RBFET is VCMSRC+6V. If the ACFET and RBFET have been turned on for
20ms, and the voltage across ACDRV and CMSRC is still 0.2V below VACFET, ACFET and RBFET will be turned
off.
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Feature Description (continued)
To limit the in-rush current on ACDRV pin and CMSRC pin, a 4kΩ resistor is recommended on each of the three
pins.
To limit the adapter inrush current when ACFET is turned on to provide power converter from adapter, the
external Cgs and Cgd capacitor of ACFET must be carefully selected. The larger the Cgs and Cgd capacitance,
the slower turn on of ACFET will be and less inrush current of adapter. However, if Cgs and Cgd is too large, the
ACDRV-CMSRC voltage may still be low after 20ms turn on time window is expired. To make sure ACFET will
not be turned on when adapter is hot plug in, the Cgs value should be 20 times or higher of Cgd.
8.3.12 DPM
When the input current exceeds the input current limit setting and IPM_EN is enabled (ChargeOption() bit [1]=1),
the bq24715 decreases the charge current to provide priority to system load current. As the system current rises,
the available charge current drops linearly to zero. Higher systems loads can be drawn from the battery, battery
discharges and BATFET is turned on when discharge current is higher than 256mA.
To reduce the risk for overcharging battery at battery insertion, please disable charge if the battery is absent.
8.3.13 Buck Converter Power up
After the ACFET is turned on, the converter is enabled and the HSFET and LSFET start switching. Every time
the buck converter is started, the IC automatically applies soft-start (no soft-start when exit LEARN) on buck
output current to avoid any overshoot or stress on the output capacitors or the power converter. The buck output
current starts at 128mA, and the step size is 64mA in CCM mode for a 10mΩ current sensing resistor. Each step
lasts around 24µs in CCM mode, until it reaches the programmed charge current limit. No external components
are needed for this function.
When power up, converter output voltage is default value set by CELL pin configuration. After converter starts
switching about 100ms, CELL pin setting is locked. If CELL pin is pulled to LOW when power-up, converter
output is default 2S for bq24715.
8.4 Device Functional Modes
8.4.1 LDO Mode and Minimum System Voltage
The BATDRV drives a p-channel BATFET between converter output (system node) and battery to provide a
charge and discharge path for battery. When battery voltage is below the minimum system voltage setting, this
BATFET works in linear mode as LDO (default chargeoption() bit[2]=1, the precharge current is set by
ChargeCurrent() and clamped below 384mA) thus to keep system node voltage always higher than the minimum
system voltage setting. If battery voltage reaches the minimum system voltage, BATFET fully turns on. This LDO
function can be optionally disabled by set "LDO Mode Enable" bit low (chargeoption() bit[2]=0) and BATFET is
fully turned on. At this condition, the battery pack internal circuit will maintain battery terminal voltage higher than
system minimum voltage. And the precharge current also determined by battery pack internal circuit.
18
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Device Functional Modes (continued)
MaxChargeVoltage
MinSystemVoltage
2.7 V
0 mV
ChargeCurrent
LDO Mode Enable
384 mA
0 mA
LDO Mode Disable
128 mA
0 mA
Figure 6. ChargeOption[2] (LDO Mode)
8.4.2 PWM Mode Converter Operation
The synchronous buck PWM converter uses a fixed frequency voltage control scheme and internal type III
compensation network. The LC output filter gives a characteristic resonant frequency
1
fo =
2p Lo Co
(1)
The resonant frequency fo is used to determine the compensation to ensure there is sufficient phase margin for
the target bandwidth. Suggested component value as charge current of 800Hz default switching frequency is
shown in Table 8.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Table 1. Suggested Component Value as Output Current of Default 800-kHz
Switching Frequency
Component
Recommended Value
Output Inductor Lo (µH)
3.3 or 2.2
System node capacitor (µF)
47- 350 (1)
SRN node Capacitor Co (µF)
0.1-1
Sense Resistor (mΩ)
10
(1)
If system capacitance is higher than 350µF, please contact TI techniclal support.
The bq24715 has four loops of regulation: input current, charge current, charge voltage and minimum system
voltage. The four loops are brought together internally at the error amplifier. The maximum voltage of the four
loops appears at the output of the error amplifier EAO. An internal saw-tooth ramp is compared to the internal
error control signal EAO to vary the duty-cycle of the converter.
When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth
ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below VBTST_REFRESH,
a refresh cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can
achieve duty cycle of up to 99.5% with pulse skip.
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8.4.3 Continuous Conduction Mode (CCM)
With sufficient charge current, the inductor current never crosses zero, which is defined as Continuous
Conduction Mode. The controller starts a new cycle with ramp coming up from 200mV. As long as EAO voltage
is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO
voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of each switching cycle, ramp gets
reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to
prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode
of the low-side power MOSFET conducts the inductor current.
During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the
LSFET turn-on keeps the power dissipation low, and allows safely at high output currents.
8.4.4 Discontinuous Conduction Mode (DCM)
When LSFET is turned on, the inductor current will decrease. If this current goes to zero, the converter enters
Discontinuous Conduction Mode. Every cycle, when the voltage across ACP and ACN falls below 1.25mV
(125mA on 10mΩ), the light-load comparator turns off LSFET to avoid negative inductor current, which may
boost the system via the body diode of HSFET. There is also a cycle-by-cycle converter under-current
comparator monitor the LFET current and prevent it goes negative.
During the DCM mode the loop response automatically changes. It changes to a single pole system and the pole
is proportional to the load current.
8.4.5 PFM Mode
In order to improve converter light-load efficiency, the bq24715 switches to PFM control at light load with charge
disable or charge in LDO mode. The effective switching frequency will decrease accordingly when system load
decreases. The minimum frequency can be limit to 40kHz if set IDPM_EN bit high (ChargeOption() bit[10]=1). To
have higher light load efficiency, set "Audio Frequency Limit" bit low (Chargeoption() bit[10]=0, default).
8.4.6 Learn Mode
A battery LEARN cycle can be activated via SMBus "LEARN Enable" command (ChargeOption() bit[5]=1 enable
Learn Mode). When LEARN is enabled with an adapter connected, the system power switch to battery by turning
off converter and keep ACFET/BATFET on. Learn mode allows the battery to discharge in order to calibrate the
battery gas gauge over a complete discharge/charge cycle. When LEARN is disabled, the system power switch
to adapter by turning on converter in a few hundreds µs.
The bq24715 also supports hardware pin to exist LEARN mode by pulling CELL to GND. When Cell pin is pulled
to GND,bq24715 resets "LEARN Enable" (ChargeOption() bit[5]) and IDPM_EN (ChargeOption() bit[1]), and
reset chargevoltage() and chargecurrent().
8.4.7 IDPM Disable at Battery Removal
CELL pull to GND can also be used to disable IDPM function automatically when battery is removed.
When battery present, IOUT monitors discharge current and CPU can do throttling when IOUT is higher than
battery discharge limit.
When battery is removed, CELL is pulled to GND. IC disables input DPM function and switch IOUT to monitor
input current, thus CPU throttling when IOUT higher than limit.
After insert battery back, EC need set bit[1]=1 to enable IDPM function.
• Customer who has external discharge current monitor can set "FIX IOUT" ChargeOption() bit[3]=1 and "IOUT
Selection" ChargeOption() bit[4]=0 to have fixed IOUT monitoring adapter current.
• Customer who has external adapter current monitor can set "FIX IOUT" ChargeOption() bit[3]=1 and "IOUT
Selection" ChargeOption() bit[4]=1 to have fixed IOUT monitoring discharge current.
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8.5 Programming
8.5.1 SMBus Communication
8.5.1.1 SMBus Interface
The bq24715 supports SMBus communication interface. Gas gauge broadcasting mode is supported.
The bq24715 operates as a slave, receiving control inputs from the embedded controller host through the SMBus
interface. The device uses a simplified subset of the commands documented in System Management Bus
Specification V1.1, which can be downloaded from www.smbus.org. The bq24715 uses the SMBus Read-Word
and Write-Word protocols (Figure 7) to communicate with the smart battery. The bq24715 performs only as a
SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In
addition, the device has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit manufacturer
ID register (0xFEH).
SMBus communication is enabled with the following conditions:
• VVCC or VSRN is above UVLO;
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 2 and
Figure 3 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is
low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24715 because either the
master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24715
supports the charger commands as described in Table 2.
8.5.1.1.1 Write-Word Format
S
SLAVE ADDRESS
7 BITS
MSB m LSB
Preset to 0b0001001
W
1b
0
ACK
1b
0
COMMAND BYTE
8 BITS
MSB m LSB
ChargeCurrent() = 0x14H
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
MinSysVoltage() = 0x3EH
ChargeOption() = 0x12H
ACK
1b
0
LOW DATA BYTE
8 BITS
MSB m LSB
D7 m D0
ACK
1b
0
HIGH DATA BYTE
8 BITS
MSB m LSB
ACK
1b
0
P
D15mD0
8.5.1.1.2 Read-Word Format
S
SLAVE
ADDRESS
W
ACK
7 BITS
1b
MSB m LSB
0
Preset to 0b0001001
COMMAND
BYTE
ACK
SLAVE
ADDRESS
R
ACK
1b
8 BITS
0
MSB m LSB
1b
8 BITS
1b
0
MSB m LSB
1
DeviceID() = 0xFFH
ManufactureID() = 0xFEH
ChargeCurrent() = 0x14H
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
MinSysVoltage() = 0x3EH
ChargeOption() = 0x12H
S
LOW DATA
BYTE
ACK
1b
8 BITS
0
MSB m LSB
Preset to
0b0001001
D7mD0
HIGH DATA
BYTE
NACK
1b
8 BITS
1b
0
MSB m LSB
1
D15mD0
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Copyright © 2013–2016, Texas Instruments Incorporated
Product Folder Links: bq24715
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21
bq24715
SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
www.ti.com
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 7. SMBus Write-Word and Read-Word Protocols
8.5.1.2 SMBus Commands
The bq24715 supports seven battery-charger commands that use either Write-Word or Read-Word protocols, as
summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24715. The
ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x0010H.
Table 2. Battery Charger Command Summary
REGISTER
ADDRESS
NAME
0x12H
ChargeOption()
READ/WRITE
Read or Write
DESCRIPTION
Charger Options Control
COMMENT
● Default E144H
● Default 0mA, 64mA Step
● Range:128mA -8.128A
0x14H
ChargeCurrent()
Read or Write
7-Bit Charge Current
Setting
● Bit [15] [14][13] value is ignored and counted as zero.
Any value below 64mA results in zero.
Write 64mA only is ignored
● 0mA disable charge
● Default 2S-9V, 3S-13.5V;
0x15H
MaxChargeVoltage()
Read or Write
11-Bit Charge Voltage
Setting
● 16mV Step
● Range: 4.096V – 14.5V
● Any value below 4.096V results in default value; not allow
chargervoltage lower than minsystemvoltage
● Default 2S-6.144V, 3S-9.216V;
0x3EH
MinSystemVoltage()
Read or Write
6-Bit Minimum System
Voltage Setting
● 256mV Step
● Range: 4.096V – 14.5V
● Any value out of range is ignored; not allow minsystemvoltage
higher than chargervoltage.
● Default 3.2A, 64mA Step
7-Bit Input Current Setting
● Range:128mA -8.064A
0x3FH
InputCurrent()
Read or Write
0xFEH
ManufacturerID()
Read Only
Manufacturer ID
0x0040H
0xFFH
DeviceID()
Read Only
Device ID
0x0010H
● Any value out of range is ignored.
22
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Copyright © 2013–2016, Texas Instruments Incorporated
Product Folder Links: bq24715
bq24715
www.ti.com
SLUSBD1B – MARCH 2013 – REVISED SEPTEMBER 2016
8.5.1.3 Setting Charger Options
By writing ChargeOption() command (0x12H or 0b00010010), bq24715 allows users to change several charger
options after POR (Power On Reset) as shown in Table 3.
Table 3. Charge Options Register (0x12H)
BIT
[15]
BIT NAME
DESCRIPTION
LOWPOWER
Effective on BAT power only (ACDET
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