I2C-CPEV

User's Guide SNVA343A – April 2008 – Revised April 2013 AN-1840 USB I2C Interface Board Reference Manual This application note discusses the features, requirements, and usages of the USB I2C Interface board. 1 2 3 4 5 6 Contents Introduction .................................................................................................................. USB I2C Interface Board Key Features .................................................................................. Block Diagram ............................................................................................................... System Requirements ...................................................................................................... 4.1 Hardware Requirements .......................................................................................... Serial Interface and Programming Connectors ......................................................................... 5.1 Serial Interface “J” ................................................................................................. 5.2 Electrical Characteristics of I2C .................................................................................. 2 I C Compatible Interface ................................................................................................... 6.1 I2C Signals .......................................................................................................... 6.2 I2C Data Validity .................................................................................................... 6.3 I2C Start and Stop Conditions .................................................................................... 6.4 Transferring Data .................................................................................................. 2 2 2 2 2 3 3 4 4 4 4 4 5 List of Figures 1 Block Diagram ............................................................................................................... 2 2 USB I2C Interface Module .................................................................................................. 3 3 I2C Signals: Data Validity................................................................................................... 4 4 START and STOP Conditions ............................................................................................. 5 5 I2C Chip Address ............................................................................................................ 5 6 I2C Write Cycle .............................................................................................................. 5 7 I2C Read Cycle .............................................................................................................. 6 All trademarks are the property of their respective owners. SNVA343A – April 2008 – Revised April 2013 Submit Documentation Feedback AN-1840 USB I2C Interface Board Reference Manual Copyright © 2008–2013, Texas Instruments Incorporated 1 Introduction 1 www.ti.com Introduction The USB I2C Interface board interacts with your application hardware via an USB port in a PC. The microcontroller with flash memory enables to control your application hardware and develop specific application functions via software. (Texas Instruments does not provide interaction software, which networks both application board and I2C board). 2 USB I2C Interface Board Key Features • • • • • • 3 TI’s COP8CBE9 microcontroller in a TSSOP package TI’s USBN9604 IC in a 28-pin PLGA package USB 2.0 compatible Bus powered 24 MHz clock from crystal 8–pin analog inputs for A/D converter Block Diagram Figure 1 shows basic connections between the PC, USB I2C Interface Module, and application board. Figure 1. Block Diagram 4 System Requirements The following requirements are vital in order to use the USB I2C Interface Module: System Requirements • Windows Operating System (Win98/ME/2000/XP) • 32 MB RAM minimum) • 2 MB available for disk space 4.1 Hardware Requirements • 2 5-Pin Mini-B USB 2.0 cable (sold separately) AN-1840 USB I2C Interface Board Reference Manual Copyright © 2008–2013, Texas Instruments Incorporated SNVA343A – April 2008 – Revised April 2013 Submit Documentation Feedback Serial Interface and Programming Connectors www.ti.com Figure 2. USB I2C Interface Module 5 Serial Interface and Programming Connectors 5.1 Serial Interface “J” The table below shows the pin configuration for the COP8 controller for all interface modes. (1) (2) Pin Name I2C Board Pin/COP8 Pin Comment SDA (Data out) SDA / 40 R = 2 kΩ (1) SCL (Clock) SCL / 39 R = 2 kΩ (1) Analog Ch. 6/GPIO A5 / 38 (2) Analog Ch. 5/GPIO A4 / 37 (2) Analog Ch. 4/GPIO A3 / 36 (2) Analog Ch. 3/GPIO A2 / 35 (2) Analog Ch. 2/GPIO A1 / 34 (2) Analog Ch. 1/GPIO A0 / 33 (2) Must have a pull-up resistor on application hardware for SCL and SDA lines. Do not use any of A5 - A0 pins as a ground connection. Connect both application and I2C grounds together to make a good ground connection between the two boards. (Refer to I2C picture for GND pin.) SNVA343A – April 2008 – Revised April 2013 Submit Documentation Feedback AN-1840 USB I2C Interface Board Reference Manual Copyright © 2008–2013, Texas Instruments Incorporated 3 I2C Compatible Interface 5.2 www.ti.com 2 Electrical Characteristics of I C The USB I2C board requires 5V from a computer to function correctly. The maximum current that the I2C board will draw from the computer is 500 mA. This I2C board will function within the temperature range of 0°C ≤ TA ≤ 70°C. For further information about the devices on the I2C board, refer to the following links: COP8CBE9/CCE9 8-Bit CMOS Flash Microcontroller with 8k Memory, Virtual EEPROM, 10- Bit A/D and Brownout Reset (SNOS978) 150-mA Low-Noise, Low-Dropout Regulator With Shutdown (SLVS522) 6 I2C Compatible Interface 6.1 I2C Signals In I2C-compatible mode, the SCL pin is used for the I2C clock and the SDA pin is used for the I2C data. Each of these signals need a pull-up resistor according to I2C specification. The values of the pull-up resistors are determined by the capacitance of the bus (typ. ~2k). See I2C specification from Phillips for further details. Signal timing specifications are according to the I2C bus specification. Maximum frequency is 400 KHz. 6.2 I2C Data Validity The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW. SCL SDA data change allowed data valid data change allowed data valid data change allowed Figure 3. I2C Signals: Data Validity 6.3 I2C Start and Stop Conditions START and STOP bits signify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 4 AN-1840 USB I2C Interface Board Reference Manual Copyright © 2008–2013, Texas Instruments Incorporated SNVA343A – April 2008 – Revised April 2013 Submit Documentation Feedback I2C Compatible Interface www.ti.com SDA SCL S P START condition STO P condition Figure 4. START and STOP Conditions 6.4 Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. All clock pulses are generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. Figure 5. I2C Chip Address MSB LSB reg addr_7 reg addr_6 reg addr_5 AI reg addr_3 reg addr_2 reg addr_1 reg addr_0 bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 1 2 3 4 5 6 7 8 2 I C SLAVE register address Figure 6. I2C Write Cycle ack from slave ack from slave start msb Chip Address lsb w ack msb Register Add lsb ack w ack addr = 02h ack ack from slave msb DATA lsb ack stop ack stop SCL SDA start Id = TBDh DGGUHVV K¶02 data w = write (SDA = '0') r = read (SDA = '1') ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = chip address SNVA343A – April 2008 – Revised April 2013 Submit Documentation Feedback AN-1840 USB I2C Interface Board Reference Manual Copyright © 2008–2013, Texas Instruments Incorporated 5 I2C Compatible Interface www.ti.com When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. Figure 7. I2C Read Cycle ack from slave start msb Chip Address lsb w ack from slave repeated start msb Register Add lsb ack from slave data from slave rs msb Chip Address lsb rs id = 36h r msb DATA ack from master lsb stop SCL SDA start 6 id = TBDh w ack addr = K¶00 ack AN-1840 USB I2C Interface Board Reference Manual Copyright © 2008–2013, Texas Instruments Incorporated r ack $GGUHVV K¶00 data ack stop SNVA343A – April 2008 – Revised April 2013 Submit Documentation Feedback IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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