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INA240A2PW

INA240A2PW

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP8

  • 描述:

    IC CURR SENSE 1 CIRCUIT 8TSSOP

  • 数据手册
  • 价格&库存
INA240A2PW 数据手册
INA240 SBOS662C – JULY 2016 – REVISED DECEMBER 2021 INA240 –4-V to 80-V, Bidirectional, Ultra-Precise Current Sense Amplifier With Enhanced PWM Rejection 1 Features 3 Description • • The INA240 device is a voltage-output, current-sense amplifier with enhanced PWM rejection that can sense drops across shunt resistors over a wide common-mode voltage range from –4 V to 80 V, independent of the supply voltage. The negative common-mode voltage allows the device to operate below ground, accommodating the flyback period of typical solenoid applications. Enhanced PWM rejection provides high levels of suppression for large common-mode transients (ΔV/Δt) in systems that use pulse width modulation (PWM) signals (such as motor drives and solenoid control systems). This feature allows for accurate current measurements without large transients and associated recovery ripple on the output voltage. • 2 Applications • • • • • • Motor Controls Solenoid and Valve Controls Power Management Actuator Controls Pressure Regulators Telecom Equipment This device operates from a single 2.7-V to 5.5-V power supply, drawing a maximum of 2.4 mA of supply current. Four fixed gains are available: 20 V/V, 50 V/V, 100 V/V, and 200 V/V. The low offset of the zero-drift architecture enables current sensing with maximum drops across the shunt as low as 10-mV full-scale. All versions are specified over the extended operating temperature range (–40°C to +125°C), and are offered in an 8-pin TSSOP and 8-pin SOIC packages. Device Information(1) PART NUMBER INA240 Supply (2.7 V to 5.5 V) (1) PACKAGE BODY SIZE (NOM) TSSOP (8) 3.00 mm × 4.40 mm SOIC (8) 4.90 mm × 3.91 mm For all available packages, see the package option addendum at the end of the data sheet. IN± + IN+ OUT REF2 REF1 Typical Application 270 270 Y1 240 240 210 210 180 180 150 3.5 150 1.5 Common-Mode Step 1 INA240 OUT 0.5 3 2.5 2 120 90 03.50 Y1 -0.53 2.5 -1 2 1.5 -1.5 60 30 0 -30 DDDDDDDDDDDDDINA240 Output • Common-Mode StepDDDDDDDDDDDDD • • Enhanced PWM Rejection Excellent CMRR: – 132-dB DC CMRR – 93-dB AC CMRR at 50 kHz Wide Common-Mode Range: –4 V to 80 V Accuracy: – Gain: • Gain Error: 0.20% (Maximum) • Gain Drift: 2.5 ppm/°C (Maximum) – Offset: • Offset Voltage: ±25 μV (Maximum) • Offset Drift: 250 nV/°C (Maximum) Available Gains: – INA240A1: 20 V/V – INA240A2: 50 V/V – INA240A3: 100 V/V – INA240A4: 200 V/V Quiescent Current: 2.4 mA (Maximum) Time (2 µs/div) D004 Enhanced PWM Rejection An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison......................................................... 3 6 Pin Configuration and Functions...................................3 7 Specifications.................................................................. 4 7.1 Absolute Maximum Ratings........................................ 4 7.2 ESD Ratings............................................................... 4 7.3 Recommended Operating Conditions.........................4 7.4 Thermal Information....................................................4 7.5 Electrical Characteristics.............................................5 7.6 Typical Characteristics................................................ 6 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................12 9 Application and Implementation.................................. 18 9.1 Application Information............................................. 18 9.2 Typical Applications.................................................. 20 9.3 What to Do and What Not to Do............................... 23 10 Power Supply Recommendations..............................23 10.1 Power Supply Decoupling.......................................23 11 Layout........................................................................... 24 11.1 Layout Guidelines................................................... 24 11.2 Layout Example...................................................... 24 12 Device and Documentation Support..........................26 12.1 Documentation Support.......................................... 26 12.2 Receiving Notification of Documentation Updates..26 12.3 Support Resources................................................. 26 12.4 Trademarks............................................................. 26 12.5 Electrostatic Discharge Caution..............................26 12.6 Glossary..................................................................26 13 Mechanical, Packaging, and Orderable Information.................................................................... 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (October 2017) to Revision C (December 2021) Page • Changed D (SOIC) package size from: 4.00 mm × 3.91 mm to: 4.90 mm × 3.91 mm....................................... 1 • Added text or leave unconnected. to the NC pin description..............................................................................3 Changes from Revision A (October 2016) to Revision B (October 2017) Page • Added D (SOIC) package to Device Information table ...................................................................................... 1 • Added Description (cont.) section ......................................................................................................................1 • Added preview label to 8-pin TSSOP package...................................................................................................1 • Added D (SOIC) pinout diagram and table to Pin Configuration and Functions section ................................... 3 • Changed y-axis values in Figure 7-15 ............................................................................................................... 6 • Added Figure 11-2 ........................................................................................................................................... 24 Changes from Revision * (July 2016) to Revision A (October 2016) Page • Changed document status from Product Preview to Production Data ...............................................................1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 5 Device Comparison Table 5-1. Device Comparison PRODUCT GAIN (V/V) INA240A1 20 INA240A2 50 INA240A3 100 INA240A4 200 6 Pin Configuration and Functions NC 1 8 OUT IN± 1 8 IN+ IN+ 2 7 REF1 GND 2 7 REF1 IN± 3 6 REF2 REF2 3 6 VS GND 4 5 VS NC 4 5 OUT Not to scale Not to scale NC- no internal connection NC- no internal connection Figure 6-1. INA240 PW Package 8-Pin TSSOP Top View Figure 6-2. INA240 D Package 8-Pin SOIC Top View Table 6-1. Pin Functions PIN I/O DESCRIPTION PW (TSSOP) D (SOIC) GND 4 2 IN– 3 1 Analog input Connect to load side of shunt resistor IN+ 2 8 Analog input Connect to supply side of shunt resistor NC 1 4 — OUT 8 5 Analog output REF1 7 7 Analog input Reference 1 voltage. Connect to 0 V to VS; see the Adjusting the Output Midpoint With the Reference Pins section for connection options REF2 6 3 Analog input Reference 2 voltage. Connect to 0 V to VS; see the Adjusting the Output Midpoint With the Reference Pins section for connection options VS 5 6 — NAME Analog Ground Reserved. Connect to ground or leave floating Output voltage Power supply, 2.7 V to 5.5 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 3 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN Supply voltage MAX UNIT 6 V Differential (VIN+) – (VIN–) –80 80 Common-mode –6 90 REF1, REF2, NC inputs GND – 0.3 VS + 0.3 V Output GND – 0.3 VS + 0.3 V –55 150 °C 150 °C 150 °C Analog inputs, VIN+, VIN– (2) Operating free-air temperature, TA Junction temperature, TJ Storage temperature, Tstg (1) (2) –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. VIN+ and VIN– are the voltages at the IN+ and IN– pins, respectively. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCM Common-mode input voltage –4 80 V VS Operating supply voltage 2.7 5.5 V TA Operating free-air temperature –40 125 °C 7.4 Thermal Information INA240 THERMAL METRIC(1) D (SOIC) UNIT 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 149.1 113.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 33.2 51.9 °C/W RθJB Junction-to-board thermal resistance 78.4 57.8 °C/W ψJT Junction-to-top characterization parameter 1.5 10.2 °C/W ψJB Junction-to-board characterization parameter 76.4 56.9 °C/W (1) 4 PW (TSSOP) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 7.5 Electrical Characteristics at TA = 25 °C, VS = 5 V, VSENSE = VIN+ – VIN–, VCM = 12 V, and VREF1 = VREF2 = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VCM Common-mode input range CMRR Common-mode rejection ratio VIN+ = –4 V to 80 V, VSENSE = 0 mV TA = – 40°C to 125°C –4 VIN+ = –4 V to 80 V, VSENSE = 0 mV TA = –40°C to 125°C 120 f = 50 kHz VOS Offset voltage, input-referred VSENSE = 0 mV dVOS/dT Offset voltage drift VSENSE = 0 mV, TA = –40°C to 125°C PSRR Power-supply rejection ratio VS = 2.7 V to 5.5 V, VSENSE = 0 mV TA = –40°C to 125°C IB Input bias current IB+, IB–, VSENSE = 0 mV Reference input range 80 132 V dB 93 ±5 ±25 µV ±50 ±250 nV/°C ±1 ±10 µV/V 90 0 µA VS V OUTPUT G Gain INA240A1 20 INA240A2 50 INA240A3 100 INA240A4 Gain error RVRR Reference divider accuracy VOUT = | (VREF1 – VREF2) | / 2 at VSENSE = 0 mV, TA = –40°C to 125°C Maximum capacitive load VOLTAGE ±0.05% TA = –40°C to 125°C GND + 10 mV ≤ VOUT ≤ VS – 200 mV Reference voltage rejection ratio (input-referred) 200 GND + 50 mV ≤ VOUT ≤ VS – 200 mV Non-linearity error V/V ±0.5 ±0.20% ±2.5 ppm/°C ±0.01% 0.02% INA240A1 20 INA240A3 5 INA240A2, INA240A4 2 No sustained oscillation 1 0.1% µV/V nF OUTPUT(2) Swing to VS power-supply rail RL = 10 kΩ to GND TA = –40°C to 125°C VS – 0.05 VS – 0.2 Swing to GND RL = 10 kΩ to GND, VSENSE = 0 mV VREF1 = VREF2 = 0 V, TA = –40°C to 125°C VGND + 1 VGND + 10 V mV FREQUENCY RESPONSE BW Bandwidth Settling time - output settles to 0.5% of final value SR All gains, –3-dB bandwidth 400 All gains, 2% THD+N(1) 100 INA240A1 9.6 INA240A4 9.8 Slew rate kHz µs 2 V/µs 40 nV/√ Hz NOISE (INPUT REFERRED) Voltage noise density POWER SUPPLY VS IQ Operating voltage range Quiescent current TA = –40°C to 125°C 2.7 VSENSE = 0 mV 5.5 1.8 IQ vs temperature, TA = –40°C to 125°C 2.4 2.6 V mA TEMPERATURE RANGE Specified range (1) (2) –40 125 °C See the Input Signal Bandwidth section for more details. See Figure 7-13. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 5 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 7.6 Typical Characteristics at TA = 25°C, VS = 5 V, VCM = 12 V, and VREF = VS / 2 (unless otherwise noted) 50 40 Population Offset Voltage (ɥV) 30 20 10 0 -10 -20 -30 -40 -25 0 -15 -13.5 -12 -10.5 -9 -7.5 -6 -4.5 -3 -1.5 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 -50 -50 100 50 75 Temperature (°C) 125 150 175 . D001 VOS (PV) 25 All gains Figure 7-2. Offset Voltage vs Temperature Figure 7-1. Input Offset Voltage Production Distribution 0.4 0.3 Population CMRR ( ɥV/V) 0.2 0.1 0 -0.1 -0.2 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -0.3 -50 D003 -25 0 25 50 75 100 Temperature (°C) 125 150 175 . CMR (PV/V) Figure 7-4. Common-Mode Rejection Ratio vs Temperature All gains -0.15 -0.135 -0.12 -0.105 -0.09 -0.075 -0.06 -0.045 -0.03 -0.015 0 0.015 0.03 0.045 0.06 0.075 0.09 0.105 0.12 0.135 0.15 -0.2 -0.18 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 Population Population Figure 7-3. Common-Mode Rejection Production Distribution Gain Error (%) Gain Error (%) D501 D502 INA240A1 INA240A2 Figure 7-5. Gain Error Production Distribution 6 Figure 7-6. Gain Error Production Distribution Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 7.6 Typical Characteristics (continued) -0.2 -0.18 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 -0.2 -0.18 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 Population Population at TA = 25°C, VS = 5 V, VCM = 12 V, and VREF = VS / 2 (unless otherwise noted) D503 Gain Error (%) D504 INA240A3 Gain Error (%) . INA240A4 Figure 7-7. Gain Error Production Distribution Figure 7-8. Gain Error Production Distribution 60 INA240A4 100 INA240A3 75 INA240A3 50 40 INA240A4 Gain (dB) Gain Error (m%) 50 25 0 20 INA240A2 INA240A2 -25 30 INA240A1 10 -50 0 INA240A1 -75 -100 -50 -10 10 -25 0 25 50 75 100 Temperature (°C) 125 150 100 175 1k 10k 100k Frequency (Hz) VCM = 0 V Figure 7-9. Gain Error vs Temperature 1M 10M VDIF = 10-mVPP sine Figure 7-10. Gain vs Frequency 150 140 135 120 CMRR (dB) PSRR (dB) 120 100 80 105 90 60 75 40 60 1 10 100 1k 10k Frequency (Hz) 100k 1M Figure 7-11. Power-Supply Rejection Ratio vs Frequency 1 10 100 1k 10k Frequency (Hz) 100k 1M Figure 7-12. Common-Mode Rejection Ratio vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 7 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 7.6 Typical Characteristics (continued) at TA = 25°C, VS = 5 V, VCM = 12 V, and VREF = VS / 2 (unless otherwise noted) 240 25qC 125qC -40qC 200 VS - 1 Input Bias Current ( PA) Output Voltage Swing (V) VS VS - 2 GND + 3 GND + 2 GND + 1 160 120 80 40 0 GND 0 1 2 3 4 Output Current (mA) 5 6 7 -40 -10 D010 0 10 20 30 40 50 60 Common-Mode Voltage (V) . 70 80 90 D011 VS = 5 V Figure 7-13. Output Voltage Swing vs Output Current Figure 7-14. Input Bias Current vs Common-Mode Voltage 200 100 95 90 Input Bias Current (ɥA) Input Bias Current (PA) 160 120 80 40 85 80 75 70 65 60 0 55 -40 -10 0 10 20 30 40 50 60 Common-Mode Voltage (V) 70 80 90 50 -50 -25 0 25 50 75 100 Temperature (°C) D012 125 150 175 . VS = 0 V Figure 7-16. Input Bias Current vs Temperature Figure 7-15. Input Bias Current vs Common-Mode Voltage 100 2 1.6 1.4 Refered-to-Input Voltage Noise (nV/—Hz) Quiescent Current (mA) 1.8 VS= 2.7-V VS= 3.3-V 1.2 VS= 5-V 1 0.8 0.6 0.4 0.2 0 -50 10 -25 0 25 50 75 100 Temperature (°C) 125 150 Figure 7-17. Quiescent Current vs Temperature 8 175 1 10 100 1k 10k Frequency (Hz) 100k 1M Figure 7-18. Input-Referred Voltage Noise vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 7.6 Typical Characteristics (continued) at TA = 25°C, VS = 5 V, VCM = 12 V, and VREF = VS / 2 (unless otherwise noted) Referred-to-Input Voltage Noise (200 nV/div) Output Voltage (0.5 V/div) 2-VPP Output Signal Input Voltage (5 mV/div) 0 10-mVPP Input Signal 0 Time (10 Ps/div) Time (1 s/div) D017 D016 VCM = 0 V Input referred VDIF = 0 V Figure 7-20. Step Response 3.5 120 1.5 60 30 0 -30 3 2.5 2 13.5 Y1 0.5 3 2.5 02 1.5 Common-Mode Input Signal -0.5 1 INA240 Output 1 -1 Time (0.25 Ps/div) Common-Mode Input SignalDDDDDDDDDDDD 240 240 Y1210 240 210 180 180 150 150 INA240 Output Common-Mode Input SignalDDDDDDDDDDDD Figure 7-19. 0.1-Hz to 10-Hz Voltage Noise 90 10-mVPP input step 240 240 Y1210 240 210 180 180 150 150 120 90 60 30 0 -30 3.5 3 2.5 2 1.5 Common-Mode Input Signal INA240 Output 13.5 Y1 0.5 3 2.5 02 1.5 -0.5 1 1 -1 Time (0.25 Ps/div) D021 INA240 Output VS = ±2.5 V VREF1 = VREF2 = 0 V VREF1 = VREF2 = 0 V . D022 Rising edge Falling edge Output (1.5 V/div) 0 Supply Voltage (2.5 V/div) Figure 7-21. Common-Mode Voltage Transient Response 0 Figure 7-22. Common-Mode Voltage Transient Response Time (2 Ps/div) D019 VREF1 = VREF2 = 0 V Figure 7-23. Start-Up Response Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 9 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 8 Detailed Description 8.1 Overview The INA240 is a current-sense amplifier that offers a wide common-mode range, precision, zero-drift topology, excellent common-mode rejection ratio (CMRR), and features enhanced pulse width modulation (PWM) rejection. Enhanced PWM rejection reduces the effect of common-mode transients on the output signal that are associated with PWM signals. Multiple gain versions are available to allow for the optimization of the desired full-scale output voltage based on the target current range expected in the application. 8.2 Functional Block Diagram VS IN± IN+ PWM Rejection ± OUT + 50 k REF2 50 k REF1 GND 8.3 Feature Description 8.3.1 Amplifier Input Signal The INA240 is designed to handle large common-mode transients over a wide voltage range. Input signals from current measurement applications for linear and PWM applications can be connected to the amplifier to provide a highly accurate output, with minimal common-mode transient artifacts. 8.3.1.1 Enhanced PWM Rejection Operation The enhanced PWM rejection feature of the INA240 provides increased attenuation of large common-mode ΔV/Δt transients. Large ΔV/Δt common-mode transients associated with PWM signals are employed in applications such as motor or solenoid drive and switching power supplies. Traditionally, large ΔV/Δt commonmode transitions are handled strictly by increasing the amplifier signal bandwidth, which can increase chip size, complexity and ultimately cost. The INA240 is designed with high common-mode rejection techniques to reduce large ΔV/Δt transients before the system is disturbed as a result of these large signals. The high AC CMRR, in conjunction with signal bandwidth, allows the INA240 to provide minimal output transients and ringing compared with standard circuit approaches. 8.3.1.2 Input Signal Bandwidth The INA240 input signal, which represents the current being measured, is accurately measured with minimal disturbance from large ΔV/Δt common-mode transients as previously described. For PWM signals typically associated with motors, solenoids, and other switching applications, the current being monitored varies at a significantly slower rate than the faster PWM frequency. The INA240 bandwidth is defined by the –3-dB bandwidth of the current-sense amplifier inside the device; see the Electrical Characteristics table. The device bandwidth provides fast throughput and fast response required for the rapid detection and processing of overcurrent events. Without the higher bandwidth, protection circuitry may not have adequate response time and damage may occur to the monitored application or circuit. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 Figure 8-1 shows the performance profile of the device over frequency. Harmonic distortion increases at the upper end of the amplifier bandwidth with no adverse change in detection of overcurrent events. However, increased distortion at the highest frequencies must be considered when the measured current bandwidth begins to approach the INA240 bandwidth. For applications requiring distortion sensitive signals, Figure 8-1 provides information to show that there is an optimal frequency performance range for the amplifier. The full amplifier bandwidth is always available for fast overcurrent events at the same time that the lower frequency signals are amplified at a low distortion level. The output signal accuracy is reduced for frequencies closer to the maximum bandwidth. Individual requirements determine the acceptable limits of distortion for high-frequency, current-sensing applications. Testing and evaluation in the end application or circuit is required to determine the acceptance criteria and to validate the performance levels meet the system specifications. 10% THD+N 1% 0.1% 90% FS Input 0.01% 1 10 100 1k 10k Frequency (Hz) 100k 1M D006 Figure 8-1. Performance Over Frequency 8.3.2 Selecting the Sense Resistor (RSENSE) The INA240 determines the current magnitude from measuring the differential voltage developed across a resistor. This resistor is referred to as a current-sensing resistor or a current-shunt resistor. The flexible design of the device allows a wide input signal range across this current-sensing resistor. The current-sensing resistor is ideally chosen solely based on the full-scale current to be measured, the full-scale input range of the circuitry following the device, and the device gain selected. The minimum currentsensing resistor is a design-based decision in order to maximize the input range of the signal chain circuitry. Full-scale output signals that are not maximized to the full input range of the system circuitry limit the ability of the system to exercise the full dynamic range of system control. Two important factors to consider when finalizing the current-sensing resistor value are: the required current measurement accuracy and the maximum power dissipation across the resistor. A larger resistor voltage provides for a more accurate measurement, but increases the power dissipation in the resistor. The increased power dissipation generates heat, which reduces the sense resistor accuracy because of the temperature coefficient. The voltage signal measurement uncertainty is reduced when the input signal gets larger because any fixed errors become a smaller percentage of the measured signal. The design trade-off to improve measurement accuracy increases the current-sensing resistor value. The increased resistance value results in an increased power dissipation in the system which can additionally decrease the overall system accuracy. Based on these relationships, the measurement accuracy is inversely proportional to both the resistance value and power dissipation contributed by the current-shunt selection. By increasing the current-shunt resistor, the differential voltage is increased across the resistor. Larger input differential voltages require a smaller amplifier gain to achieve a full-scale amplifier output voltage. Smaller current-shunt resistors are desired but require large amplifier gain settings. The larger gain settings often have increased error and noise parameters, which are not attractive for precision designs. Historically, the design goals for high-performance measurements forced designers to accept selecting larger current-sense resistors and the lower gain amplifier settings. The INA240 provides 100-V/V and 200-V/V gain options that offer the Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 11 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 high-gain setting and maintains high-performance levels with offset values below 25 µV. These devices allow for the use of lower shunt resistor values to achieve lower power dissipation and still meet high system performance specifications. Table 8-1 shows an example of the different results obtained from using two different gain versions of the INA240. From the table data, the higher gain device allows a smaller current-shunt resistor and decreased power dissipation in the element. The Calculating Total Error section provides information on the error calculations that must be considered in addition to the gain and current-shunt value when designing with the INA240. Table 8-1. RSENSE Selection and Power Dissipation(1) PARAMETER Gain VDIFF Ideal maximum differential input voltage RSENSE Current-sense resistor value PRSENSE Current-sense resistor power dissipation (1) RESULTS EQUATION INA240A1 INA240A4 — 20 V/V 200 V/V VDIFF = VOUT / Gain 150 mV 15 mV RSENSE = VDIFF / IMAX 15 mΩ 1.5 mΩ RSENSE × IMAX 2 1.5 W 0.15 W Full-scale current = 10 A, and full-scale output voltage = 3 V. 8.4 Device Functional Modes 8.4.1 Adjusting the Output Midpoint With the Reference Pins Figure 8-2 shows a test circuit for reference-divider accuracy. The INA240 output is configurable to allow for unidirectional or bidirectional operation. VS VS IN± ± IN+ OUT + REF2 REF1 GND Figure 8-2. Test Circuit For Reference Divider Accuracy Note Do not connect the REF1 pin or the REF2 pin to any voltage source lower than GND or higher than VS. The output voltage is set by applying a voltage or voltages to the reference voltage inputs, REF1 and REF2. The reference inputs are connected to an internal gain network. There is no operational difference between the two reference pins. 8.4.2 Reference Pin Connections for Unidirectional Current Measurements Unidirectional operation allows current measurements through a resistive shunt in one direction. For unidirectional operation, connect the device reference pins together and then to the negative rail (see the Ground Referenced Output section) or the positive rail (see the VS Referenced Output section). The required differential input polarity depends on the output voltage setting. The amplifier output moves away from the referenced rail proportional to the current passing through the external shunt resistor. If the amplifier reference pins are connected to the positive rail, then the input polarity must be negative to move the amplifier output down 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 (towards ground). If the amplifier reference pins are connected at ground, then the input polarity must be positive to move the amplifier output up (towards supply). The following sections describe how to configure the output for unidirectional operation cases. 8.4.2.1 Ground Referenced Output When using the INA240 in a unidirectional mode with a ground referenced output, both reference inputs are connected to ground; this configuration takes the output to ground when there is a 0-V differential at the input (as Figure 8-3 shows). VS VS IN± ± OUT + REF2 IN+ REF1 GND Figure 8-3. Ground Referenced Output 8.4.2.2 VS Referenced Output Unidirectional mode with a VS referenced output is configured by connecting both reference pins to the positive supply. Use this configuration for circuits that require power-up and stabilization of the amplifier output signal and other control circuitry before power is applied to the load (as shown in Figure 8-4). VS VS IN± ± OUT + REF2 IN+ REF1 GND Figure 8-4. VS Referenced Output 8.4.3 Reference Pin Connections for Bidirectional Current Measurements Bidirectional operation allows the INA240 to measure currents through a resistive shunt in two directions. For this operation case, the output voltage can be set anywhere within the reference input limits. A common configuration is to set the reference inputs at half-scale for equal range in both directions. However, the reference inputs can be set to a voltage other than half-scale when the bidirectional current is non-symmetrical. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 13 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 8.4.3.1 Output Set to External Reference Voltage Connecting both pins together and then to a reference voltage results in an output voltage equal to the reference voltage for the condition of shorted input pins or a 0-V differential input; this configuration is shown in Figure 8-5. The output voltage decreases below the reference voltage when the IN+ pin is negative relative to the IN– pin and increases when the IN+ pin is positive relative to the IN– pin. This technique is the most accurate way to bias the output to a precise voltage. VS VS IN± ± OUT + IN+ REF2 REF1 REF5025 2.5-V Reference GND Copyright © 2016, Texas Instruments Incorporated Figure 8-5. External Reference Output 8.4.3.2 Output Set to Midsupply Voltage By connecting one reference pin to VS and the other to the GND pin, the output is set at half of the supply when there is no differential input, as shown in Figure 8-6. This method creates a ratiometric offset to the supply voltage, where the output voltage remains at VS / 2 for 0 V applied to the inputs. VS VS IN± ± + IN+ OUT Output REF2 REF1 GND Figure 8-6. Midsupply Voltage Output 8.4.3.3 Output Set to Mid-External Reference In this case, an external reference is divided by two by connecting one REF pin to ground and the other REF pin to the reference, as shown in Figure 8-7. 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 VS VS IN± ± OUT + IN+ REF2 REF1 REF5025 2.5-V Reference GND Copyright © 2016, Texas Instruments Incorporated Figure 8-7. Mid-External Reference Output 8.4.3.4 Output Set Using Resistor Divider The INA240 REF1 and REF2 pins allow for the midpoint of the output voltage to be adjusted for system circuitry connections to analog to digital converters (ADCs) or other amplifiers. The REF pins are designed to be connected directly to supply, ground, or a low-impedance reference voltage. The REF pins can be connected together and biased using a resistor divider to achieve a custom output voltage. If the amplifier is used in this configuration, as shown in Figure 8-8, use the output as a differential signal with respect to the resistor divider voltage. Use of the amplifier output as a single-ended signal in this configuration is not recommended because the internal impedance shifts can adversely affect device performance specifications. VS VS IN± IN+ ± R1 OUT TO ADC+ + TO ADC± REF2 REF1 R2 GND Figure 8-8. Setting the Reference Using a Resistor Divider 8.4.4 Calculating Total Error The INA240 electrical specifications (see the Electrical Characteristics table) include typical individual errors terms (such as gain error, offset error, and nonlinearity error). Total error, including all of these individual error components, is not specified in the Electrical Characteristics table. In order to accurately calculate the expected error of the device, the device operating conditions must first be known. Some current-shunt monitors specify a total error in the product data sheet. However, this total error term is accurate under only one particular set of operating conditions. Specifying the total error at this point has limited value because any deviation from these specific operating conditions no longer yields the same total error value. This section discusses the individual error sources and how the device total error value can be calculated from the combination of these errors for specific conditions. Two examples are provided in Table 8-2 and Table 8-3 that detail how different operating conditions can affect the total error calculations. Typical and maximum calculations are shown as well to provide the user more information on how much error variance is present from device to device. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 15 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 8.4.4.1 Error Sources The typical error sources that have the largest effect on the total error of the device are gain error, nonlinearity, common-mode rejection ratio, and input offset voltage error. For the INA240, an additional error source (referred to as the reference voltage rejection ratio) is also included in the total error value. 8.4.4.2 Reference Voltage Rejection Ratio Error Reference voltage rejection ratio refers to the amount of error induced by applying a reference voltage to the INA240 that deviates from the mid-point of the device supply voltage. 8.4.4.2.1 Total Error Example 1 Table 8-2. Total Error Calculation: Example 1(1) TERM Initial input offset voltage SYMBOL EQUATION TYPICAL VALUE VOS — 5 µV 1 Added input offset voltage because of common-mode voltage VOS_CM Added input offset voltage because of reference voltage VOS_REF Total input offset voltage VOS_Total (VOS)2 + (VOS_CM)2 + (VOS_REF)2 5 µV Error from input offset voltage Error_VOS VOS_Total VSENSE ´ 100 0.05% Gain error Error_Gain — 0.05% Error_Lin — 0.01% — (Error_VOS)2 + (Error_Gain)2 + (Error_Lin)2 0.07% Total error (1) 20 ( Nonlinearity error 10 ( CMRR_dB ´ (VCM - 12V) RVRR × |VS / 2 – VREF| 0 µV 0 µV The data for Table 8-2 was taken with the INA240A4, VS = 5 V, VCM = 12 V, VREF1 = VREF2 = VS / 2, and VSENSE = 10 mV. 8.4.4.2.2 Total Error Example 2 Table 8-3. Total Error Calculation: Example 2(1) TERM Initial input offset voltage SYMBOL EQUATION TYPICAL VALUE VOS — 5 µV 1 Added input offset voltage because of common-mode voltage VOS_CM Added input offset voltage because of reference voltage VOS_REF Total input offset voltage VOS_Total (VOS)2 + (VOS_CM)2 + (VOS_REF)2 14 µV Error from input offset voltage Error_VOS VOS_Total VSENSE ´ 100 0.14% Gain error Error_Gain — 0.05% Error_Lin — 0.01% 16 20 ( Nonlinearity error 10 ( CMRR_dB ´ (VCM - 12V) RVRR × |VS / 2 – VREF| Submit Document Feedback 12.1 µV 5 µV Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 Table 8-3. Total Error Calculation: Example 2(1) (continued) TERM Total error (1) SYMBOL EQUATION TYPICAL VALUE — (Error_VOS)2 + (Error_Gain)2 + (Error_Lin)2 0.15% The data for Table 8-3 was taken with the INA240A4, VS = 5 V, VCM = 60 V, VREF1 = VREF2 = 0 V, and VSENSE = 10 mV. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 17 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The INA240 measures the voltage developed as current flows across the current-sensing resistor. The device provides reference pins to configure operation as either unidirectional or bidirectional output swing. When using the INA240 for inline motor current sense, the device is commonly configured for bidirectional operation. 9.1.1 Input Filtering Note Input filters are not required for accurate measurements using the INA240, and use of filters in this location is not recommended. If filter components are used on the input of the amplifier, follow the guidelines in this section to minimize the effects on performance. Based strictly on user design requirements, external filtering of the current signal may be desired. The initial location that can be considered for the filter is at the output of the current amplifier. Although placing the filter at the output satisfies the filtering requirements, this location changes the low output impedance measured by any circuitry connected to the output voltage pin. The other location for filter placement is at the current amplifier input pins. This location satisfies the filtering requirement also, however the components must be carefully selected to minimally impact device performance. Figure 9-1 shows a filter placed at the inputs pins. VS RS IN± t Bias R OUT + RS REF2 IN+ REF1 GND Figure 9-1. Filter at Input Pins External series resistance provide a source of additional measurement error, so keep the value of these series resistors to 10-Ω or less to reduce loss of accuracy. The internal bias network shown in Figure 9-1 creates a mismatch in input bias currents (see Figure 9-2) when a differential voltage is applied between the input pins. If additional external series filter resistors are added to the circuit, a mismatch is created in the voltage drop across the filter resistors. This voltage is a differential error voltage in the shunt resistor voltage. In addition to the absolute resistor value, mismatch resulting from resistor tolerance can significantly impact the error because this value is calculated based on the actual measured resistance. 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 250 IB+ Input Bias Current (PA) 200 150 100 IB50 0 -50 -100 0 0.2 0.4 0.6 Differential Input Voltage (V) 0.8 1 Figure 9-2. Input Bias Current vs Differential Input Voltage The measurement error expected from the additional external filter resistors can be calculated using Equation 1, where the gain error factor is calculated using Equation 2. Gain Error (%) = 100 - (100 ´ Gain Error Factor) (1) The gain error factor, shown in Equation 1, can be calculated to determine the gain error introduced by the additional external series resistance. Equation 1 calculates the deviation of the shunt voltage resulting from the attenuation and imbalance created by the added external filter resistance. Table 9-1 provides the gain error factor and gain error for several resistor values. Gain Error Factor 3000 RS 3000 (2) Where: • RS is the external filter resistance value Table 9-1. Gain Error Factor and Gain Error For External Input Resistors EXTERNAL RESISTANCE (Ω) GAIN ERROR FACTOR GAIN ERROR (%) 5 0.998 0.17 10 0.997 0.33 100 0.968 3.23 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 19 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 9.2 Typical Applications The INA240 offers advantages for multiple applications including the following: • High common-mode range and excellent CMRR enables direct inline sensing • Ultra-low offset and drift eliminates the necessity of calibration • Wide supply range enables a direct interface with most microprocessors Two specific applications are provided and include more detailed information. 9.2.1 Inline Motor Current-Sense Application 5V VS 40 V IN+ OUT INA240 REF2 REF1 IN± GND 100 PŸ Copyright © 2016, Texas Instruments Incorporated Figure 9-3. Inline Motor Application Circuit 9.2.1.1 Design Requirements Inline current sensing has many advantages in motor control, from torque ripple reduction to real-time motor health monitoring. However, the full-scale PWM voltage requirements for inline current measurements provide challenges to accurately measure the current. Switching frequencies in the 50-kHz to 100-kHz range create higher ΔV/Δt signal transitions that must be addressed to obtain accurate inline current measurements. With a superior common-mode rejection capability, high precision, and a high common-mode specification, the INA240 provides performance for a wide range of common-mode voltages. 9.2.1.2 Detailed Design Procedure For this application, the INA240 measures current in the drive circuitry of a 36-V, 4000-RPM motor. To demonstrate the performance of the device, the INA240A1 with a gain of 20 V/V was selected for this design and powered from a 5-V supply. Using the information in the Adjusting the Output Midpoint With the Reference Pins section, the reference point is set to midscale by splitting the supply with REF1 connected to ground and REF2 connected to supply. This configuration allows for bipolar current measurements. Alternatively, the reference pins can be tied together and driven with an external precision reference. The current-sensing resistor is sized so that the output of the INA240 is not saturated. A value of 100-mΩ was selected to maintain the analog input within the device limits. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 270 3.5 240 3 210 2.5 180 2 150 Input Signal INA240A1 Output Common-Mode Input Signal 120 1.5 1 90 0.5 60 0 30 -0.5 0 INA240A1 Output 9.2.1.3 Application Curve -1 -30 -1.5 Time (25 s/div) C005 Figure 9-4. Inline Motor Current-Sense Input and Output Signals Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 21 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 9.2.2 Solenoid Drive Current-Sense Application 12 V 5V Control IN+ VS OUT 10 m INA240 REF2 REF1 IN± GND Copyright © 2016, Texas Instruments Incorporated Figure 9-5. Solenoid Drive Application Circuit 9.2.2.1 Design Requirements Challenges exist in solenoid drive current sensing that are similar to those in motor inline current sensing. In certain topologies, the current-sensing amplifier is exposed to the full-scale PWM voltage between ground and supply. The INA240 is well suited for this type of application. 9.2.2.2 Detailed Design Procedure For this application, the INA240 measures current in the driver circuit of a 24-V, 500-mA water valve. To demonstrate the performance of the device, the INA240A4 with a gain of 200 V/V was selected for this design and powered from a 5-V supply. Using the information in the Adjusting the Output Midpoint With the Reference Pins section, the reference point is set to midscale by splitting the supply with REF1 connected to ground and REF2 connected to supply. Alternatively, the reference pins can be tied together and driven with an external precision reference. A value of 10 mΩ was selected to maintain the analog input within the device limits. 66 2 Y 60 2 2 54 1 1 48 1 6 5 4 3 42 2 36 Common-Mode Input Signal 1 INA240 Output 0 30 DDDDDDDDDDDDDINA240 Output Common-Mode Input SignalDDDDDDDDDDDDD 9.2.2.3 Application Curve 24 -1 18 -2 12 3.50 -3 3.50 -4 Y1 3 2.5 -5 2 1.5 -6 6 0 -6 Time (20 ms/div) D020 Figure 9-6. Solenoid Drive Current Sense Input and Output Signals 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 9.3 What to Do and What Not to Do 9.3.1 High-Precision Applications For high-precision applications, verify accuracy and stability of the amplifier by: • Providing a precision reference connected to REF1 and REF2 • Optimizing the layout of the power and sensing path of the sense resistor (see the Layout section) • Providing adequate bypass capacitance on the supply pin (see the Power Supply Decoupling section) 9.3.2 Kelvin Connection from the Current-Sense Resistor To provide accurate current measurements, verify the routing between the current-sense resistor and the amplifier uses a Kelvin connection. Use the information provided in Figure 9-7 and the Connection to the Current-Sense Resistor section during device layout. RSHUNT RSHUNT 1 2 3 4 1 2 3 4 INA240 INA240 8 7 6 5 8 7 6 5 DO Kelvin Connection from Shunt Resistor '21¶7 Non-Kelvin Connection from Shunt Resistor Copyright © 2016, Texas Instruments Incorporated Figure 9-7. Shunt Connections to the INA240 10 Power Supply Recommendations The INA240 series makes accurate measurements beyond the connected power-supply voltage (VS) because the inputs (IN+ and IN–) operate anywhere between –4 V and 80 V independent of VS. For example, the VS power supply equals 5 V and the common-mode voltage of the measured shunt can be as high as 80 V. Although the common-mode voltage of the input can be beyond the supply voltage, the output voltage range of the INA240 series is constrained to the supply voltage. 10.1 Power Supply Decoupling Place the power-supply bypass capacitor as close as possible to the supply and ground pins. TI recommends a bypass capacitor value of 0.1 μF. Additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 23 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 11 Layout 11.1 Layout Guidelines 11.1.1 Connection to the Current-Sense Resistor Poor routing of the current-sensing resistor can result in additional resistance between the input pins of the amplifier. Any additional high-current carrying impedance can cause significant measurement errors because the current resistor has a very-low-ohmic value. Use a Kelvin or 4-wire connection to connect to the device input pins. This connection technique ensures that only the current-sensing resistor impedance is detected between the input pins. 11.2 Layout Example RSHUNT Power Supply Load VIA to Ground Plane VIA to Ground Plane 4 3 2 1 GND IN± IN+ NC CBYPASS INA240 5 6 Supply Voltage REF1 OUT 8 REF2 7 VS Output Voltage VIA to Ground Plane Copyright © 2016, Texas Instruments Incorporated Figure 11-1. Recommended TSSOP Package Layout 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 Power Supply Load RSHUNT VIA to Ground Plane VIA to Ground Plane 1 IN- 2 GnD REF1 7 3 REF2 Vs 6 4 NC OUT 5 IN+ CBYPASS 8 VIA to Power Supply INA240 Figure 11-2. Recommended SOIC Package Layout Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 25 INA240 www.ti.com SBOS662C – JULY 2016 – REVISED DECEMBER 2021 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Texas Instruments, INA240EVM User's Guide • Texas Instruments, Motor Control Application Report • Texas Instruments, 48-V Three-Phase Inverter With Shunt-Based In-Line Motor Phase Current Sensing Reference Design 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: INA240 PACKAGE OPTION ADDENDUM www.ti.com 18-Nov-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) INA240A1D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A1 INA240A1DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A1 INA240A1PW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A1 INA240A1PWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A1 INA240A2D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A2 INA240A2DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A2 INA240A2PW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A2 INA240A2PWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A2 INA240A3D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A3 INA240A3DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A3 INA240A3PW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A3 INA240A3PWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A3 INA240A4D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A4 INA240A4DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A4 INA240A4PW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A4 INA240A4PWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 I240A4 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Nov-2021 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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