JFE150
SLPS732A – JUNE 2021 – REVISED NOVEMBER 2021
JFE150 Ultra-Low-Noise, Low-Gate-Current, Audio, N-Channel JFET
1 Features
•
•
•
•
•
•
Ultra-low noise:
– Voltage noise:
• 0.8 nV/√Hz at 1 kHz, IDS = 5 mA
• 0.9 nV/√Hz at 1 kHz, IDS = 2 mA
– Current noise: 1.8 fA/√Hz at 1 kHz
Low gate current: 10 pA (max)
Low input capacitance: 24 pF at VDS = 5 V
High gate-to-drain and gate-to-source breakdown
voltage: –40 V
High transconductance: 68 mS
Packages: Small SC70 and SOT-23 (Preview)
and yields excellent noise performance for currents
from 50 μA to 20 mA. When biased at 5 mA, the
device yields 0.8 nV/√Hz of input-referred noise,
giving ultra-low noise performance with extremely
high input impedance (> 1 TΩ). The JFE150 also
features integrated diodes connected to separate
clamp nodes to provide protection without the addition
of high leakage, nonlinear external diodes.
The JFE150 can withstand a high drain-to-source
voltage of 40-V, as well as gate-to-source and gateto-drain voltages down to –40 V. The temperature
range is specified from –40°C to +125°C. The device
is offered in 5-pin SOT-23 and SC-70 packages.
2 Applications
•
•
•
•
•
•
Device Information
Microphone inputs
Hydrophones and marine equipment
DJ controllers, mixers, and other DJ equipment
Professional audio mixer or control surface
Guitar amplifier and other music instrument
amplifier
Condition monitoring sensor
PART NUMBER
JFE150
(1)
PACKAGE(1)
BODY SIZE (NOM)
SOT-23 (5) - Preview 2.90 mm × 1.60 mm
SC-70 (5)
2.00 mm × 1.25 mm
For all available packages, see the package option
addendum at the end of the data sheet.
Device Summary
PARAMETER
3 Description
The JFE150 is a Burr-Brown™ discrete JFET built
using Texas Instruments' modern, high-performance,
analog bipolar process. The JFE150 features
performance not previously available in older discrete
JFET technologies. The JFE150 offers the maximum
possible noise-to-power efficiency and flexibility,
where the quiescent current can be set by the user
D
VALUE
VGSS
Gate-to-source voltage
–40 V
VDSS
Drain-to-source voltage
±40 V
CISS
Input capacitance
24 pF
TJ
Junction temperature
IDSS
Drain-to-source saturation current
–40°C to +125°C
36 mA
VCH
G
VCL
S
Functional Block Diagram
Ultra-Low Input Voltage Noise
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
JFE150
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SLPS732A – JUNE 2021 – REVISED NOVEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 6
7 Parameter Measurement Information............................ 8
7.1 AC Measurement Configurations................................8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................16
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Device Support....................................................... 17
12.2 Documentation Support.......................................... 18
12.3 Receiving Notification of Documentation Updates..18
12.4 Support Resources................................................. 18
12.5 Trademarks............................................................. 18
12.6 Electrostatic Discharge Caution..............................18
12.7 Glossary..................................................................18
13 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2021) to Revision A (November 2021)
Page
• Changed VGS minimum from –1.1 V to –1.3 V (100 µA), –0.9 V to –1.1 V (2 mA) ............................................5
• Changed Figure 6-3, Drain-to-Source Current vs Drain-to-Source Voltage, to show correct VGS values.......... 6
2
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5 Pin Configuration and Functions
VCH
1
VCL
2
G
3
5
D
4
S
Not to scale
Figure 5-1. DBV (5-Pin SOT-23, Preview) and DCK (5-Pin SC70) Packages, Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
D
5
G
S
TYPE
DESCRIPTION
Output
Drain
3
Input
Gate
4
Output
Source
VCH
1
Power
Positive diode clamp voltage
VCL
2
Power
Negative diode clamp voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VDS
Drain-to-source voltage
–40
40
V
VGS, VGD
Gate-to-source, gate-to-drain voltage
–40
0.9
V
VVCH
Voltage between VCH to D, G, or S
40
V
VVCL
Voltage between VCL to D, G, or S
IVCL, IVCH
Clamp diode current
IDS
Drain-to-source current
–50
IGS, IGD
Gate-to-source, gate-to-drain current
TA
Ambient temperature
TJ
Tstg
(1)
(2)
UNIT
–40
DC
20
50-ms pulse(2)
200
mA
50
mA
–20
20
mA
–55
150
°C
Junction temperature
–55
150
°C
Storage temperature
–55
175
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
Maximum diode current pulse specified for 50 ms at 1% duty cycle.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
Charged device model (CDM), per JEDEC specification JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MAX
UNIT
IDS
Drain-to-source current
0.02
MIN
NOM
IDSS
mA
VGS
Gate-to-source voltage
0
–1.2
V
TA
Specified temperature
–40
125
°C
6.4 Thermal Information
JFE150
THERMAL
METRIC(1)
DCK (SC70)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
197.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
93.7
°C/W
RθJB
Junction-to-board thermal resistance
44.8
°C/W
ψJT
Junction-to-top characterization parameter
16.7
°C/W
ψJB
Junction-to-board characterization parameter
44.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, IDS = 2 mA, and VDS = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE
IDS = 100 µA , VDS = 5 V
en
Input-referred voltage noise density
IDS = 2 mA, VDS = 5 V
IDS = 5 mA, VDS = 5 V
ei
f = 10 Hz
3
f = 1 kHz
2
f = 10 Hz
1.6
f = 1 kHz
0.9
f = 10 Hz
1.8
f = 1 kHz
nV/√Hz
0.8
IDS = 100 µA
0.19
IDS = 2 mA
0.09
IDS = 5 mA
0.13
Input-referred voltage noise
f = 0.1 Hz to 10 Hz,
VDS = 5 V
Input current noise
f = 1 kHz, VDS = 5 V
1.8
VDS = 2 V, VGS = –0.7 V, VVCH = 5 V, VVCL = –5 V
0.2
µVPP
fA/√Hz
INPUT CURRENT
IG
Input gate current
±10
0.2
VDS = 0 V, VGS = –30 V
TA = –40°C to +85°C
±2000
TA = –40°C to +125°C
±10000
pA
INPUT VOLTAGE
VGSS
Gate-to-source breakdown voltage
VDS = 0 V, |IG| < 100 µA
VGSC
Gate-to-source cutoff voltage
VDS = 10 V, IDS = 0.1 µA
−1.5
IDS = 100 µA
–1.3
–0.7
IDS = 2 mA
–1.1
–0.5
VGS
Gate-to-source voltage
−1.2
−40
V
−0.9
V
V
INPUT IMPEDANCE
RIN
Gate input resistance
VGS = –5 V to 0 V, VDS = 0 V
1
VDS = 0 V
30
VDS = 5 V
24
7
CISS
Input capacitance
CRSS
Reverse transfer capacitance
VDS = 0 V
IDSS
Drain-to-source saturation current
VDS = 10 V, VGS = 0 V
gm
Transconductance
GFS
Full conduction transconductance
VDS = 10 V, VGS = 0 V
55
VDSS
Drain-to-source breakdown voltage
|IDS| < 100 µA, VGS = –2 V
40
COSS
Output capacitance
VDS = 5 V
TΩ
pF
OUTPUT
24
TA = –40°C to +125°C
35
22
IDS = 100 µA
46
57
3
IDS = 2 mA
mS
18
68
mA
80
mS
V
8
pF
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6.6 Typical Characteristics
at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 5 V (unless otherwise noted)
6
Figure 6-1. Drain-to-Source Current vs Gate-to-Source Voltage
Figure 6-2. Drain-to-Source Current vs Drain-to-Source Voltage
Figure 6-3. Drain-to-Source Current vs Drain-to-Source Voltage
Figure 6-4. Common Source Transconductance vs Drain-toSource Current
Figure 6-5. Gate Current vs Drain-to-Source Voltage
Figure 6-6. Gate Current vs Gate-to-Source Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 5 V (unless otherwise noted)
VDS = 5 V
Figure 6-7. Gate-to-Source Voltage vs Temperature
Figure 6-8. IDSS vs Drain-to-Source Voltage
f = 1kHz
Figure 6-9. Input-Referred Noise Density vs Frequency
Figure 6-10. Noise Density Contributors
vs Input Gate Resistance
f = 1 kHz
Figure 6-11. Input-Referred Noise Spectral Density
vs Drain‑to‑Source Current
Figure 6-12. Input, Output, and Reverse Transfer Capacitance
vs Drain-to-Source Voltage
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7 Parameter Measurement Information
7.1 AC Measurement Configurations
The circuit configuration used for noise measurements is seen in Figure 7-1. The nominal IDS current is
configured in the schematic by calibrating V–. After IDS is fixed, the VDS voltage is set by calibrating V+. For
input-referred noise data, the gain of the circuit is calibrated from VIN to VOUT and used for the input-referred gain
calculation.
V+
10 k
RD
10 k
±
JFE150
+
VOUT
OPA210
F
RG
VIN
+
±
100 k
RS
10 k
3 mF
V±
Figure 7-1. AC Measurement Reference Schematic
8
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8 Detailed Description
8.1 Overview
The JFE150 is an ultra-low noise JFET designed to create low-noise gain stages for very high output impedance
sensors or microphones. Advanced processing technology gives the JFE150 extremely low-noise performance,
a high gm/CISS ratio, and ultra-low gate-current performance. Input protection diodes are integrated to clamp
high-voltage spurious input signals without the need for additional input diodes that can add leakage current
or distortion-creating non-linear capacitance. The JFE150 provides a next-generation device to implement lownoise amplifiers for piezoelectric sensors, transducers, large-area condenser microphones, and hydrophones in
small-package options.
8.2 Functional Block Diagram
D
VCH
G
S
VCL
8.3 Feature Description
8.3.1 Ultra-Low Noise
Junction-gate field-effect transistors (JFETs) are commonly used as an input stage in high-input-impedance,
low-noise designs in audio, SONAR, vibration analysis, and other technologies. The JFE150 is a new generation
JFET device that offers very low noise performance at the lowest possible current consumption in high-inputimpedance amplifier designs. The JFE150 is manufactured on a high-performance analog process technology,
giving tighter process parameter control than a standard JFET.
Designs that feature operational amplifiers (op amps) as the primary gain stage are common, but these designs
are not able to achieve the lowest possible noise as a result of the inherent challenges and tradeoffs required
from a full operational amplifier design. Noise in JFET designs can be evaluated in two separate regions:
low-frequency flicker noise and wideband thermal noise. Flicker, or 1/f noise, is extremely important for systems
that require signal gain at frequencies less that 100 Hz. The JFE150 achieves extremely low 1/f noise in
this range. Thermal noise is noise in the region greater than 1 kHz and depends on the gain, or gm, of the
circuit. The gm is a function of the drain-to-source bias current; therefore, thermal noise is also a function of
drain-to-source bias current. Figure 6-9 shows both 1/f and thermal noise with multiple bias conditions measured
using the circuit shown in Figure 7-1.
Noise is typically modeled as a voltage source (voltage noise) and current source (current noise) on the input.
The 1/f and thermal noise can be represented as voltage noise. Current noise is dominated by current flow into
the gate, and is called shot noise. The JFE150 features extremely low gate current, and therefore, extremely low
current noise. Figure 6-10 shows how source impedance on the input is the dominant noise source. In nearly all
cases, noise created as a result of current noise is negligible.
8.3.2 Low Gate Current
The JFE150 features a maximum gate current of 10 pA at room temperature, making the device an excellent
choice for maximizing the gain and dynamic range from extremely high impedance sensors. Additionally, any
noise contributions as a result of gate current are minimized because of the negligible shot noise at low current
levels. As with all JFET devices, when the drain-to-source voltage increases, the gate current also increases.
Keep the drain-to-source voltage to less than 5 V for the lowest gate input current operation.
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8.3.3 Input Protection
The JFE150 features input protection diodes that are used for surge clamping and ESD events. The diodes are
rated to withstand high current surges for short times, steering current from the gate (G) pin to the VCH and VCL
pins. The diodes also feature very low leakage, removing the need for external protection devices that may have
high leakage currents or nonlinear capacitance that degrade the distortion performance.
8.4 Device Functional Modes
The JFE150 functionality is identical to standard N-channel depletion JFET devices. The gate-to-source (VGS)
voltage, drain-to-source voltage (VDS) and drain-to-source current (IDS) determine the region of operation.
•
•
For VGS < VGSC: JFE150 conduction channel is closed; IDS is only determined by junction leakage current.
For VGS > VGSC: Two modes of operation can exist depending on VDS. When VDS is less than the linear
(saturation) region threshold (see Figure 8-1), the device operates in the linear region, meaning that the
device behaves as a resistor connected from drain-to-source with minimal variation from any changes in
VGS. When VDS is greater than the linear (saturation) region threshold, IDS has a strong dependance on VGS,
where the relationship is described by the parameter gm.
Linear Region
Saturation Region
Figure 8-1. VDS vs IDS
10
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Input Protection Diodes
The JFE150 features diodes that are used to help clamp voltage surges that can occur on the input sensor
to the gate. The diodes are connected between the gate and two separate pins, VCL and VCH. The clamping
mechanism works by steering current from the gate into the VCL or VCH nodes when the voltage at the gate
is less than VCL or greater than VCH. Figure 9-1 shows an example of a microphone input circuit where a dc
blocking capacitor operates with a large dc voltage. When the microphone input is dropped or shorted, the dc
blocking capacitor discharges into the VCL or VCH nodes, thus helping eliminate large signal transient voltages
on the gate. There are also clamping diodes from the drain and source to VCL and VCH, respectively. The
clamping diodes can withstand high surge currents up to 200 mA for 50 ms; however, limit dc current to less than
20 mA.
48 V
VCH
D
6.8 kŸ
CDC
10 …F
RG
G
JFE150
iG
RB
VCL
S
RL
Figure 9-1. JFE150 Clamping Diode Example
Figure 9-1 shows an example of configuring the diode clamp to protect the JFET against overvoltage in a
phantom-powered microphone circuit. Phantom power typically delivers 48 V through a 6.8-kΩ pullup resistor to
a microphone or dynamic load. If the microphone is disconnected, dc blocking capacitor CDC can be biased up to
48 V. If the input to the capacitor is then shorted to ground (shown by the switch in Figure 9-1), the gate voltage
can exceed the absolute maximum rating for VGS. In this case, the blocking diode is used, along with current
limiting resistors RG and RL, to clamp the gate voltage to a safe level. Be aware that the thermal noise of RG
couples directly into the gate input; therefore, make sure to minimize the resistance of RG.
The clamping diodes are not required for operation. The VGS voltage can withstand –40 V, so clamping is not
required if the VGS voltage is kept greater than this limit. If the diodes are not needed, leave the VCL and VCH
nodes floating.
Most previous-generation JFET devices featured only three pins (gate, source, and drain). For these devices,
the gate pin is in the same physical location as the VCL pin on the JFE150. To test the JFE150 in a three-pin
socket, short pin 2 of the JFE150 (VCL) to pin 3 (G). When the devices are connected with pin 2 shorted to pin 3,
the diode from VCL is shorted out and cannot provide any clamping protection. The input capacitance (CISS) also
increases by 1 pF; see Figure 6-12.
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9.1.2 Capacitive Transducer Input Stage
Piezoelectric transducers are used for many different applications that require low-noise, high-gain performance.
These transducers exhibit high output impedance (> 10 MΩ), and therefore require very high impedance loading
for subsequent input stages. The JFE150 has ultra-low input gate current (maximum IG = ±10 pA) and low
input capacitance (CISS = 24 pF), which makes the device an excellent choice for transducers with an effective
capacitance of greater than 240 pF. For smaller, lower-capacitance transducers, the CISS may impact the gain of
the front end by attenuating the input signal, thereby reducing the noise performance.
9.1.3 Common-Source Amplifier
The common-source amplifier is a commonly used open-loop gain stage for JFET amplifiers, the basic circuit is
shown in Figure 9-2.
V+
RD
JFE150
VOUT
RG
VIN
+
±
RS
Figure 9-2. Common-Source Amplifier
The equation for gain of the circuit in Figure 9-2 is shown in Equation 1.
VOUT
gm*RD
VIN = − 1 + gm*RS
(1)
Generally, higher gain results in improved noise performance. Gain increases as the bias current is increased
as a result of increasing gm (see Figure 6-4). As a result, the input-referred noise decreases as bias current
is increased (see Figure 6-9). Any JFET design must make a tradeoff between current consumption and
noise performance. The JFE150, however, delivers significantly lower noise performance than most operational
amplifiers at the same current consumption. The bias current (IDS) is set by the value of the source resistor, RS,
and the threshold voltage, VT, of the JFE150. A graph showing nominal IDS vs RS is shown in Figure 9-3.
Figure 9-3. Drain-to-Source Current vs RS, VDS = 5 V
12
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The bias current varies according to the resistor and threshold voltage tolerances. Additionally, thermal noise
associated with RS couples directly into the gain of the circuit, degrading the overall noise performance. To
improve the circuit in Figure 9-4, use a current-source biasing scheme. Current-source biasing removes the
JFET threshold variation from the biasing scheme, and allows for lower-value filtering capacitance (CS) for
equivalent filtering due to the high output impedance of current sources.
V+
RD
VOUT
JFE150
RG
VIN
+
±
CS
IBIAS
V±
Figure 9-4. Common-Source Amplifier With Current-Source Biasing
9.1.4 Composite Amplifiers
The JFE150 can be configured to provide a low-noise, high-input impedance front-end stage for a typical op
amp. Open-loop transistor gain stages shown previously suffer from wide gain variations that are dependent
on the forward transcondutance of the JFE150. When precision gain is required, the composite amplifier (JFET
front-end + operational amplifier) achieves excellent results by allowing for a fixed gain determined by external
resistors, and improving the noise and bandwidth of the operational amplifier. The JFE150 gain stage provides
a boost to the open-loop performance of the system, extending the bandwidth beyond what the operational
amplifier alone can provide, and gives a high-input impedance, ultra-low noise input stage to interface with high
source impedance microphones.
Figure 9-5 shows a generic schematic representation of a current-feedback composite amplifier. The component
requirements and tradeoffs are listed in Table 9-1.
CF
VDD
RD
CD
JFE150
CB
VIN
+
±
VBIASO
RG
RB
±
OPA
+
VOUT
RS2
RS
CS
Figure 9-5. Low Noise, High Input Impedance Composite Amplifier
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Table 9-1. Composite Amplifier Component List and Function
COMPONENT
DESCRIPTION
RELATED EQUATION
CB
DC blocking capacitor for input source. Use a dc blocking capacitor
if the dc voltage of the input source is not the same as the gate bias
voltage.
RB
Bias resistor. Use biasing resistors to set the dc voltage at the
gate. High-value resistors can be used without an impact to noise
if the source impedance and bypass capacitor have sufficiently low
impedance.
RG
Gate resistor. Can be used to help limit current flow into gate in
overvoltage cases.
RD
Drain resistor. Sets gain of JFET stage in common source biasing,
along with gm and RS.
RS
Source resistor. Used to set bias of JFET; see Figure 9-3. Resistor
thermal noise directly impacts noise performance.
CD
DC blocking capacitor. Blocks nominal drain voltage so the amplifier
operates at a midsupply bias point.
CF
Feedback capacitor. Along with RF, this capacitor sets the –3‑dB
high-pass cutoff frequency when the amplifier gain-bandwidth product
(GBW) is sufficiently high enough to support the –3‑dB frequency.
If the GBW is not high enough, then the GBW sets the –3-dB
frequency.
RF
Feedback resistor. Along with CF, this resistor sets the –3‑dB highpass cutoff frequency when the amplifier gain-bandwidth product
(GBW) is sufficiently high enough to support the –3‑dB frequency.
If the GBW is not high enough, then the GBW sets the –3-dB
frequency.
RF2
Current feedback gain-setting resistor 1. Along with RS2, sets gain
closed-loop.
RS2
Current feedback gain-setting resistor 2. Along with RS2, sets
gain closed-loop. Resistor thermal noise directly impacts noise
performance.
CS
Current feedback ac-coupling capacitor. This capacitor, along with R2,
sets the low-pass –3-dB frequency.
f–3dBDC =
1
2* π*RB1 RB2*CB1
(2)
See Equation 2
f–3dBHP = 2*π*R1 *C
F F
(3)
See Equation 3
V
R
VOUT = RF2
IN
S2
(4)
See Equation 4
f–3dBLP = 2*π*R1 *C
S2 S
(5)
9.2 Typical Application
The JFE150 can be configured to provide a low-noise, high-input-impedance front-end stage for a typical op
amp. Single-transistor gain stages shown previously suffer from wide gain variations dependent on the forward
transcondutance of the JFE150. When precision gain is required, the composite amplifier (JFET front-end +
operational amplifier) achieves excellent results.
CF
10 pF
12 V
RD
10 k
CD
F
±
JFE 150
CB
F
6V
RG
VOUT
+
OPA 202
+
VIN
±
RB
1M
RS2
RS
CS
F
Figure 9-6. Low-Noise, High-Input-Impedance Composite Amplifier
14
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9.2.1 Design Requirements
PARAMETER
DESIGN GOAL
Gain
60 dB
Frequency response
60 Hz to 20 kHz
Noise
< 1.5 nV/√Hz
Input current
< 100 pA
Output swing
±5 V
9.2.2 Detailed Design Procedure
This design provides 60 dB of gain with extremely high input impedance at a very low frequency response. The
order of design priorities are as follows:
•
•
•
•
The JFE150 bias current is set by selecting the desired bias current and noise tradeoff (see Figure 6-11). The
input-referred noise is dominated by the JFE150 bias current and gain. To set the bias current point, adjust
the source resistance according to Figure 9-3.
After the bias current is selected, set the JFET stage gain as high as possible without pushing the device
into the linear region of operation. This is achieved by using the largest drain resistor (RD) possible while
maintaining a minimum of 2 V across the drain to source nodes. Be aware that the amplifier forces the drain
node to match the noninverting amplifier input in normal closed-loop operation. Both ac and dc voltages must
be considered, but generally, only the dc operating point on the drain is considered because the ac voltage
swing is minimal.
Set the closed gain according to RF2 and RS2, as seen in Equation 4. Thermal noise from RS2 directly couples
into the circuit; therefore, small values for this resistor are required.
CS is required to block dc voltages from altering the bias point set by source resistor RS. CS also forms the
low-frequency response as described in Equation 5.
9.2.3 Application Curves
Figure 9-7. Voltage Gain
Figure 9-8. Input-Referred Noise Density
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10 Power Supply Recommendations
The JFE150 is a JFET transistor with clamping diodes. There are no specific power-supply connections;
however, take care not to exceed any absolute maximum voltages on any of the pins if system supply voltages
greater than or equal to 40 V are used.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
•
•
•
•
•
•
•
•
•
Reduce parasitic coupling by running the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Keep high impedance input signals away from noisy traces.
Make sure supply voltages are adequately filtered.
Minimize distance between source-connected and drain-connected components to the JFE150.
Consider a driven, low-impedance guard ring around the critical gate traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
Clean the PCB following board assembly for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
VDD
RD
VDD
VSS
VCH D
VCL
G
VSS
S
RS
VIN
CS
Figure 11-1. JFE150 Layout Example, Common Source Configuration
16
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
12.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully functional version of the TINA software, preloaded with a library of macro
models, in addition to a range of both passive and active models. TINA-TI software provides all the conventional
dc, transient, and frequency domain analyses of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
12.1.1.3 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials,
and measured performance of many useful circuits. TI Precision Designs are available online at http://
www.ti.com/ww/en/analog/precision-designs/.
12.1.1.4 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer allows the user to create optimized filter designs using a selection of TI operational amplifiers and
passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
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12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx202 Precision, Low-Noise, Heavy Capacitive Drive, 36-V Operational Amplifiers
data sheet
• Texas Instruments, OPAx210 2.2-nV/√Hz Precision, Low-Power, 36-V Operational Amplifiers data sheet
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
Burr-Brown™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
JFE150DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
1IF
JFE150DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
1IF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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