LM25085MYEVAL

User's Guide SNVA375B – October 2008 – Revised April 2013 AN-1905 LM25085 Evaluation Board 1 Introduction The LM25085EVAL evaluation board provides the design engineer with a fully functional buck regulator, employing the LM25085 PFET switching controller that uses the constant on-time (COT) operating principle. This evaluation board provides a 5 V output over an input range of 5.5 V to 42 V. The circuit delivers load currents to 5A, with current limit set at ≊8.2A. The board is populated with all components except C5. Its use is described later in this document. The board’s specification are: • Input Voltage: 5.5 V to 42 V • Output Voltage: 5 V • Maximum load current: 5A for VIN >9 V • Minimum load current: 0A • Current Limit Threshold: ≊8.2A • Measured Efficiency: 97.2% (VIN = 5.5 V, IOUT = 0.6Amps) • Nominal Switching Frequency: 300 kHz • Size: 3.1 in. x 1.5 in. x 0.78 in Figure 1. Evaluation Board - Top Side All trademarks are the property of their respective owners. SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1905 LM25085 Evaluation Board 1 Theory of Operation 2 www.ti.com Theory of Operation The evaluation board schematic is shown in Figure 7. When the circuit is in regulation, the on-time at the PGATE output pin is determined by R4 and the voltage at VIN according to Equation 1: -7 tON = 1.45 x 10 x (R4 + 1.4) + 50 ns VIN ± 1.56V + R4/3167 (1) where, R4 is in kΩs. The on-time at the SW node (junction of Q1, L1 and D1) is longer than the above calculated on-time due to the difference of the turn-on and turn-off delay of Q1. The data sheet for the Si7465 PFET indicates a typical turn-on delay of 8 ns, and a typical turn-off delay of 65 ns, resulting in an additional 57 ns at the SW node. The SW on-time of this evaluation board ranges from ≊3479 ns at VIN = 5.5 V, to ≊438 ns at VIN = 42 V. The on-time varies inversely with VIN to maintain a nearly constant switching frequency. During the off-time, the load current is supplied by the inductor and the output capacitor (C6, C7). When the output voltage falls sufficiently that the voltage at FB is below the reference voltage (1.25 V), the regulation comparator initiates a new on-time period. For stable, fixed frequency operation, a minimum of 25 mV of ripple is required at the FB pin to switch the regulation comparator. The required ripple is generated by R7 and C10, and supplied to the FB pin via C9. The current limit threshold is set by the sense resistor (R5), and R3 at the ADJ pin, and is ≊8.2A on this board. A current sink at the ADJ pin sets a constant voltage across R3. When the voltage across R5 exceeds the voltage across R3 the current limit comparator switches to shut off Q1, and the LM25085 forces a longer-than-normal off-time. The long off-time is a function of the input voltage (VIN) and the voltage at the FB pin, and is necessary to allow the inductor current to decrease at least as much, if not more, than the current increase that occurred during the on-time. The circuit may be shutdown at any time by grounding the Enable test point (EN, TP1). Removing the ground connection allows normal operation to resume. For a detailed block diagram, and a complete description of the various functional blocks, see the LM25085 42V Constant On-Time PFET Buck Switching Controller Data Sheet (SNVS593). 3 Board Layout and Probing Figure 1 shows the placement of the circuit components. The following should be kept in mind when the board is powered: 1) When operating at high input voltage and continuous conduction mode forced air flow is necessary to prevent overheating of the LM25085 controller. 2) When operating at high load current forced air flow may be necessary to prevent overheating of Q1, D1, and L1. These components may be hot to the touch. 3) Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible damage to the circuit. 4) At maximum load current (5A), the wire size and length used to connect the source voltage, and the load, becomes important. Ensure there is not a significant drop in the wires supplying the input current and the load current. 4 Board Connection/Start-up The input connections are made to the J1 (+) and J2 (-) connectors. The load is connected to the J3 (VOUT) and J4 (GND) terminals. Ensure the wires are adequately sized for the intended load current. Before start-up a voltmeter should be connected to the input terminals, and one to the output terminals. The load current should be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased gradually to 4.5 V, at which time the output voltage should be slightly less than 4.5 V, depending on the load current. The output is regulated at 5 V when the input voltage is increased above 5 V. If the output voltage is correct, then increase the input voltage as desired and proceed with evaluating the circuit. DO NOT EXCEED 45 V AT VIN. 2 AN-1905 LM25085 Evaluation Board SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Load Current Derating www.ti.com 5 Load Current Derating Although the maximum load current for this evaluation board is specified as 5A, the data sheet for the Si7465 PFET specifies a maximum continuous current of 3.2A. Since the input current, which is the average current though Q1, increases as the input voltage is decreased, the load current must be derated at low input voltage, see Figure 2. Figure 2. Maximum Load Current Derating 6 Operating at Low Voltage When the input voltage is less than 5 V, the PFET (Q1) is on continuously (100% duty cycle) and the output voltage is equal to the input voltage, minus voltage drops across the sense resistor, Q1, and the inductor. As the input voltage is increased above 5V switching commences at the PGATE pin and the SW node as the LM25085 regulates the output at 5 V. Since the LM25085 does not have a required minimum off-time, the circuit transitions smoothly from 100% duty cycle to a regulated output. 7 Current Limit The LM25085 peak current limit detection operates by sensing the voltage across either the RDS(ON) of Q1, or a sense resistor (R5), during the on-time and comparing it to the voltage across R3 at the ADJ pin. The current limit threshold is reached when the sensed voltage exceeds the voltage across R3. When current limit is reached Q1 is immediately switched off. The current limit function is much more accurate and stable over temperature when a sense resistor is used. The RDS(ON) of a MOSFET has a wide process variation and a large temperature coefficient. Current sensing is disabled for a blanking time of ≊100 ns at the beginning of each on-time to prevent false triggering of the current limit comparator due to leading edge current spikes. After Q1 is turned off due to current limit detection, Q1 is held off for a longer-than-normal off-time. The extended off-time is a function of the input voltage and the voltage at the FB pin, as shown in Figure 3. The current limit off-time can be calculated from Equation 2: -6 tOFF(CL) = 4 x 10 x ((VIN/31) + 0.15) (VFB x 0.93) + 0.28V (2) The longer-than-normal forced off-time allows the inductor current to decrease to a low level before the next on-time. This cycle-by-cycle monitoring, followed by a long forced off-time, provides effective protection from output load faults over a wide range of operating conditions. SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1905 LM25085 Evaluation Board 3 Current Limit www.ti.com Figure 3. Current Limit Off-time vs. VIN and VFB 7.1 Sense Resistor Method This evaluation board is supplied configured for the sense resistor method of current limit detection. Jumpers A-B are in place at both jumper locations (JP1, JP2), which connects the ADJ pin resistor (R3) and the ISEN pin across the sense resistor (R5). If the voltage across R5 exceeds the voltage across R3 during the on-time, the current limit comparator switches to turn off Q1. The voltage across R3 is set by an internal 40 µA current sink at the ADJ pin. The current at which the current limit comparator switches is calculated from: ICL = 40 µA x R3/R5 (3) With R5 = 10 mΩ and R3 = 2.05 kΩ, the nominal current limit threshold calculates to 8.2A. Since that is the peak of the inductor current waveform, the load current is equal to that peak value minus one half the ripple current amplitude. At VIN = 5.5 V, the ripple amplitude is ≊116 mAp-p, and the load current at current limit is equal to 8.14 A. At VIN = 42 V, the ripple amplitude is ≊1080 mAp-p, and the load current at current limit is equal to ≊7.66A. Using the tolerances for the ADJ pin current and the current limit comparator offset, the maximum current limit threshold calculates to: ICL(max) = (2.05 k: x 48 PA) + 9 mV 0.01: = 10.74A (4) and, the load current at current limit calculates to 10.7A at 5.5 V, and 10.2A at 42 V. The minimum current limit thresholds calculate to: ICL(min) = (2.05 k: x 32 PA) - 9 mV 0.01: = 5.66A (5) and, the load current at current limit calculates to 5.6A at 5.5 V, and 5.12A at 42 V. To change the current limit threshold the value for R5 should be chosen to achieve 50 mV to 100 mV across it at current limit, staying within the practical limitations of power dissipation and physical size of the resistor. A larger value for R5 reduces the effects of the current limit comparator offset, but at the expense of higher power dissipation. After selecting the value for R5, calculate the value for R3 by rearranging Equation 3. For a procedure to account for ripple current amplitude and tolerances when selecting the resistor for the ADJ pin, see the Applications Information section of the LM25085 42V Constant On-Time PFET Buck Switching Controller Data Sheet (SNVS593). 4 AN-1905 LM25085 Evaluation Board SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Output Ripple Control www.ti.com 7.2 Q1 RDS(ON) Method To configure the evaluation board to use the RDS(ON) of Q1 for current limit detection, move the jumpers at both JP1 and JP2 from the A-B position to the B-C position. This change connects the ADJ pin resistor (R3) and the ISEN pin across Q1. Since the sense resistance is now the RDS(ON) of Q1, R3 must be changed. The data sheet for the Si7465 PFET lists the typical RDS(ON) as 51 mΩ at VGS = 10 V, and 64 mΩ at VGS = 4.5 V. Therefore, the RDS(ON) is estimated to be nominally 57 mΩ at VGS = 7.7 V. To achieve the same nominal current limit threshold as above (8.2A), using Equation 6 in the data sheet R3 calculates to: R3 = 8.2A x 0.057: 40 PA = 11.7 k: (6) The load current is equal to the current limit threshold minus half the current ripple amplitude. R3 can be changed to set other current limit detection thresholds. 8 Output Ripple Control The LM25085 requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform at the SW node, for proper operation. On this evaluation board, the required ripple is generated by R7, C9, and C10, allowing the ripple at VOUT to be kept to a minimum, as described in Section 8.1. Alternatively, the required ripple at the FB pin can be supplied from ripple generated at VOUT and passed through the feedback resistors, as described in Section 8.2 and Section 8.3, using one or two less external components. 8.1 Minimum Output Ripple This evaluation board is supplied configured for minimum ripple at VOUT by using components R7, C9 and C10. The ripple voltage required by the FB pin is generated by R7 and C10 since the SW node switches from ≊-1 V to VIN, and the right end of C10 is a virtual ground. The values for R7 and C10 are chosen to generate a 25-40 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through C9. The following procedure is used to calculate values for R7, C9 and C10: 1) Calculate the voltage VA: VA = VOUT - (VSW x (1 - (VOUT/VIN(min)))) (7) where, VSW is the absolute value of the voltage at the SW node during the off-time, typically 0.5 V to 1 V depending on the diode, and VIN is the minimum input voltage. Using a typical value of 0.65 V for VSW, VA calculates to 4.94 V. This is the approximate DC voltage at the R7/C10 junction, and is used in Equation 8. 2) Calculate the R7xC10 product: R7 x C10 = (VIN - VA) x tON 'V (8) where, tON is the maximum on-time (≊3479 ns), VIN is the minimum input voltage, and ΔV is the desired ripple amplitude at the R7/C10 junction, 25 mVp-p for this example. R7 x C10 = (5.5V ± 4.94V) x 3479 ns 0.025V = 7.79 x 10 -5 (9) R7 and C10 are then chosen from standard value components to satisfy the above product. On this evaluation board, C10 is set at 3300 pF. R7 calculate to be 23.6 kΩ, and a standard value 23.2 kΩ resistor is used. C9 is chosen to be 0.01 µF, large compared to C10. The circuit as supplied on this EVB is shown in Figure 4. The output ripple that ranges from ≊10 mVp-p at VIN = 5.5 V to ≊28 mVp-p at VIN = 42 V, is determined primarily by the ESR of the output capacitance (C6, C7), and the inductor’s ripple current that ranges from 116 mAp-p to 1080 mAp-p over the input voltage range, see Figure 11. SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1905 LM25085 Evaluation Board 5 Output Ripple Control www.ti.com LM25085 PGATE Q1 L1 15 PH Pads for wire loop VOUT 5V D1 GND FB C9 0.01 PF R6 0: R1 10k C10 3300 pF R7 23.2k C6 47 PF R2 3.4k C7 47 PF GND Figure 4. Minimum Ripple Using R7, C9, C10 8.2 Reduced Ripple Level Configuration This configuration generates more ripple at VOUT than the above configuration, but uses one less capacitor. If some ripple is acceptable in the application, this configuration is slightly more economical, and simpler. R6 and C5 are used instead of R7, C9 and C10, as shown in Figure 5. Ripple is generated at VOUT as the inductor’s ripple current flows through R6, and that ripple voltage is passed to the FB pin via C5. The ripple at VOUT can be set as low as 25 mVp-p since it is not attenuated by R1 and R2. The minimum value for R6 is calculated from Equation 10: (10) where, IOR(min) is the minimum inductor’s ripple current that occurs at minimum input voltage, and is 116 mAp-p at 5.5 V. The minimum value for R6 calculates to 0.22 Ωs. Using a standard value 0.27 Ω resistor for R6, the ripple at VOUT ranges from 31 mVp-p to 292 mVp-p over the input voltage range, see Figure 11. The minimum value for C5 is determined from Equation 11: (11) where, tON(max) is the maximum on-time, 3479 ns in this evaluation board. The minimum value for C5 calculates to 4113 pF. LM25085 PGATE Q1 L1 15 PH Pads for wire loop VOUT 5V D1 GND C5 4700 pF R6 0.27: R1 10k FB C6 47 PF R2 3.4k C7 47 PF GND Figure 5. Reduced Ripple Configuration 6 AN-1905 LM25085 Evaluation Board SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Monitor The Inductor Current www.ti.com 8.3 Lowest Cost Configuration This configuration is the same as Section 8.2, but with C5 removed. The ripple at the FB pin is attenuated from that at VOUT by the feedback resistors (R1, R2). Since ≥25 mVp-p are required at the FB pin, R6 is chosen to generate ≥100 mV at VOUT. Since the minimum ripple current in this circuit is 116 mAp-p the minimum value for R6 calculates to 0.86 Ωs. Using a standard value 1.0 Ωs resistor for R6, the ripple at VOUT ranges from ≊116 mVp-p to ≊1080 mVp-p over the input voltage range, see Figure 11. If the application can accept this ripple level, this is the most economical solution. The circuit is shown in Figure 6. LM25085 PGATE Q1 L1 15 PH Pads for wire loop VOUT 5V D1 GND R6 1: R1 10k FB R2 3.4k C6 47 PF C7 47 PF GND Figure 6. Lowest Cost Configuration 9 Monitor The Inductor Current The inductor’s current can be monitored or viewed on a scope with a current probe. Remove the jumper from the WIRE LOOP pads, and install an appropriate current loop across the pads. In this way, the inductor’s ripple current and peak current can be accurately determined. 10 Scope Probe Adapters Scope probe adapters are provided on this evaluation board for monitoring the waveform at the SW node, and at the circuit’s output (VOUT), without using the probe’s ground lead, which can pick up noise from the switching waveforms. The probe adapters are suitable for Tektronix P6137 or similar probes, with a 0.135” diameter. SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1905 LM25085 Evaluation Board 7 Scope Probe Adapters www.ti.com 5.5V to 42V Input C3 0.47 PF VCC VIN VIN C1 6.8 PF GND C8 C2 0.1 PF 4.7 PF R4 90.9k 1000 pF ADJ JP1 A B C R5 10 m: R3 2.05k ISEN RT ENABLE C4 LM25085 PGATE JP2 B A C Q1 TP1 Pads for wire loop L1 15 PH VOUT 5V SW D1 GND FB C10 3300 pF R7 23.2k R6 0: R1 10k VOUT C9 0.01 PF R2 3.4k C6 47 PF C7 47 PF GND Figure 7. Complete Evaluation Board Schematic Table 1. Bill of Materials (BOM) 8 Item Description Mfg Part Number Package Value C1 Ceramic Capacitor United Chemicon KTS101B685M55N0T00 2220 6.8 µF, 100 V C2 Ceramic Capacitor United Chemicon KTS101B475M43N0T00 1812 4.7 µF, 100 V C3 Ceramic Capacitor TDK C2012X7R1C474K 0805 0.47 µF, 16 V C4 Ceramic Capacitor TDK C2012X7R2A102K 0805 1000 pF, 100 V C5 Ceramic Capacitor Unpopulated 0805 C6, C7 Ceramic Capacitor TDK C3225X5R0J476M 1210 47 µF, 6.3 V C8 Ceramic Capacitor TDK C2012X7R2A104K 0805 0.1 µF, 100 V C9 Ceramic Capacitor TDK C2012X7R2A103K 0805 0.01 µF, 100 V C10 Ceramic Capacitor TKD C2012X7R2A332K 0805 3300 pF, 100 V D1 Schottky Diode On Semi MBRB2060CT D2PAK 60 V, 20A L1 Power Inductor Wurth XXL 7447709150 12 mm x 12 mm x 10 mm 15 µH Q1 P-Channel MOSFET Vishay Si7465DP SO-8 Power 60 V, 5A R1 Resistor Vishay CRCW08051002F 0805 10k R2 Resistor Vishay CRCW08053401F 0805 3.4k R3 Resistor Vishay CRCW08052051F 0805 2.05k R4 Resistor Vishay CRCW08059092F 0805 90.9k R5 Resistor Vishay WSL2010R0100F 2010 0.01 Ω, R6 Resistor Vishay CRCW08050000Z 0805 0 Ωs R7 Resistor Vishay CRCW08052322F 0805 23.2k U1 Switching Regulator LM25085 VSSOP8-EP AN-1905 LM25085 Evaluation Board SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Circuit Performance www.ti.com 11 Circuit Performance 100 100 VIN = 5.5V 6V 90 12V EFFICIENCY (%) EFFICIENCY (%) 90 24V 80 42V 3A 5A 1A 80 IOUT = 0.2A 70 70 VOUT = 5V FS = 300 kHz VOUT = 5V FS = 300 kHz 60 60 0 1 2 3 4 5 0 10 20 30 40 VIN (V) LOAD CURRENT (A) Figure 8. Efficiency vs Load Current Figure 9. Efficiency vs Input Voltage Figure 10. Switching Frequency vs. Input Voltage Figure 11. Output Voltage Ripple SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1905 LM25085 Evaluation Board 9 Circuit Performance www.ti.com Figure 12. Line Regulation 10 AN-1905 LM25085 Evaluation Board Figure 13. Load Regulation SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Typical Waveforms www.ti.com 12 Typical Waveforms Trace 4 = Inductor Current Trace 3 = VOUT Trace 1 = SW Node VIN = 42 V, IOUT = 1Amp Minimum Ripple Configuration (Option A) Figure 14. Continuous Conduction Mode Trace 4 = Inductor Current Trace 3 = VOUT Trace 1 = SW Node VIN = 42 V, IOUT = 0 Figure 15. Discontinuous Conduction Mode SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1905 LM25085 Evaluation Board 11 Typical Waveforms www.ti.com Trace 4 = Inductor Current Trace 3 = VOUT Trace 1 = SW Node VIN = 42 V, IOUT = 0 Figure 16. Discontinuous Conduction Mode (Expanded Scale) 12 AN-1905 LM25085 Evaluation Board SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated PC Board Layout www.ti.com 13 PC Board Layout Figure 17. Board Silkscreen Figure 18. Board Top Layer SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1905 LM25085 Evaluation Board 13 PC Board Layout www.ti.com Figure 19. Board Bottom Layer (Viewed from Top) 14 AN-1905 LM25085 Evaluation Board SNVA375B – October 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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