LM2724ALD/NOPB

LM2724A www.ti.com SNVS242C – JUNE 2003 – REVISED MARCH 2013 LM2724A High Speed 3A Synchronous MOSFET Driver Check for Samples: LM2724A FEATURES DESCRIPTION • • • • • • The LM2724A is a dual N-channel MOSFET driver which can drive both the top and bottom MOSFETs in a push-pull structure simultaneously. The LM2724A takes a logic input and splits it into two complimentary signals with a typical 20ns dead time in between. The built-in cross-conduction protection circuitry prevents the top and bottom MOSFETs from turning on simultaneously. With a bias voltage of 5V, the peak sourcing and sinking current for each driver of the LM2724A is about 3A. Input UVLO (Under-VoltageLock-Out) ensures that all the driver outputs stay low until the supply rail exceeds the power-on threshold during system power on, or after the supply rail drops below power-on threshold by a specified hysteresis during system power down. The cross-conduction protection circuitry detects both driver outputs and will not turn on a driver until the other driver output is low. The top gate voltage needed by the top MOSFET is obtained through an external boot-strap structure. When not switching, the LM2724A only draws up to 195µA from the 5V rail. The synchronization operation of the bottom MOSFET can be disabled by pulling the SYNC pin to ground. 1 2 Shoot-Through Protection Input Under-Voltage-Lock-Out 3A Peak Driving Current 195µA Quiescent Current 28V Input Voltage in Buck Configuration SOIC-8 and WSON Packages APPLICATIONS • • • • High Current DC/DC Power Supplies High Input Voltage Switching Regulators Fast Transient Microprocessors Notebook Computers TYPICAL APPLICATION VIN (up to 28V) D1 1.5 C2 + Q1 6 (to controller) 5 (to controller) 4 8 VCC SYNC IN GND C3 .33PF U1 C1 1PF BOOT LM2724A +5V HG SW LG 3 L1 2 VOUT 1 7 Q2 + C4 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated LM2724A SNVS242C – JUNE 2003 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM 1 8 GND HG 2 7 LG BOOT 3 6 VCC IN 4 5 SYNC Figure 1. 8-Lead SOIC See Package Number D SW 1 8 GND HG 2 7 LG BOOT 3 6 VCC IN 4 5 SYNC GROUND SW Figure 2. 8-Lead WSON See Package Number NGN PIN DESCRIPTIONS Pin Name 1 SW Top driver return. Should be connected to the common node of top and bottom FETs Function 2 HG Top gate drive output. Should be connected to the top FET gate. 3 BOOT 4 IN Bootstrap. Accepts a bootstrap voltage for powering the high-side driver 5 SYNC 6 VCC Connect to +5V supply 7 LG Bottom gate drive output. Should be connected to the bottom FET gate. 8 GND Accepts a logic control signal Bottom gate enable Ground BLOCK DIAGRAM +5V VIN BOOT HG VCC Power On Reset Q1 SW VOUT + SYNC Q2 Logic IN LG Shoot-through Protection 2 GND Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2724A LM2724A www.ti.com SNVS242C – JUNE 2003 – REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) VALUE / UNITS VCC 7V BOOT to SW 7V BOOT to GND (3) 35V SW to GND (4) -2V to 30V Junction Temperature +150°C 720mW (SOIC-8) 3.2W (WSON-8) Power Dissipation (5) −65°C to 150°C Storage Temperature ESD Susceptibility Human Body Model (6) Soldering Time, Temperature (1) (2) (3) (4) (5) (6) 2.0 kV 10sec., 300°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates correctly. The ensured specifications apply only for the listed test conditions. Some performance characteristics may degrade when the part is not operated under listed conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. If BOOT voltage exceeds this value, the ESD structure will degrade. The SW pin can have -2V to -0.5V applied for a maximum duty cycle of 10% with a maximum period of 1 second. There is no duty cycle or maximum period limitation for a SW pin voltage range of -0.5V to 30V. Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PMAX = (TJMAX-TA) / θJA. The junction-to-ambient thermal resistance, θJA, for LM2724A is 172°C/W. For a TJMAX of 150°C and TA of 25°C, the maximum allowable power dissipation is 0.7W. The θJA, for LM2724A WSON package is 39°C/W. For a TJMAX of 150°C and TA of 25°C, the maximum allowable power dissipation is 3.2W. ESD machine model susceptibility is 200V. RECOMMENDED OPERATING CONDITIONS (1) VALUE / UNITS VCC 4.3V to 6.8V Junction Temperature Range (1) -40°C to 125°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates correctly. The ensured specifications apply only for the listed test conditions. Some performance characteristics may degrade when the part is not operated under listed conditions. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2724A 3 LM2724A SNVS242C – JUNE 2003 – REVISED MARCH 2013 www.ti.com Electrical Characteristics — LM2724A VCC = BOOT = SYNC = 5V, SW = GND = 0V, unless otherwise specified. Tyicals and limits appearing in plain type apply for TA = TJ = +25°C. Limits appearing in boldface type apply over the entire operating temperature range. Symbol Parameter Condition Min Typ Max Units IN = 0V 145 195 µA 3.0 A IBOOT = IHG = 0.3A 1.2 Ω POWER SUPPLY Iq_op Operating Quiescent Current TOP DRIVER Peak Pull-Up Current Pull-Up Rds_on −3.2 A Pull-down Rds_on ISW = IHG = 0.3A 0.5 Ω t4 Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns t6 Fall Time 12 ns t3 Pull-Up Dead Time Timing Diagram 19 ns t5 Pull-Down Delay Timing Diagram, from IN Falling Edge 27 ns Peak Pull-down Current BOTTOM DRIVER Peak Pull-Up Current Pull-up Rds_on IVCC = ILG = 0.3A Peak Pull-down Current 3.2 A 1.1 Ω 3.2 A Pull-down Rds_on IGND = ILG = 0.3A 0.6 Ω t8 Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns t2 Fall Time 14 ns t7 Pull-up Dead Time Timing Diagram 22 ns t1 Pull-down Delay Timing Diagram 13 ns Vuvlo_up VCC Under-Voltage-Lock-Out Upper Threshold VCC rises from 0V toward 5V Vuvlo_dn VCC Under-Voltage-Lock-Out Lower Threshold VCC falls from 5V toward 0V Vuvlo_hys VCC Under-Voltage-Lock-Out Hysteresis VCC falls from 5V toward 0V VIH_SYNC SYNC Pin High Input VIL_SYNC SYNC Pin Low Input LOGIC SYNC = 5V, Sink Current 2 SYNC = 0V, Source Current 10 IN = 0V, Source Current 2 IN = 5V, Sink Current 10 ton_min1 Minimum Positive Pulse Width at IN Pin (1) 160 ton_min2 Minimum Positive Pulse Width at IN Pin for HG to Respond (2) 45 ton_min3 Minimum Positive Pulse Width at IN Pin for LG to Respond (3) 10 toff_min1 Minimum Negative Pulse Width at IN Pin for LG to Respond (4) 40 toff_min2 Minimum Negative Pulse Width at IN Pin for HG to Respond (5) 5 VIH_IN IN High Level Input Voltage When IN pin goes high from 0V VIL_IN IN Low Level Input Voltage When IN pin goes low from 5V (1) (2) (3) (4) (5) 4 V 25% IN Pin Leakage Current V V 0.8 55% Ileak_SYNC SYNC Pin Leakage Current Ileak_IN 4 2.5 VCC µA µA ns 55% 25% VCC If the positive pulse width at IN pin is below this value but above ton_min2, the pulse is internally stretched to ton_min1, so the HG width will be a constant value. If the positive pulse width at IN pin is below this value but above ton_min3, then HG stops responding while LG still responds to the pulse. If the positive pulse width at IN pin is below this value, the pulse will be completely ignored. Neither HG or LG will respond to it. If the negative pulse width at IN pin is below this value but above toff_min2, then LG stops responding while HG still responds. If the negative pulse width at IN pin is below this value, the pulse will be completely ignored. Neither HG or LG will respond to it. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2724A LM2724A www.ti.com SNVS242C – JUNE 2003 – REVISED MARCH 2013 TIMING DIAGRAM IN t2 t7 t8 t5 t1 LG t3 t4 t6 HG Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2724A 5 LM2724A SNVS242C – JUNE 2003 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C • 6 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 5 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2724A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM2724AMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2724 AM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of